CN112509615B - Flash memory, sensing circuit and method for determining storage state of storage unit - Google Patents
Flash memory, sensing circuit and method for determining storage state of storage unit Download PDFInfo
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- CN112509615B CN112509615B CN202011389897.3A CN202011389897A CN112509615B CN 112509615 B CN112509615 B CN 112509615B CN 202011389897 A CN202011389897 A CN 202011389897A CN 112509615 B CN112509615 B CN 112509615B
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- G—PHYSICS
- G11—INFORMATION STORAGE
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- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/143—Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels ; Switching between alternative supplies
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Abstract
The application relates to a flash memory, a sensing circuit and a method for determining a storage state of a storage unit. The sensing circuit comprises a first switch, a second switch, an isolating switch and a state determining unit, wherein the first switch comprises an input end connected to a system voltage source and an output end connected to the input end of the isolating switch; the isolating switch comprises an input end connected to the output end of the first switch, and an output end connected to a sensing node suitable for being connected with the storage unit to be detected; the second switch includes an input connected to the output of the isolation switch; and an output adapted to be connected to a string of memory cells including a memory cell to be tested; the state determination unit is connected to the sensing node and configured to determine a storage state of the memory cell to be detected according to a voltage of the sensing node.
Description
Technical Field
The present application relates to a memory device, and more particularly, to a flash memory, a sensing circuit in the flash memory, and a method of determining a memory state of a memory cell to be detected by the sensing circuit.
Background
A flash memory is a type of nonvolatile memory that can retain stored data without being powered. Compared with the conventional hard disk, the flash memory has the advantages of higher reading speed, lower power consumption, better shock resistance and the like, and is therefore applied more and more. For example, flash memory is commonly used in electronic systems such as personal computers, digital cameras, digital media players, digital recorders, vehicles, wireless devices, cellular telephones, and removable memory modules.
Flash memories may be classified into NOR flash memories and NAND flash memories. In NAND flash memory, for example, erase and write operations are required to a particular memory cell in use, and in these operations sensing circuitry is required to verify or read the state of the particular memory cell. A conventional sensing circuit first charges a sensing node connected to a bit line of a flash memory, and then detects a sensing voltage at the sensing node after being discharged through the bit line, so as to determine a storage state of a selected memory cell corresponding to the bit line. In such a sensing circuit, the sensing voltages corresponding to different memory states are relatively close, which may affect the accuracy of state identification.
The sensing circuit proposed later further separates the sensing voltages corresponding to different memory states by providing a boost driver, thereby improving the accuracy of the identification of the memory states. However, such a sensing circuit requires a separate N-well (N-well) at a precharge switch for precharging the sensing node to prevent current leakage due to boosting, which increases the design size of the sensing circuit, which is disadvantageous to the miniaturization trend of the flash memory. Further, in both schemes described above, the control signal of the precharge switch needs to be changed too many times while operating the other page buffers, which increases the power consumption of the sensing circuit.
Therefore, there is a need for a sensing circuit that can reduce design size and/or power consumption.
It should be appreciated that this background section is intended in part to provide a useful background for understanding the present technology and is not intended to imply that such matter has necessarily been prior art, as is known to those skilled in the art, prior to the present application.
Disclosure of Invention
One aspect of the present disclosure provides a sensing circuit including a first switch, a second switch, a disconnector, and a state determination unit, wherein the first switch includes an input connected to a system voltage source, and an output connected to the input of the disconnector; the isolating switch comprises an input end connected to the output end of the first switch, and an output end connected to a sensing node suitable for being connected with the storage unit to be detected; the second switch includes an input terminal connected to the output terminal of the isolation switch; and an output adapted to be connected to a string of memory cells including a memory cell to be tested; the state determination unit is connected to the sensing node and configured to determine a storage state of the memory cell to be detected according to a voltage of the sensing node.
According to one embodiment, the isolation switch is a low voltage N-type device.
According to one embodiment, the isolation switch is a low voltage nmos transistor.
According to one embodiment, the state determination unit is configured to determine the storage state of the memory cell to be detected by comparing the voltage of the sensing node with a reference voltage.
According to one embodiment, the sensing circuit further comprises a third switch comprising: an input terminal connected to an output terminal of the second switch; and an output connected to the string of memory cells.
According to one embodiment, a parasitic capacitance is formed between the output terminal of the third switch and ground.
According to one embodiment, the sensing circuit further comprises a fourth switch comprising: an input connected to a system voltage source; and an output terminal connected to an input terminal of the third switch.
According to one embodiment, the first switch, the second switch, the third switch, and the fourth switch are metal oxide semiconductor transistors.
According to one embodiment, the first switch is a pmos transistor.
According to one embodiment, the second switch, the third switch, and the fourth switch are nmos transistors.
According to one embodiment, the sensing circuit further comprises: a boost driver connected to the sensing node and configured to provide a boost voltage to the sensing node.
According to one embodiment, a parasitic capacitance is formed between the output of the isolation switch and the boost driver.
According to one embodiment, a parasitic capacitance is formed between the output terminal of the isolation switch and ground.
Another aspect of the present disclosure provides a method of determining a storage state of a memory cell to be detected by a sensing circuit, the sensing circuit including a first switch, a second switch, a disconnector, and a state determination unit, wherein an input of the first switch is adapted to receive a system voltage from a system voltage source, an output of the first switch is connected to an input of the disconnector, an output of the disconnector is connected to a sensing node and an input of the second switch, an output of the second switch is connected to a string of memory cells including the memory cell to be detected, the method comprising: turning on the first switch and the isolation switch at a first time point to charge the sensing node with the system voltage; disconnecting the first switch and the disconnector at a second point in time; turning on the second switch at a third time point so that the sensing node is electrically connected with the memory cell string; opening the second switch at a fourth time point; and determining the storage state of the storage unit to be detected according to the voltage of the sensing node after the fourth time point.
According to one embodiment, the method further comprises: applying the boosted voltage to the sensing node at a fifth time point between the second time point and the third time point, and decreasing the boosted voltage at a sixth time point after the fourth time point; and determining the storage state of the storage unit to be detected according to the voltage of the sensing node after the sixth time point.
According to one embodiment, the sensing circuit further comprises a boost driver connected to the sensing node, the boost driver being arranged to apply a boost voltage to the sensing node.
According to one embodiment, a parasitic capacitance is formed between the output of the isolation switch and the boost driver.
According to one embodiment, the isolation switch is a low voltage N-type device.
According to one embodiment, the isolation switch is a low voltage nmos transistor.
According to one embodiment, determining the storage state of the memory cell to be tested comprises: the memory state of the memory cell to be detected is determined by comparing the voltage of the sensing node with a reference voltage.
According to one embodiment, the sensing circuit further comprises a third switch comprising: an input terminal connected to an output terminal of the second switch; and an output connected to the string of memory cells.
According to one embodiment, a parasitic capacitance is formed between the output terminal of the third switch and ground.
According to one embodiment, the sensing circuit further comprises a fourth switch comprising: an input terminal connected to a system voltage source; and an output terminal connected to the input terminal of the third switch.
According to one embodiment, the first switch, the second switch, the third switch, and the fourth switch are metal oxide semiconductor transistors.
According to one embodiment, the first switch is a pmos transistor.
According to one embodiment, the second switch, the third switch, and the fourth switch are nmos transistors.
According to one embodiment, a parasitic capacitance is formed between the output terminal of the isolation switch and ground.
Yet another aspect of the present disclosure provides a flash memory including: a plurality of memory cells arranged in an array; and a plurality of sensing circuits as described above respectively connected to each column of the plurality of memory cells.
Drawings
The above and other advantages and features of the present disclosure will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings.
FIG. 1 shows a schematic diagram of a flash memory according to an embodiment of the present disclosure.
FIG. 2 shows a schematic diagram of a sensing circuit according to an embodiment of the present disclosure.
FIG. 3 illustrates a control signal timing diagram for the sensing circuit of FIG. 2, according to an embodiment of the present disclosure.
FIG. 4 shows a flow diagram of a method for operating the sensing circuit of FIG. 2, according to an embodiment of the present disclosure.
FIG. 5 shows a schematic diagram of a sensing circuit according to another embodiment of the present disclosure.
FIG. 6 illustrates a control signal timing diagram for the sensing circuit of FIG. 5, according to an embodiment of the present disclosure.
FIG. 7 shows a flow diagram of a method for operating the sensing circuit of FIG. 5, according to an embodiment of the present disclosure.
Detailed Description
Exemplary embodiments of the present invention will now be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.
It will also be understood that when an element or layer is referred to as being "on," "connected to" or "coupled to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers may be present. When an element or layer is referred to as being "directly on," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. For purposes of this specification, the term "connected" may refer to physical, electrical, and/or fluid connections, with or without intervening elements.
Like reference numerals refer to like elements throughout the specification. In the drawings, the thickness of layers and regions are exaggerated for clarity.
Although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms may be used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of one or more embodiments. The description of an element as a "first" element may not require or imply the presence of a second element or other elements. The terms "first," "second," and the like may also be used herein to distinguish between different classes or groups of elements. For the sake of simplicity, the terms "first", "second", etc. may denote "first class (or first group)", "second class (or second group)", etc., respectively.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, regions, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, regions, steps, operations, elements, components, and/or groups thereof.
Furthermore, relative terms, such as "lower" or "bottom" and "upper" or "top," may be used herein to describe one element's relationship to another element as illustrated in the figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. In an exemplary embodiment, when the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. Thus, the exemplary term "lower" can encompass both an orientation of "lower" and "upper," depending on the particular orientation of the figure. Similarly, when the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. Thus, the exemplary terms "below" or "beneath" can encompass both an orientation of above and below.
As used herein, "about" or "approximately" includes the stated value as well as the average value within an acceptable range of deviation of the specified value as determined by one of ordinary skill in the art in view of the measurement in question and the error associated with the measurement of the specified quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present invention and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
Some example embodiments are described and illustrated in the accompanying drawings with respect to functional blocks, units and/or modules as is conventional in the art. Those skilled in the art will appreciate that the blocks, units, and/or modules are physically implemented with electrical (or optical) circuitry, such as logic, discrete components, microprocessors, hardwired circuitry, memory elements, wiring connectors, and so forth, which may be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Where the blocks, units, and/or modules are implemented by a microprocessor or other similar hardware, they may be programmed and controlled by software (e.g., microcode) to perform the various functions discussed herein, and may optionally be driven by firmware and/or software. It is also contemplated that each block, unit, and/or module may be implemented by dedicated hardware, or as a combination of dedicated hardware for performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) for performing other functions. In addition, each block, unit and/or module in some example embodiments may be physically separated into two or more interactive and discrete blocks, units and/or modules without departing from the scope of the inventive concept. Furthermore, the blocks, units and/or modules in some example embodiments may be physically combined into more complex blocks, units and/or modules without departing from the scope of the inventive concept.
FIG. 1 shows a schematic diagram of a flash memory 100 according to an embodiment of the present disclosure. The flash memory 100 includes M × N memory cells C (1, 1) to C (M, N), where M and N are positive integers. For example, in a NAND flash memory, memory cells (e.g., C (1, 1) to C (M, 1)) in the same column may be connected in series to the same bit line (e.g., bit line BL 1), one end of the series-connected memory cell string may be connected to the bit line via bit line transistor Tb, and the other end may be connected to the source line via source line transistor Ts. Each bit line connects a corresponding memory cell string to the sensing circuit 200. Memory cells in the same row (e.g., C (M, 1) through C (M, N)) may be connected to the same word line (e.g., word line WLM). In operation, a memory cell string in which a memory cell to be detected is located is selected by the bit line transistor Tb and/or the source line transistor Ts, and a memory cell to be detected in the memory cell string is selected by applying a read voltage to the word line, and then a voltage or a current on the corresponding bit line is read by the sense circuit 200 to determine a memory state of the memory cell to be detected. Taking the read memory cell C (M, N) as an example, a read voltage is applied to the word line WLM by turning on the bit line transistor Tb and the source line transistor Ts corresponding to the bit line BLN, and a pass voltage is applied to the other word lines to select the memory cell C (M, N) to be detected, and then the voltage or current on the bit line BLN is read by the sensing circuit 200 to determine the memory state (e.g., erased state/programmed state, or "1"/"0") of the selected memory cell.
Fig. 2 shows a schematic diagram of a sensing circuit 200 according to an embodiment of the present disclosure.
As shown in FIG. 2, a sensing circuit 200 according to an embodiment of the present disclosure may include a first switch T 1 A second switch T 2 Isolating switch T iso And a state determination unit SA. First switch T 1 Can be connected directly or indirectly to a system voltage source V DD And a first switch T 1 Can be connected to the isolating switch T iso To the input terminal of (1). Isolating switch T iso Is connectable to a first switch T 1 And isolating the switch T iso May be connected to the sensing node SO, the state determination unit SA and the second switch T 2 To the input terminal of (1). A second switch T 2 May be connected to a bitline BL of a certain memory cell string in the flash memory. For example, the second switch T 2 Can pass through a third switch T 3 A bit line BL connected to a certain memory cell string in the flash memory. In some embodiments, the sensing circuit 200 may further include a fourth switch T 4 Fourth switch T 4 Can be connected directly or indirectly to a system voltage source V DD And a fourth switch T 4 May be connected to the second switch T 2 And a third switch T 3 To the input terminal of (1).
First switch T included in sensing circuit 200 1 A second switch T 2 A third switch T 3 And a fourth switch T 4 May be a Metal Oxide Semiconductor (MOS) transistor. In some embodiments, the first switch T 1 Can be a P-type MOS transistor, an isolation switch T iso A second switch T 2 And a third switch T 3 And a fourth switch T 4 May be an N-type MOS transistor. The state determination unit SA may include a MOS transistor, and a gate thereof may be connected to the sensing node SO. However, the state determination unit SA is not limited thereto, but may further include other devices such as a latch. In this case, the first switch T 1 The input terminal of (A) can be the source electrode of a transistor, a first switch T 1 The gate of the first switch T1 is used to receive a control signal Prechb that controls its on and off; isolating switch T iso Can be the source of a transistor, a disconnector T iso The output terminal of (2) can be the drain electrode of a transistor and an isolating switch T iso The gate of the transistor is used for receiving a control signal Prech _ isob for controlling the on and off of the transistor; a second switch T 2 The input terminal of (A) can be the source electrode of the transistor, the second switch T 2 The output terminal of (1) can be the drain electrode of the transistor, and the second switch T 2 The gate of (b) is used for receiving a control signal Vsoblk for controlling the on and off of the gate; third switch T 3 The input terminal of (A) can be the source electrode of the transistor, and the third switch T 3 The output terminal of (A) can be the drain electrode of the transistor, and the third switch T 3 The grid of the grid is used for receiving a control signal Vlbias for controlling the on and off of the grid; fourth switch T 4 May be the source of a transistor, a fourth switch T 4 May be the drain of a transistor, a fourth switch T 4 The gate of which is used to receive a control signal Vblclamp that controls its turn-on and turn-off.
In the sensing circuit 200 according to the present embodiment, at the sensing node SO or the first switch T 1 May form a parasitic capacitance C between the output terminal of (2) and the ground SO Between bit line BL and groundTo form a parasitic capacitance C bl 。
A method of operating the sensing circuit shown in fig. 2 will be described with reference to fig. 3 and 4.
FIG. 3 illustrates a control signal timing diagram for the sensing circuit of FIG. 2 according to an embodiment of the present disclosure; FIG. 4 shows a flow diagram of a method for operating the sensing circuit of FIG. 2, according to an embodiment of the present disclosure.
Referring to fig. 2 to 4, in operation of the sensing circuit 200, according to the method 400, first, at step S401, the first switch T is turned on 1 And a disconnecting switch T iso To charge the sensing node SO with the system voltage. For example, at a first point in time t 1 So that the first switch T 1 And a disconnecting switch T iso Is turned on to charge the sensing node SO with the system voltage, at which time the second switch T 2 In the off state (also referred to as "open state"). At the first switch T 1 Is a P-type MOS transistor, an isolating switch T iso And a second switch T 2 In the case of an N-type MOS transistor, as shown in fig. 3, the first switch T may be connected 1 Applies a low-level control signal Prechb to the gate of the isolating switch T iso Applies a high-level control signal Prech _ isob to the gate of the first switch T, and applies a high-level control signal to the second switch T 2 The gate of the first switch T is applied with the control signal Vsoblk of low level to make the first switch T 1 And a disconnecting switch T iso Is turned on and the second switch T is turned on 2 In the off state (also referred to as "open state"). Conducting first switch T 1 And a disconnecting switch T iso Such that the sensing node SO and the system voltage source V DD Is electrically connected and the sensing node SO is charged to the system voltage after a period of time has elapsed.
Then, at step S402, the first switch T is turned off 1 And a disconnecting switch T iso . For example, at a second time point t 2 So that the first switch T 1 And a disconnecting switch T iso And (5) disconnecting. At the first switch T 1 Is a P-type MOS transistor, an isolation switch T iso In the case of an N-type MOS transistor, as shown in FIG. 3, the first switch T can be activated 1 Application of gridHigh level control signal Prechb, and to the isolating switch T iso Applies a control signal Prech _ isob of a low level to make the first switch T 1 And a disconnecting switch T iso And (4) disconnecting. At this time, the voltage of the sensing node is the system voltage.
At step S403, the second switch T is turned on 2 SO that the sensing node SO is electrically connected to the memory cell string. For example, at a third point in time t 3 So that the second switch T 2 And conducting. At the second switch T 2 In the case of an N-type MOS transistor, as shown in fig. 3, the second switch T may be provided 2 Applies a high-level control signal Vsoblk to make the second switch T 2 And conducting. At this time, the voltage of the sensing node SO may vary according to the memory state of the memory cell to be detected selected by the word line in the memory cell string. For example, the sensing node SO can be discharged through the memory cell string as the sensing current Isense is generated, and in the process, the voltage of the sensing node SO is also reduced.
At step S404, the second switch T is turned off 2 . For example, the sensing node SO may be discharged for a period of time, and then at the fourth time point t 4 So that the second switch T 2 And (5) disconnecting. At the second switch T 2 In the case of an N-type MOS transistor, as shown in fig. 3, the second switch T may be provided 2 A gate of the first switch T applies a control signal Vsoblk of a low level to make the second switch T 2 And (5) disconnecting. At this time, the sensing node SO is electrically disconnected from the memory cell string.
Since the variation of the voltage of the sensing node SO may be different according to the storage state of the memory cell to be detected, the storage state of the memory cell to be detected may be determined by detecting the voltage at the sensing node SO after the sensing node SO is discharged at step S405. The detection may be at a fourth point in time t 4 And then by the state determination unit SA. In some embodiments, the storage state of the memory cell to be detected can be determined by comparing the voltage of the sensing node SO with a reference voltage. For example, when the voltage of the sensing node SO is higher than the reference voltage, it may be determined that the memory cell is in a programmed state or "0"When the voltage of the sensing node SO is lower than the reference voltage, it may be determined that the memory cell is in an erased state or "1". For the case where the state determination unit SA includes a MOS transistor, the gate threshold voltage of the MOS transistor may be used as the reference voltage, and the storage state of the memory cell to be detected may be determined by the switching state of the MOS transistor in the state determination unit SA.
The sensing circuit 200 includes a third switch T 3 And a fourth switch T 4 In the case of (3), the third switch T 3 And a fourth switch T 4 Can be controlled by control signals Vblclamp and vbibias, respectively, in the course of which the third switch T is switched 3 And a fourth switch T 4 May be in a conducting state. At the above step S401, C is charged to the system voltage capacitance while the sensing node SO is charged bl Is also charged, e.g., to Vvbias-Vth, where Vth is the third switch T 3 The threshold voltage of (2).
FIG. 5 shows a schematic diagram of a sensing circuit according to another embodiment of the present disclosure. Compared to the sensing circuit 200 shown in fig. 2, the sensing circuit 500 shown in fig. 5 is different in that a Boost driver Boost is provided at the sensing node SO, which is connected to the sensing node SO and configured to provide a Boost voltage to the sensing node SO. A parasitic capacitance C may be formed between the sensing node SO or the output terminal of the first switch and the Boost driver Boost SO 。
FIG. 6 illustrates a control signal timing diagram for the sensing circuit of FIG. 5, according to an embodiment of the present disclosure; FIG. 7 shows a flow diagram of a method for operating the sensing circuit of FIG. 5, according to an embodiment of the present disclosure.
A method of operating the sensing circuit shown in fig. 5 will be described with reference to fig. 6 and 7.
Referring to fig. 4 to 7, in operation of the sensing circuit 500, according to the method 700, first, at step S701, the first switch T is turned on 1 And a disconnecting switch T iso To charge the sensing node OS with the system voltage. For example, at a first point in time t 1 So that the first switch T 1 And a disconnecting switch T iso Is conducted to use the system voltageCharging the sensing node SO while the second switch T is on 2 In an off state (also referred to as an "open state"). At the first switch T 1 Is a P-type MOS transistor, an isolation switch T iso And a second switch T 2 In the case of an N-type MOS transistor, as shown in FIG. 6, the first switch T can be turned on 1 Applies a low-level control signal Prechb to the gate of the isolating switch T iso Applies a high-level control signal Prech _ isob to the gate of the first switch T, and applies a high-level control signal to the second switch T 2 A low level control signal Vsoblk is applied to the gate of the first switch T, so that the first switch T is turned on 1 And a disconnecting switch T iso Is turned on and the second switch T is turned on 2 In an off state (also referred to as an "open state"). Conducting first switch T 1 And a disconnecting switch T iso SO that the sensing node SO and the system voltage source V DD Is electrically connected and the sensing node SO is charged to the system voltage after a period of time has elapsed.
Then, at step S702, the first switch T is turned off 1 And a disconnecting switch T iso . For example, at a second point in time t 2 So that the first switch T 1 And a disconnecting switch T iso And (4) disconnecting. At the first switch T 1 Is a P-type MOS transistor, an isolating switch T iso In the case of an N-type MOS transistor, as shown in fig. 6, the first switch T may be turned on 1 Applies a high-level control signal Prechb to the gate of the isolation switch T and applies the high-level control signal Prechb to the gate of the isolation switch T iso Applies a control signal Prech _ isob of a low level to make the first switch T 1 And a disconnecting switch T iso And (5) disconnecting. At this time, the voltage of the sensing node is the system voltage.
At step S703, a boost voltage is applied to the sense node SO. For example, as shown in FIG. 6, at a second time point t 2 At a fifth subsequent point in time t 5 The Boost driver Boost may start to output the output voltage Vboost of a high level such that the voltage at the sensing node SO is boosted.
At step S704, the second switch T is turned on 2 SO that the sensing node SO is electrically connected to the memory cell string. For example, at a third point in time t 3 So that the second switch T 2 And conducting. At the second placeSwitch T 2 In the case of an N-type MOS transistor, as shown in FIG. 6, a second switch T may be provided 2 Gate of the first switch T is raised to a high level to enable the second switch T 2 And conducting. At this time, the voltage of the sensing node SO may vary according to the memory state of the memory cell to be detected selected by the word line in the memory cell string. For example, the sensing node SO may be discharged through the memory cell string 210 as the sensing current Isense is generated, and the voltage of the sensing node SO is also decreased in the process.
At step S705, the second switch T is turned off 2 . For example, the sensing node SO may be discharged for a period of time, and then at the fourth time point t 4 So that the second switch T 2 And (4) disconnecting. At the second switch T 2 In the case of an N-type MOS transistor, as shown in FIG. 6, the second switch T can be used 2 A gate of the first switch T applies a control signal Vsoblk of a low level to make the second switch T 2 And (5) disconnecting. At this time, the sensing node SO is electrically disconnected from the memory cell string 210.
At step S706, the boost voltage is decreased. For example, as shown in FIG. 6, at a fourth time point t 4 At a sixth later point in time t 6 The Boost driver Boost may lower the output voltage Vboost, for example, by Δ V, or change to 0.
Then, the storage state of the memory cell to be detected may be determined by detecting the voltage at the sensing node SO at step S707. The detection may be at a fourth point in time t 6 And then by the state determination unit SA. In some embodiments, the storage state of the memory cell can be determined by comparing the voltage of the sensing node SO with a reference voltage. For example, when the voltage of the sensing node SO is higher than the reference voltage, it may be determined that the memory cell is in a programmed state or "0", and when the voltage of the sensing node SO is lower than the reference voltage, it may be determined that the memory cell is in an erased state or "1". In the case where the state determination unit SA includes a MOS transistor, the gate threshold voltage thereof may be used as the reference voltage, and the storage state of the memory cell may be determined by the switching state of the MOS transistor in the state determination unit SA.
The sensing circuit 500 includes a third switch T 3 And a fourth switch T 4 In the case of (2), the third switch T 3 And a fourth switch T 4 Can be controlled by control signals Vblclamp and vbibias, respectively, in the course of which the third switch T is switched 3 And a fourth switch T 4 May be in an on state. At the above step S701, C is performed while the sensing node SO is charged to the system voltage capacitance bl Is also charged, e.g., to Vvbias-Vth, where Vth is the third switch T 3 The threshold voltage of (2).
The sensing circuit 500 according to the above embodiment increases the voltage at the sensing node by the boost driver during sensing, which allows a larger separation space between the voltages at the sensing node SO corresponding to different memory states of the memory cell to be detected, which can improve the reading accuracy. Meanwhile, the sensing circuit 500 is provided with the isolating switch T iso Which when boosting with a boost driver will switch the first switch T 1 Is isolated from the sensing node, so that current leakage, which may occur due to the voltage at the sensing node being higher than the system voltage, can be prevented, and the first switch T can be omitted 1 A separately provided N-well, which can reduce the design size of the sensing circuit.
At the conclusion of the detailed description, those skilled in the art will appreciate that many variations and modifications may be made to the preferred embodiments without substantially departing from the principles of the present invention. Accordingly, the disclosed preferred embodiments of the invention are used in a generic and descriptive sense only and not for purposes of limitation.
Claims (26)
1. A sensing circuit comprising a first switch, a second switch, a disconnector, a state determining unit, and a boost driver, wherein:
the first switch includes:
an input terminal connected to a system voltage source; and
an output connected to an input of the isolation switch;
the disconnecting switch comprises:
an input connected to an output of the first switch; and
an output connected to a sensing node adapted to connect with a memory cell to be sensed;
the second switch includes:
an input connected to an output of the isolation switch; and
an output adapted to be connected to a memory cell string comprising said memory cells to be tested,
the state determining unit is connected to the sensing node and configured to determine a storage state of the memory cell to be detected according to a voltage of the sensing node, an
The boost driver is connected to the sense node and configured to provide a boost voltage that boosts the voltage of the charged sense node,
wherein the isolation switch is configured to open at least during the time that the boost driver is providing the boost voltage.
2. The sensing circuit of claim 1, wherein the isolation switch is a low voltage N-type device.
3. The sensing circuit of claim 2, wherein the isolation switch is a low voltage nmos transistor.
4. The sensing circuit as claimed in claim 1, wherein the state determining unit is configured to determine the storage state of the memory cell to be detected by comparing the voltage of the sensing node with a reference voltage.
5. The sensing circuit of claim 1, wherein the sensing circuit further comprises a third switch comprising:
an input connected to an output of the second switch; and
an output connected to the string of memory cells.
6. The sensing circuit of claim 5, wherein a parasitic capacitance is formed between the output of the third switch and ground.
7. The sensing circuit of claim 5, wherein the sensing circuit further comprises a fourth switch comprising:
an input connected to the system voltage source; and
an output connected to an input of the third switch.
8. The sensing circuit of claim 7, wherein the first switch, the second switch, the third switch, and the fourth switch are metal oxide semiconductor transistors.
9. The sensing circuit of claim 8, wherein the first switch is a P-type metal oxide semiconductor transistor.
10. The sensing circuit of claim 8, wherein the second, third, and fourth switches are nmos transistors.
11. The sensing circuit as claimed in claim 10, wherein a parasitic capacitance is formed between the output of the isolation switch and the boost driver.
12. The sensing circuit as claimed in claim 1, wherein a parasitic capacitance is formed between the output terminal of the isolation switch and ground.
13. A method of determining a memory state of a memory cell to be detected by a sensing circuit, the sensing circuit comprising a first switch, a second switch, a disconnector and a state determination unit, wherein an input of the first switch is adapted to receive a system voltage from a system voltage source, an output of the first switch is connected to an input of the disconnector, an output of the disconnector is connected to a sensing node and an input of the second switch, an output of the second switch is connected to a string of memory cells comprising the memory cell to be detected, the method comprising:
turning on the first switch and the isolation switch at a first time point to charge the sensing node with the system voltage;
opening the first switch and the disconnector at a second point in time;
applying a boosted voltage to the sensing node at a fifth point in time between the second point in time and the third point in time to boost the voltage of the sensing node;
turning on the second switch at a third time point such that the sensing node is electrically connected with the memory cell string;
opening the second switch at a fourth point in time;
decreasing the boosted voltage at a sixth time point after the fourth time point; and
and determining the storage state of the storage unit to be detected according to the voltage of the sensing node after the sixth time point.
14. The method of claim 13, the sensing circuit further comprising a boost driver connected to the sensing node, the boost driver configured to apply the boost voltage to the sensing node.
15. The method of claim 14, wherein a parasitic capacitance is formed between the output of the isolation switch and the boost driver.
16. The method of claim 13, wherein the isolation switch is a low voltage N-type device.
17. The method of claim 16, wherein the isolation switch is a low voltage nmos transistor.
18. The method of claim 13, wherein determining the storage state of the memory cell to be tested comprises:
determining a storage state of the memory cell to be detected by comparing a voltage of the sensing node with a reference voltage.
19. The method of claim 13, the sensing circuit further comprising a third switch, the third switch comprising:
an input connected to an output of the second switch; and
an output connected to the string of memory cells.
20. The method of claim 19, wherein a parasitic capacitance is formed between the output of the third switch and ground.
21. The method of claim 19, the sensing circuit further comprising a fourth switch comprising:
an input connected to the system voltage source; and
an output connected to an input of the third switch.
22. The method of claim 21, wherein the first switch, the second switch, the third switch, and the fourth switch are metal oxide semiconductor transistors.
23. The method of claim 22, wherein the first switch is a pmos transistor.
24. The method of claim 22, wherein the second switch, the third switch, and the fourth switch are nmos transistors.
25. The method of claim 13, wherein a parasitic capacitance is formed between an output terminal of the isolation switch and ground.
26. A flash memory, comprising:
a plurality of memory cells arranged in an array; and
a plurality of the sensing circuits of any of claims 1-12, respectively connected to each column of memory cells of the plurality of memory cells.
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