CN112491417B - Analog-to-digital converter - Google Patents

Abstract

The invention discloses an analog-to-digital converter for receiving an analog input signal and generating a digital code. The analog-to-digital converter comprises a delta-sigma modulator, a down-conversion filter and a detection circuit. The delta-sigma modulator comprises a loop filter, a quantizer and a digital-to-analog converter. The loop filter is used for receiving the analog input signal. The quantizer is coupled to the loop filter for quantizing an output of the loop filter to generate a digital output signal. The digital-to-analog converter is coupled to the quantizer and the loop filter. The down-conversion filter is coupled to the delta-sigma modulator for converting the digital output signal into the digital code. The detecting circuit is coupled to the delta-sigma modulator for detecting a node voltage of the delta-sigma modulator and generating a control signal. The control signal is used for controlling a feedback path of the loop filter, the quantizer, the sigma-delta modulator and/or a feedforward path of the sigma-delta modulator.

Description

Analog-to-digital converter

Technical Field

The present invention relates to analog-to-digital converter (ADC) converters, and more particularly to ADCs based on delta-sigma modulators.

Background

A sigma-delta modulator (SDM) is a common means of implementing an ADC, however, the signal applied to the sigma-delta modulator typically has the property that an out-of-band (out-of-band) signal with an amplitude (magnitude) greater than the in-band signal is present outside the signal bandwidth (signal bandwidth) of the in-band signal, which can interfere with the out-of-band signal of the sigma-delta modulator, which can be referred to as an image or a blocker. Therefore, detection and suppression of these unnecessary out-of-band signals is an important issue in the art.

Disclosure of Invention

In view of the shortcomings of the prior art, an objective of the present invention is to provide an ADC for improving the stability of the ADC.

The invention discloses an analog-digital converter, which is used for receiving an analog input signal and generating a digital code. The analog-to-digital converter comprises a delta-sigma modulator, a down-conversion filter and a detection circuit. The delta-sigma modulator comprises a loop filter, a quantizer and a digital-to-analog converter. The loop filter is used for receiving the analog input signal. The quantizer is coupled to the loop filter for quantizing an output of the loop filter to generate a digital output signal. The digital-to-analog converter is coupled to the quantizer and the loop filter. The down-conversion filter is coupled to the delta-sigma modulator for converting the digital output signal into the digital code. The detecting circuit is coupled to the delta-sigma modulator for detecting a node voltage of the delta-sigma modulator and generating a control signal. The control signal is used for controlling a feedback path of the loop filter, the quantizer, the sigma-delta modulator and/or a feedforward path of the sigma-delta modulator.

The invention also discloses an analog-digital converter for receiving an analog input signal and generating a digital code. The analog-to-digital converter comprises a delta-sigma modulator, a down-conversion filter, a detection circuit and a control circuit. The delta-sigma modulator comprises a loop filter, a quantizer and a digital-to-analog converter. The loop filter is used for receiving the analog input signal. The quantizer is coupled to the loop filter for quantizing an output of the loop filter to generate a digital output signal. The digital-to-analog converter is coupled to the quantizer and the loop filter. The down-conversion filter is coupled to the delta-sigma modulator for converting the digital output signal into the digital code. The detecting circuit is coupled to the delta-sigma modulator for detecting a node voltage of the delta-sigma modulator and generating a detection result. The control circuit is coupled to the detection circuit and used for generating a control signal according to the detection result. The control signal is used for controlling a feedback path of the loop filter, the quantizer, the sigma-delta modulator and/or a feedforward path of the sigma-delta modulator.

The ADC of the invention detects the node voltage of the delta-sigma modulator by using the detection circuit, and adaptively adjusts the ADC according to the detection result so as to improve the stability of the ADC and reduce the power consumption. Compared with the prior art, the ADC of the invention can detect and inhibit the unnecessary out-of-band signals, so that the operation of the ADC is more stable.

The features, operations and technical effects of the present invention will be described in detail below with reference to examples of embodiments shown in the accompanying drawings.

Drawings

FIG. 1 is a circuit diagram of an ADC according to an embodiment of the present invention;

FIG. 2 is a circuit diagram of a resonator according to an embodiment of the invention;

FIG. 3 is a circuit diagram of a clamping circuit according to an embodiment of the invention;

FIG. 4 is a circuit diagram of an ADC according to another embodiment of the present invention;

FIG. 5 is a functional block diagram of a detection circuit according to an embodiment of the invention, and

FIG. 6 is a functional block diagram of a detection circuit according to another embodiment of the present invention.

Symbol description

10. 15A/D converter

100. Low pass filter

200. Delta-sigma modulator

210. Loop filter

212A, 212b, 500 resonator

214. 240 Switch

220. Quantizer

230. Digital-to-analog converter

245. Feedback path

250. Impedance circuit

255. Feedforward path

300A, 300b, 300c, 300d detection circuit

400A, 400b, 400c, 400d clamping circuit

900. Down-conversion filter

Cd 1-Cd 4 and Cdx control signals

S1-S10, S control signal

Vin analog input signal

Dout digital output signal

D digital code

510. 520 Integrator

512. 522 Operational amplifier

530. Impedance of

532. Variable resistor

412. 414, 416, 418 Transistors

N1, N2 node

610A, 610b integrator or op amp

700. Control circuit

800. Memory device

DR 1-DR 4, DRx, DR detection results

310. Low-resolution analog-to-digital converter

320. Regional control circuit

330. Comparator with a comparator circuit

Voltage of Vn node

Detailed Description

Technical terms used in the following description refer to terms commonly used in the art, and as used in the specification, some terms are described or defined, and the explanation of the some terms is based on the description or the definition of the specification.

The present disclosure includes an ADC based on a sigma delta modulator. Since some of the components included in the ADC of the present invention may be known components alone, details of the known components will be omitted from the following description without affecting the full disclosure and operability of the device invention.

Fig. 1 is a circuit diagram of an ADC according to an embodiment of the invention. The ADC 10 is a delta-sigma modulator-based ADC, and includes a low-pass filter (low-PASS FILTER, LPF) 100, an SDM 200, a down-conversion filter (decimation filter) 900, a plurality of detection circuits 300 (including a detection circuit 300a, a detection circuit 300b, a detection circuit 300c, and a detection circuit 300d in the example of fig. 1), and a plurality of clamp circuits 400 (including a clamp circuit 400a, a clamp circuit 400b, a clamp circuit 400c, and a clamp circuit 400d in the example of fig. 1). The low-pass filter 100 low-pass filters the analog input signal Vin, and the SDM 200 converts the low-pass filtered analog input signal Vin into a digital output signal Dout, which is processed by the down-filter 900 to generate the digital code D. The digital code D is the output of the ADC 10. The operation of the down-conversion filter 900 is well known to those skilled in the art and will not be described in detail.

SDM 200 includes loop filter 210, quantizer 220, digital-to-analog converter (DAC) 230, switch 240, and impedance circuit 250. Loop filter 210 receives and filters a low-pass filtered analog input signal Vin and includes resonator 212a, resonator 212b, and switch 214. The quantizer 220 is coupled to the loop filter for quantizing the output of the loop filter 210 to generate a digital output signal Dout. Switch 240 is coupled between DAC 230 and loop filter 210. The principle of operation of SDM 200 is well known to those skilled in the art and will not be described in detail. The order of loop filter 210 in fig. 1 is merely exemplary and is not intended to limit the present invention.

Resonator 212a is controlled by control signal S1, resonator 212b is controlled by control signal S2, switch 214 is controlled by control signal S3, quantizer 220 is controlled by control signal S4, switch 240 is controlled by control signal S5, impedance circuit 250 is controlled by control signal S6, and clamp circuits 400a through 400d are controlled by control signals S7 through S10, respectively.

The detection circuit 300 detects a number of node voltages of the SDM 200 and generates a control signal Cdx (in the example of FIG. 1, x is an integer and 1.ltoreq.x.ltoreq.4). More specifically, the detection circuit 300a detects the voltage at the input of the SDM 200 (i.e., the output of the low-pass filter 100, the input of the resonator 212 a) and generates the control signal Cd1, the detection circuit 300b detects the voltage at the internal node of the resonator 212a and generates the control signal Cd2, the detection circuit 300c detects the output voltage of the resonator 212a (i.e., the input voltage of the resonator 212 b) and generates the control signal Cd3, and the detection circuit 300d detects the output voltage of the resonator 212b (i.e., the input voltage of the quantizer 220) and generates the control signal Cd4. The control signal Cdx may be used to control (1) the loop filter 210, (2) the quantizer 220, (3) the feedback path 245 of the SDM 200, (4) the feed-forward path 255 of the SDM 200, and (5) the clamp 400. The various control scenarios described above are discussed separately below.

Context (1) control signal Cdx controls loop filter 210. Referring to fig. 2, fig. 2 is a circuit diagram of a resonator 500 according to an embodiment of the invention. Resonator 500 includes integrator 510, integrator 520, and impedance 530. Resonator 212a and resonator 212b of fig. 1 may be implemented as resonator 500. The integrator 510 and the integrator 520 each include a resistor R, a capacitor C, and an operational amplifier 512 or 522, and the connection modes of the elements are shown in fig. 2, and the operation principles of the integrator 510 and the integrator 520 are well known to those skilled in the art, so that the description thereof is omitted. Impedance 530 is located in the feedback path of resonator 500 and has one end coupled to the output of op-amp 522 of integrator 520 and the other end coupled to one of the inputs of op-amp 512 of integrator 510. Impedance 530 includes variable resistor 532. Integrator 510 and/or integrator 520 may operate in a passive mode under the control of control signal S1. More specifically, the control signal S1 may turn off the operational amplifier 512 and/or the operational amplifier 522, such that the integrator 510 and the integrator 520 only leave passive components (i.e., the resistor R and the capacitor C). Turning off op-amp 512 and/or op-amp 522 helps to stabilize the circuit when the mirror or blocker in SDM 200 is too large. In addition, turning off the op-amp 512 and/or the op-amp 522 has the technical effect of saving power.

Returning to fig. 1, the control signal Cdx may also reduce the order of the loop filter 210. More specifically, when the switch 214 is controlled by the control signal S3 to be turned on, the resonator 212a is bypassed (bypass), which is equivalent to tuning down the order of the loop filter 210 by two orders. Bypass resonator 212a is equivalent to controlling resonator 212a to be inactive. Reducing the order of loop filter 210 helps stabilize the circuit when the image or blockage in SDM 200 is too large. In addition, reducing the order of the loop filter 210 has the technical effect of saving power.

Context (2) control signal Cdx controls the input working range of quantizer 220. More specifically, the detection circuit 300c may measure the output swing (output swing) of the resonator 212a, thereby turning on/off the comparator in the quantizer 220, or adjusting the binary search period (binary SEARCH CYCLE) of the quantizer 220. For example, when the detection circuit 300c detects that the output swing of the resonator 212a is smaller than the first preset value (representing that the most significant bit of the digital output signal Dout may be logic 0) or larger than the second preset value (representing that the most significant bit of the digital output signal Dout may be logic 1) (the second preset value is larger than the first preset value), the control signal S4 turns off the comparator corresponding to the higher bit in the quantizer 220 or controls the quantizer 220 to skip the previous period corresponding to the higher bit in the binary search. In other words, the input working range of the quantizer 220 may be the number of active comparators or the number of cycles of the binary search actually performed.

In case (3), the control signal Cdx controls the switch 240 to couple the output of DAC 230 to the input of resonator 212a or the input of resonator 212 b. When resonator 212a is bypassed, control signal Cdx may conformally control switch 240 to couple the output of DAC 230 to the input of resonator 212 b. When resonator 212a is not bypassed, control signal Cdx may control switch 240 to couple the output of DAC 230 to the input of resonator 212a or the input of resonator 212 b.

Context (4) control signal Cdx controls impedance circuit 250. The feedforward path 255 connects the input of the loop filter 210 and the output of the loop filter 210, and includes an impedance circuit 250. The impedance of the impedance circuit 250 is adjustable (e.g., the impedance circuit 250 includes a variable resistor and/or a variable capacitor), and the control signal S6 adjusts the feedforward of the SDM 200 by adjusting the equivalent impedance of the impedance circuit 250.

In case (5), the control signal Cdx adjusts the clamping voltage of the clamping circuit 400 to limit the voltage value of the corresponding node, thereby inhibiting mirroring or blocking and stabilizing the circuit.

Referring to fig. 2, the detection circuit 300b is coupled to the output end of the integrator 510 and the input end of the integrator 520, and is configured to detect the voltage of the internal node of the resonator 500 to generate the control signal Cd2. The clamping circuit 400b is coupled to the output terminal of the integrator 510 and the input terminal of the integrator 520, and is used for limiting the node voltage of the output terminal of the integrator 510 and the input terminal of the integrator 520. Note that the detection circuit 300 and the clamp circuit 400 electrically connected to the internal nodes of the resonator 212b are not shown in fig. 1 for simplicity, however, one skilled in the art can implement the detection circuit 300 and the clamp circuit 400 in accordance with the disclosure of fig. 1 and 2.

In some embodiments, the control signal Cdx is used to control the elements electrically connected to the detection circuit 300 that generates the control signal Cdx. More specifically, the control signal S1 may be the control signal Cd1, the control signal Cd2 or the control signal Cd3, the control signal S2 may be the control signal Cd3 or the control signal Cd4, the control signal S3 may be the control signal Cd1 or the control signal Cd2, the control signal S4 may be the control signal Cd4, the control signal S7 may be the control signal Cd1, the control signal S8 may be the control signal Cd2, the control signal S9 may be the control signal Cd3, and the control signal S10 may be the control signal Cd4. In addition, the control signal S5 may be equal to the control signal S3, and the control signal S6 may be any one of the control signals Cdx.

In other embodiments, any of the control signals S1 to S10 may be equal to any of the control signals Cd1 to Cd 4.

Fig. 3 is a circuit diagram of a clamp 400 according to an embodiment of the invention. The clamp 400 mainly includes a transistor 412, a transistor 414, a transistor 416, a transistor 418, and a plurality of switches. The clamping voltage (i.e., the voltage difference between node N1 and node N2) of the clamping circuit 400 may be adjusted by switching the plurality of switches. The node N1 and the node N2 are electrically connected to the output terminals of the integrator or operational amplifier 610a and the integrator or operational amplifier 610b, and thus the output voltages of the integrator or operational amplifier 610a and the integrator or operational amplifier 610b are limited to the clamping voltage of the clamping circuit 400. The number of transistors and the number of switches of the clamp circuit 400 are not limited to those shown in fig. 3, and the operation principle of the clamp circuit 400 is well known to those skilled in the art, so that the description thereof is omitted. Similar to integrators 510 and 520, integrators or operational amplifiers 610a and 610b may be tuned to operate in a passive mode.

Fig. 4 is a circuit diagram of an ADC according to another embodiment of the invention. The embodiment of fig. 4 is similar to the embodiment of fig. 1, except that the ADC 15 of fig. 4 also includes a control circuit 700 and a memory 800. In the embodiment of fig. 4, the control signal S (including S1 to S10) is generated by the control circuit 700 according to the detection result DR (including DR1 to DR 4) of the detection circuit 300, instead of being directly generated by the detection circuit 300. More specifically, the control circuit 700 may be a circuit or electronic element having program execution capability, such as a central processing unit, a microprocessor, a micro-processing unit, or a digital signal processor, which is controlled by executing program codes or program instructions stored in the memory 800. In some embodiments, the memory 800 stores a lookup table, and the control circuit 700 uses the detection result DR to find a corresponding control mode in the lookup table to suppress mirroring or blocking in the SDM 200 and achieve the technical effect of power saving.

In comparison to the ADC 10 of fig. 1, the ADC 15 of fig. 4 may consider the voltages at multiple nodes of the SDM 200 at the same time to make a comprehensive control for the foregoing situations, thereby achieving a preferred combination of the following circuit characteristics, namely, the order of the loop filter 210, the coefficients of the signal transfer function (SIGNAL TRANSFER function, STF) and/or the noise transfer function (noise transfer function, NTF), the swing, the clamp voltage of the clamp circuit 400, the maximum signal-to-noise ratio (SNR), the maximum dynamic range (DYNAMIC RANGE), the maximum error vector magnitude (error vector magnitude, EVM), the maximum swing stability (swing stability), the maximum blocking capability (co-existence) ability), and the minimum power consumption. The embodiment of fig. 1 has a faster response time, i.e., the circuit can be adjusted more quickly, and the embodiment of fig. 4 has a more comprehensive and versatile adjustment strategy. Note that the control circuit 700 of fig. 4 may also be individually adapted to the above-described situations, in other words, at least one of the control signals S1 to S10 has no dependency on other control signals.

FIG. 5 is a functional block diagram of one embodiment of a detection circuit 300. The detection circuit 300 includes a low resolution ADC 310 and a region control circuit 320. The low-resolution ADC 310 converts the node voltage Vn into a detection result DRx (in the example of fig. 4, x is an integer and 1+.x+.4), and the area control circuit 320 generates the control signal Cdx according to the detection result DRx. The number of bits of the low resolution ADC 310 is smaller than the number of bits of the ADC 10 and the ADC 15. For example, the low-resolution ADC 310 may be implemented as a 2-bit ADC to obtain the detection result DRx quickly. The area control circuit 320 may be a logic circuit composed of a plurality of transistors, and one skilled in the art may implement the area control circuit 320 according to the above. When the detection circuit 300 of fig. 5 is applied to the embodiment of fig. 4, the detection circuit 300 includes the low resolution ADC 310 but does not include the region control circuit 320. When the node voltage Vn is large (for example, the swing of the node is large due to the existence of the mirror image or the blocking), the detection result DRx is also large.

Fig. 6 is a functional block diagram of another embodiment of a detection circuit 300. The detection circuit 300 includes a comparator 330 and a region control circuit 320. The comparator 330 compares the node voltage Vn with a predetermined voltage to generate a detection result DRx, and the area control circuit 320 generates a control signal Cdx according to the detection result DRx. Comparator 330 may be considered a one-bit low resolution ADC 310. When the detection circuit 300 of fig. 6 is applied to the embodiment of fig. 4, the detection circuit 300 includes the comparator 330 but does not include the area control circuit 320.

In summary, the ADC of the present invention detects the node voltage of the delta-sigma modulator by using the detection circuit, and adaptively adjusts the ADC according to the detection result, so as to improve the stability of the ADC and reduce the power consumption.

It should be noted that the shapes, sizes, proportions and the like of the elements in the foregoing drawings are merely illustrative, and are used for understanding the present invention by those skilled in the art, and are not intended to limit the present invention.

Although the embodiments of the present invention have been described above, the present invention is not limited thereto, and those skilled in the art can apply the present invention with respect to the technical features of the present invention according to the explicit or implicit disclosure, and all such variations are possible within the scope of the present invention, that is, the scope of the present invention is defined by the claims of the present specification.

Claims (9)

1. An analog-to-digital converter for receiving an analog input signal and generating a digital code, comprising:

a sigma-delta modulator comprising:

a loop filter for receiving the analog input signal;

a quantizer coupled to the loop filter for quantizing an output of the loop filter to generate a digital output signal, and

A digital-to-analog converter coupled to the quantizer and the loop filter;

a down-conversion filter coupled to the delta-sigma modulator for converting the digital output signal into the digital code, and

The detection circuit is coupled with the delta-sigma modulator and is used for detecting a node voltage of the delta-sigma modulator and generating a control signal;

wherein the control signal is used to control the loop filter and/or the quantizer.

2. The analog-to-digital converter of claim 1, wherein the loop filter comprises a resonator comprising an operational amplifier, and the control signal is used to turn off the operational amplifier.

3. An analog to digital converter as claimed in claim 1, in which the loop filter comprises a resonator and the control signal is used to control the resonator to be inactive.

4. An adc according to claim 3, wherein the resonator is a first resonator, the loop filter further comprises a second resonator, an input of the second resonator is coupled to an output of the first resonator, the delta-sigma modulator further comprises a switch coupled between the loop filter and the adc, and the control signal is used to control the switch such that an output of the adc is coupled to the input of the second resonator when the first resonator is inactive.

5. The adc of claim 1, wherein the loop filter comprises a first resonator and a second resonator, an input of the second resonator is coupled to an output of the first resonator, the delta-sigma modulator further comprises a switch coupled between the loop filter and the adc, and the control signal is used to control the switch to control an output of the adc to be coupled to an input of the first resonator or the input of the second resonator.

6. The analog-to-digital converter of claim 1, wherein the control signal is used to control an input operating range of the quantizer.

7. The analog-to-digital converter of claim 1, further comprising a clamp coupled to the delta-sigma modulator, the control signal controlling a clamp voltage of the clamp.

8. The analog-to-digital converter of claim 1, wherein the detection circuit comprises a low-resolution analog-to-digital converter, and the number of bits of the low-resolution analog-to-digital converter is smaller than the number of bits of the analog-to-digital converter.

9. An analog-to-digital converter for receiving an analog input signal and generating a digital code, comprising:

a sigma-delta modulator comprising:

a loop filter for receiving the analog input signal;

a quantizer coupled to the loop filter for quantizing an output of the loop filter to generate a digital output signal, and

A digital-to-analog converter coupled to the quantizer and the loop filter;

A down-conversion filter coupled to the delta-sigma modulator for converting the digital output signal into the digital code;

A detecting circuit coupled to the delta-sigma modulator for detecting a node voltage of the delta-sigma modulator and generating a detection result, and

The control circuit is coupled with the detection circuit and used for generating a control signal according to the detection result;

wherein the control signal is used to control the loop filter and/or the quantizer.