CN112490129A - Semiconductor package and method of manufacturing the same - Google Patents
Semiconductor package and method of manufacturing the same Download PDFInfo
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- CN112490129A CN112490129A CN201910857148.XA CN201910857148A CN112490129A CN 112490129 A CN112490129 A CN 112490129A CN 201910857148 A CN201910857148 A CN 201910857148A CN 112490129 A CN112490129 A CN 112490129A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 258
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 16
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 41
- 239000010703 silicon Substances 0.000 claims abstract description 41
- 238000005538 encapsulation Methods 0.000 claims abstract description 17
- 239000013078 crystal Substances 0.000 claims description 41
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 36
- 239000008393 encapsulating agent Substances 0.000 claims description 10
- 229910000679 solder Inorganic materials 0.000 claims description 8
- 238000000034 method Methods 0.000 claims description 7
- 230000005540 biological transmission Effects 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012858 packaging process Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
- H01L25/0657—Stacked arrangements of devices
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
一种半导体封装及其制造方法。所述半导体封装包括第一至三半导体晶粒、第一至三重布线层、导通孔与包封体。第一重布线层位于第一半导体晶粒的主动表面上。第二半导体晶粒以覆晶方式设置于第一重布线层上。第二半导体晶粒通过位于其中的第一硅导孔与第一重布线层电性连接。导通孔位于第一重布线层上且位于第二半导体晶粒周围。包封体包覆第二半导体晶粒与导通孔。第二重布线层位于包封体上。第三半导体晶粒以覆晶方式设置于第二重布线层上。第三半导体晶粒通过位于其中的第二硅导孔与第二重布线层电性连接。第三重布线层位于第三半导体晶粒上。第二半导体晶粒的面积小于第一半导体晶粒的面积，且第三半导体晶粒的面积大于第二半导体晶粒的面积。
A semiconductor package and a manufacturing method thereof. The semiconductor package includes first to third semiconductor grains, first to third redistribution layers, vias and an encapsulation body. The first redistribution layer is located on the active surface of the first semiconductor grain. The second semiconductor grain is disposed on the first redistribution layer in a flip chip manner. The second semiconductor grain is electrically connected to the first redistribution layer through a first silicon via located therein. The via is located on the first redistribution layer and around the second semiconductor grain. The encapsulation body encapsulates the second semiconductor grain and the via. The second redistribution layer is located on the encapsulation body. The third semiconductor grain is disposed on the second redistribution layer in a flip chip manner. The third semiconductor grain is electrically connected to the second redistribution layer through a second silicon via located therein. The third redistribution layer is located on the third semiconductor grain. The area of the second semiconductor grain is smaller than the area of the first semiconductor grain, and the area of the third semiconductor grain is larger than the area of the second semiconductor grain.
Description
Technical Field
The present invention relates to semiconductor structures and methods of fabricating the same, and more particularly, to a semiconductor package and a method of fabricating the same.
Background
In the field of semiconductor packaging technology, semiconductor packages are being developed toward downsizing and multi-functions. In a typical semiconductor package, in order to satisfy the requirement of multiple functions, a plurality of semiconductor dies (die) are usually included, and the dies may have different functions and areas, respectively. For example, the dies may include logic dies (logic dies) having a relatively large area, memory dies (memory dies) and controller dies (controller dies) having a relatively small area, and the like. In addition, the dies are disposed on an interposer (interposer) and electrically connected to a Printed Circuit Board (PCB) through the interposer. As a result, the interposer requires a larger size, which results in inefficient miniaturization of the semiconductor package. In addition, since the interposer is disposed in the semiconductor package, a delay in the transmission speed of the electrical signal is also caused.
Disclosure of Invention
The invention provides a semiconductor package including semiconductor dies of different sizes stacked on top of each other without an interposer.
The invention provides a manufacturing method of a semiconductor package, which is used for manufacturing the semiconductor package.
The semiconductor package of the invention comprises a first semiconductor crystal grain, a first redistribution layer (RDL layer), a second semiconductor crystal grain, a plurality of via holes (conductive via), an encapsulation body (encapsulation), a second redistribution layer, a third semiconductor crystal grain and a third redistribution layer. The first semiconductor crystal grain is provided with an active surface and a back surface which are opposite to each other. The first redistribution layer is disposed on the active surface of the first semiconductor die and electrically connected to the first semiconductor die. The second semiconductor die has an active surface and a back surface opposite to each other, and is disposed on the first redistribution layer in a manner that the active surface faces the first redistribution layer, wherein a plurality of first through-silicon vias (TSVs) are disposed in the second semiconductor die, and the second semiconductor die is electrically connected to the first redistribution layer through the plurality of first through-silicon vias. The plurality of via holes are arranged on the first redistribution layer, are positioned around the second semiconductor crystal grain and are electrically connected with the first redistribution layer. The encapsulating body is arranged on the first redistribution layer and encapsulates the second semiconductor crystal grain and the plurality of through holes. The second redistribution layer is disposed on the encapsulation and electrically connected to the plurality of vias and the plurality of first silicon vias in the second semiconductor die. The third semiconductor crystal grain is provided with an active surface and a back surface which are opposite to each other and is arranged on the second rewiring layer in a mode that the active surface faces the second rewiring layer, wherein a plurality of second silicon guide holes are arranged in the third semiconductor crystal grain, and the third semiconductor crystal grain is electrically connected with the second rewiring layer through the second silicon guide holes. The third redistribution layer is disposed on the third semiconductor die and electrically connected to the second silicon vias in the third semiconductor die. The area of the second semiconductor die is smaller than the area of the first semiconductor die, and the area of the third semiconductor die is larger than the area of the second semiconductor die, as seen from a top view of the third semiconductor die to the first semiconductor die.
The method for manufacturing a semiconductor package of the present invention includes the steps of: providing a first semiconductor crystal grain, wherein the first semiconductor crystal grain is provided with an active surface and a back surface which are opposite to each other; forming a first redistribution layer on the active surface of the first semiconductor die, wherein the first redistribution layer is electrically connected with the first semiconductor die; stacking a second semiconductor crystal grain on the first redistribution layer, wherein the second semiconductor crystal grain is provided with an active surface and a back surface which are opposite to each other, the active surface of the second semiconductor crystal grain faces the first redistribution layer, a plurality of first silicon guide holes are formed in the second semiconductor crystal grain, and the second semiconductor crystal grain is electrically connected with the first redistribution layer through the plurality of first silicon guide holes; forming a plurality of via holes on the first redistribution layer, wherein the plurality of via holes are located around the second semiconductor crystal grain and are electrically connected with the first redistribution layer; forming an encapsulation body on the first redistribution layer, wherein the encapsulation body encapsulates the second semiconductor crystal grain and the plurality of via holes; forming a second redistribution layer on the encapsulation, wherein the second redistribution layer is electrically connected to the plurality of vias and the plurality of first silicon vias in the second semiconductor die; stacking a third semiconductor crystal grain on the second redistribution layer, wherein the third semiconductor crystal grain has an active surface and a back surface which are opposite to each other, the active surface of the third semiconductor crystal grain faces the second redistribution layer, and a plurality of second silicon guide holes are formed in the third semiconductor crystal grain, and the third semiconductor crystal grain is electrically connected with the second redistribution layer through the plurality of second silicon guide holes; and forming a third redistribution layer on the third semiconductor die, wherein the third redistribution layer is electrically connected to the second plurality of silicon vias in the third semiconductor die. The area of the second semiconductor die is smaller than the area of the first semiconductor die, and the area of the third semiconductor die is larger than the area of the second semiconductor die, as seen from a top view of the third semiconductor die to the first semiconductor die.
In view of the above, in the semiconductor package of the present invention, the through-silicon vias electrically connect the devices to each other, and the interposer is omitted, so that the transmission speed of the electronic signals can be effectively increased. In addition, in the semiconductor package of the present invention, the semiconductor die having a larger size and the semiconductor die having a smaller size are alternately stacked, so that warpage (warp) due to stress non-uniformity can be prevented. In addition, since the provision of the interposer is omitted and the semiconductor dies are alternately stacked, the size of the semiconductor package can be greatly reduced.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIGS. 1A-1F are schematic cross-sectional views illustrating a manufacturing process of a semiconductor package according to an embodiment of the invention;
fig. 2 is a schematic cross-sectional view of a semiconductor package according to another embodiment of the invention.
Detailed Description
The following examples are set forth in detail in conjunction with the accompanying drawings, but are not provided to limit the scope of the present invention. In addition, the drawings are for illustrative purposes only and are not drawn to scale. For ease of understanding, like elements will be described with like reference numerals in the following description.
All references to "including," comprising, "" having, "and the like, herein are to be interpreted as open-ended terms, that is, to mean" including, but not limited to. Furthermore, directional phrases such as "up," "down," and the like may be used with reference to the drawings in the following detailed description, and are not intended to limit the invention. When elements are described in terms of "first," "second," etc., these elements are merely used to distinguish one element from another, and the order or importance of these elements is not limited. Thus, in some cases, a first element can also be referred to as a second element, and a second element can also be referred to as a first element, without departing from the scope of the claims.
In the following embodiments, the numbers and shapes are only mentioned to illustrate the present invention specifically for understanding the contents, but not to limit the present invention.
Fig. 1A to 1F are schematic cross-sectional views illustrating a manufacturing process of a semiconductor package according to an embodiment of the invention. First, referring to fig. 1A, a first semiconductor die 100 having an active surface 100a and a back surface 100b opposite to each other is provided. The first semiconductor die 100 is a semiconductor die having a larger size, such as a logic die. In the present embodiment, "size" represents the area of the semiconductor die as viewed from a top view above the active surface of the semiconductor die. Various semiconductor devices (not shown for clarity of the drawing) are formed on the active surface 100a of the first semiconductor die 100, and the semiconductor devices are, for example, transistors (transistors), interconnects (interconnects), pads (pads), and the like. In the present embodiment, the semiconductor die 100 with a larger size can be used as a supporting substrate in a semiconductor packaging process.
Then, a first redistribution layer 102 is formed on the active surface 100a of the first semiconductor die 100. The first redistribution layer 102 is electrically connected to the first semiconductor die 100. The first redistribution layer 102 may include a dielectric layer 102a and a first line layer 102b disposed in the dielectric layer 102 a. The first redistribution layer 102 may be connected to the pad of the first semiconductor die 100 through the first circuit layer 102 b. In fig. 1A, the number of first wiring layers 102b of the first redistribution layer 102 is only for illustration and is not intended to limit the present invention. The manufacturing method of the first redistribution layer 102 is well known to those skilled in the art and will not be described herein.
Next, referring to fig. 1B, a second semiconductor die 104 having an active surface 104a and a back surface 104B opposite to each other is stacked on the first redistribution layer 102. The second semiconductor die 104 is a semiconductor die having a smaller size, such as a memory die or a controller die. Various semiconductor devices (not shown for clarity of the drawing) such as transistors, interconnects, pads, etc. are formed on the active surface 104a of the second semiconductor die 104. The first silicon via 104c is formed in the second semiconductor die 104 and penetrates the second semiconductor die 104. In the present embodiment, the second semiconductor die 104 is disposed on the first redistribution layer 102 in a manner that the active surface 104a faces the first redistribution layer 102 (i.e., in a flip-chip die manner), and is electrically connected to the first redistribution layer 102. In the present embodiment, the second semiconductor die 104 is connected to the first circuit layer 102b of the first redistribution layer 102 through the first silicon via 104c and an external bump (bump)106, but the invention is not limited thereto. In other embodiments, the second semiconductor die 104 may be connected to the first wiring layer 102b of the first redistribution layer 102 by other external connection means. In addition, in the present embodiment, an underfill (underfill)108 may be selectively formed between the second semiconductor die 104 and the first redistribution layer 102 to protect the bumps 106 between the second semiconductor die 104 and the first redistribution layer 102.
Then, referring to fig. 1C, a plurality of via holes 110 are formed on the first redistribution layer 102. The via hole 110 is located around the second semiconductor die 104 and electrically connected to the first redistribution layer 102. The via hole 110 is, for example, a copper conductive pillar (copper conductive pillar), and the forming method thereof is well known to those skilled in the art and will not be described herein. In the present embodiment, the vias 110 surround the second semiconductor die 104 and are each connected to the first wiring layer 102b of the first redistribution layer 102. The top surface of the via 110 may be coplanar with the back surface 104b of the second semiconductor die 104, or the top surface of the via 110 may be higher than the back surface 104b of the second semiconductor die 104, which is not limited in the present invention. Next, an encapsulation 112 is formed on the first redistribution layer 102. The encapsulant 112 encapsulates the second semiconductor die 104 and the via 110.
In the embodiment, a molding process is performed to form the encapsulant 112, such that the encapsulant 112 covers the sidewalls of the second semiconductor die 104 and the sidewalls of the via 110 and exposes the back surface 104b of the second semiconductor die 104 and the top surface of the via 110, but the invention is not limited thereto. In other embodiments, a molding process is performed to form the encapsulant 112 such that the encapsulant 112 covers the entire second semiconductor die 104 and the entire via 110. Thereafter, a grinding process is performed to remove a portion of the package 112 (if the top surface of the via 110 is higher than the back surface 104b of the second semiconductor die 104, a portion is removed at the same time) until the back surface 104b of the second semiconductor die 104 and the top surface of the via 110 are exposed. As such, the back surface 104b of the second semiconductor die 104, the top surface of the via 110, and the top surface of the encapsulant 112 are coplanar such that other components can be securely disposed thereon.
Next, referring to fig. 1D, a second redistribution layer 114 is formed on the encapsulation 112. The second redistribution layer 114 is electrically connected to the via 110 and the first silicon via 104c in the second semiconductor die 104. The second rewiring layer 114 may include a dielectric layer 114a and a second line layer 114b disposed in the dielectric layer 114 a. The second redistribution layer 114 may be connected to the via 110 and the first silicon via 104c in the second semiconductor die 104 through the second line layer 114 b. In fig. 1D, the number of the second circuit layers 114b of the second redistribution layer 114 is only for illustration and is not intended to limit the invention. The manufacturing method of the second redistribution layer 114 is well known to those skilled in the art and will not be described herein. In the present embodiment, since the back surface 104b of the second semiconductor die 104, the top surface of the via 110, and the top surface of the encapsulant 112 are coplanar, the second redistribution layer 114 can be stably disposed thereon.
Then, referring to fig. 1E, a third semiconductor die 116 having an active surface 116a and a back surface 116b opposite to each other is stacked on the second redistribution layer 114. The third semiconductor die 116 is a semiconductor die having a larger size, such as a logic die. The third semiconductor die 116 may be the same as or different from the first semiconductor die 100, and the invention is not limited thereto. In addition, in the present embodiment, the third semiconductor die 116 may have the same size as the first semiconductor die 100, but the invention is not limited thereto. In other embodiments, the third semiconductor die 116 may not have the same size as the first semiconductor die 100, so long as the size of the third semiconductor die 116 is larger than the size of the second semiconductor die 104.
Various semiconductor devices (not shown for clarity of the drawing) such as transistors, interconnects, pads, etc. are formed on the active surface 116a of the third semiconductor die 116. A second silicon via 116c is formed in the third semiconductor die 116 and penetrates the third semiconductor die 116. In the present embodiment, the third semiconductor die 116 is disposed on the second redistribution layer 114 with the active surface 116a facing the second redistribution layer 114 (i.e., in a flip-chip manner), and is electrically connected to the second redistribution layer 114. In the present embodiment, the third semiconductor die 116 is connected to the second circuit layer 114b of the second redistribution layer 114 through the second silicon via 116.
Thereafter, referring to fig. 1F, a third redistribution layer 118 is formed on the third semiconductor die 116 to form the semiconductor package 10 of the present embodiment. The third redistribution layer 118 is electrically connected to the second silicon via 116c in the third semiconductor die 116. The third redistribution layer 118 may include a dielectric layer 118a and a third circuit layer 118b disposed in the dielectric layer 118 a. The third redistribution layer 118 may be connected to the second silicon via 116c in the third semiconductor die 116 through a third line layer 118 b. In fig. 1F, the number of the third wiring layers 118b of the third redistribution layer 118 is only for illustration and is not intended to limit the present invention. The manufacturing method of the third redistribution layer 118 is well known to those skilled in the art and will not be described herein.
In the semiconductor package 10 of the present embodiment, two semiconductor dies with larger sizes (the first semiconductor die 100, the third semiconductor die 116) and a semiconductor die with smaller sizes (the second semiconductor die 104) are alternately stacked, but the invention is not limited thereto. In other embodiments, after the semiconductor package 10 is formed, the steps illustrated in fig. 1B to 1F are performed one or more times according to actual requirements, so that a plurality of semiconductor dies with larger sizes and a plurality of semiconductor dies with smaller sizes are alternately stacked on the first semiconductor die 100.
After the semiconductor package 10 of the present embodiment is formed, a plurality of solder balls (solder balls) 120 electrically connected to the third redistribution layer 118 may be further formed on the third redistribution layer 118.
Fig. 2 is a schematic cross-sectional view of a semiconductor package according to another embodiment of the invention. Referring to fig. 2, solder balls 120 are formed on the third redistribution layer 118. The solder balls 120 are connected to the third wiring layer 118b of the third redistribution layer 118. Thereby, the semiconductor package 10 can be electrically connected to an external member (e.g., a printed circuit board) through the solder balls 120.
The semiconductor package of the present invention will be described below by taking the semiconductor package 10 as an example. The semiconductor package 10 includes a first semiconductor die 100, a first redistribution layer 102, a second semiconductor die 104, a plurality of vias 110, an encapsulant 112, a second redistribution layer 114, a third semiconductor die 116, and a third redistribution layer 118. The first redistribution layer 102 is disposed on the active surface 100a of the first semiconductor die 100 and electrically connected to the first semiconductor die 100. The second semiconductor die 104 is disposed on the first redistribution layer 102 with the active surface 104a facing the first redistribution layer 102, and the second semiconductor die 104 is electrically connected to the first redistribution layer 102 through the first silicon via 104 c. The via hole 110 is disposed on the first redistribution layer 102, located around the second semiconductor die 104, and electrically connected to the first redistribution layer 102. The encapsulant 112 is disposed on the first redistribution layer 102 and encapsulates the second semiconductor die 104 and the via 110. The second redistribution layer 114 is disposed on the encapsulation 112 and electrically connected to the via 110 and the first tsv 104c in the second semiconductor die 104. The third semiconductor die 116 is disposed on the second redistribution layer 114 with the active surface 116a facing the second redistribution layer 114, and the third semiconductor die 116 is electrically connected to the second redistribution layer 114 through the second silicon via 116 c. The third redistribution layer 118 is disposed on the third semiconductor die 116 and electrically connected to the second silicon via 116c in the third semiconductor die 116.
In addition, in the semiconductor package 10, the first semiconductor die 100 and the third semiconductor die 116 have a larger size, and the second semiconductor die 104 has a smaller size. In detail, from a top view of the third semiconductor die 116 to the first semiconductor die 100, the area of the second semiconductor die 104 is smaller than the area of the first semiconductor die 100, and the area of the third semiconductor die 116 is larger than the area of the second semiconductor die 104.
In the semiconductor package of the invention, the elements are electrically connected with each other through the silicon guide holes, and the arrangement of the intermediate layer is omitted, so that the transmission speed of electronic signals can be effectively improved. In addition, in the semiconductor package of the present invention, the semiconductor dies having a larger size and the semiconductor dies having a smaller size are alternately stacked, so that warpage due to stress unevenness can be prevented. In addition, since the interposer is omitted and the semiconductor dies are stacked alternately, the size of the semiconductor package can be greatly reduced to meet the requirement of miniaturization.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.
Claims (10)
1. A semiconductor package, comprising:
a first semiconductor die having an active surface and a back surface opposite to each other;
the first redistribution layer is arranged on the active surface of the first semiconductor crystal grain and is electrically connected with the first semiconductor crystal grain;
a second semiconductor crystal grain which is provided with an active surface and a back surface which are opposite to each other and is arranged on the first redistribution layer in a mode that the active surface faces the first redistribution layer, wherein a plurality of first silicon guide holes are arranged in the second semiconductor crystal grain, and the second semiconductor crystal grain is electrically connected with the first redistribution layer through the plurality of first silicon guide holes;
a plurality of via holes disposed on the first redistribution layer, located around the second semiconductor die, and electrically connected to the first redistribution layer;
the encapsulating body is arranged on the first rewiring layer and coats the second semiconductor crystal grains and the through holes;
a second redistribution layer disposed on the encapsulation and electrically connected to the plurality of vias and the plurality of first silicon vias in the second semiconductor die;
a third semiconductor crystal grain which is provided with an active surface and a back surface which are opposite to each other and is arranged on the second rewiring layer in a mode that the active surface faces the second rewiring layer, wherein a plurality of second silicon guide holes are arranged in the third semiconductor crystal grain, and the third semiconductor crystal grain is electrically connected with the second rewiring layer through the plurality of second silicon guide holes; and
a third redistribution layer disposed on the third semiconductor die and electrically connected to the second plurality of silicon vias in the third semiconductor die,
wherein an area of the second semiconductor die is smaller than an area of the first semiconductor die and an area of the third semiconductor die is larger than an area of the second semiconductor die in a plan view from the third semiconductor die to the first semiconductor die.
2. The semiconductor package of claim 1, wherein the first semiconductor die and the third semiconductor die comprise logic dies.
3. The semiconductor package of claim 1, wherein the second semiconductor die comprises a memory die or a controller die.
4. The semiconductor package of claim 1, wherein the encapsulation exposes a top surface of the plurality of first through silicon vias, the back surface of the second semiconductor die, and a top surface of the plurality of through vias in the second semiconductor die.
5. The semiconductor package according to claim 1, further comprising a plurality of solder balls disposed on the third redistribution layer and electrically connected to the third redistribution layer.
6. A method of manufacturing a semiconductor package, comprising:
providing a first semiconductor crystal grain, wherein the first semiconductor crystal grain is provided with an active surface and a back surface which are opposite to each other;
forming a first redistribution layer on the active surface of the first semiconductor die, wherein the first redistribution layer is electrically connected with the first semiconductor die;
stacking a second semiconductor crystal grain on the first redistribution layer, wherein the second semiconductor crystal grain is provided with an active surface and a back surface which are opposite to each other, the active surface of the second semiconductor crystal grain faces the first redistribution layer, a plurality of first silicon guide holes are formed in the second semiconductor crystal grain, and the second semiconductor crystal grain is electrically connected with the first redistribution layer through the plurality of first silicon guide holes;
forming a plurality of via holes on the first redistribution layer, wherein the plurality of via holes are located around the second semiconductor crystal grain and are electrically connected with the first redistribution layer;
forming an encapsulation body on the first redistribution layer, wherein the encapsulation body encapsulates the second semiconductor crystal grain and the plurality of via holes;
forming a second redistribution layer on the encapsulation, wherein the second redistribution layer is electrically connected to the plurality of vias and the plurality of first silicon vias in the second semiconductor die;
stacking a third semiconductor die on the second redistribution layer, wherein the third semiconductor die has an active surface and a back surface opposite to each other, and the third semiconductor die faces the second redistribution layer with the active surface, and wherein a plurality of second silicon vias are formed in the third semiconductor die, and the third semiconductor die is electrically connected with the second redistribution layer through the plurality of second silicon vias; and
forming a third redistribution layer on the third semiconductor die, wherein the third redistribution layer is electrically connected to the plurality of second silicon vias in the third semiconductor die,
wherein an area of the second semiconductor die is smaller than an area of the first semiconductor die and an area of the third semiconductor die is larger than an area of the second semiconductor die in a plan view from the third semiconductor die to the second semiconductor die.
7. The method of manufacturing a semiconductor package according to claim 6, wherein the first semiconductor die and the third semiconductor die comprise logic dies.
8. The method of manufacturing a semiconductor package according to claim 6, wherein the second semiconductor die comprises a memory die or a controller die.
9. The method of claim 6, wherein the encapsulant exposes a top surface of the first plurality of through silicon vias, the back surface of the second semiconductor die, and a top surface of the plurality of vias in the second semiconductor die.
10. The method of manufacturing a semiconductor package according to claim 6, wherein after the third redistribution layer is formed, further comprising forming a plurality of solder balls on the third redistribution layer, wherein the plurality of solder balls are electrically connected to the third redistribution layer.
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| CN201910857148.XA CN112490129A (en) | 2019-09-11 | 2019-09-11 | Semiconductor package and method of manufacturing the same |
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Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
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