CN112463018A - Instruction transmission method, memory control circuit unit and memory storage device - Google Patents
Instruction transmission method, memory control circuit unit and memory storage device Download PDFInfo
- Publication number
- CN112463018A CN112463018A CN201910840718.4A CN201910840718A CN112463018A CN 112463018 A CN112463018 A CN 112463018A CN 201910840718 A CN201910840718 A CN 201910840718A CN 112463018 A CN112463018 A CN 112463018A
- Authority
- CN
- China
- Prior art keywords
- memory
- instruction
- sequence
- interface
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/12—Replacement control
- G06F12/121—Replacement control using replacement algorithms
- G06F12/126—Replacement control using replacement algorithms with special data handling, e.g. priority of data or instructions, handling errors or pinning
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Human Computer Interaction (AREA)
- Read Only Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The invention provides an instruction transmission method, a memory control circuit unit and a memory storage device. The method comprises the following steps: sending a plurality of instruction sequences and a state reading instruction sequence to a memory interface electrically connected with the rewritable nonvolatile memory module; and storing the instruction sequences through a memory interface, and transmitting the state reading instruction sequence to the rewritable nonvolatile memory module.
Description
Technical Field
The invention relates to an instruction transmission method, a memory control circuit unit and a memory storage device.
Background
Digital cameras, mobile phones and MP3 players have grown rapidly over the years, resulting in a rapid increase in consumer demand for storage media. Since the rewritable non-volatile memory module (e.g., flash memory) has the characteristics of non-volatility, power saving, small volume, and no mechanical structure, it is very suitable for being built in various portable multimedia devices as described above.
Generally, when the memory management circuit receives a high-level command (e.g., a read command, a write command, or an erase command) from the host system for accessing the rewritable nonvolatile memory module, the memory management circuit needs to convert the high-level command into a sequence of instructions (also referred to as a low-level language) readable by the rewritable nonvolatile memory module, so as to enable the rewritable nonvolatile memory module to perform corresponding operations according to the sequence of instructions. In the prior art, before converting a high-order instruction into an instruction sequence, the memory management circuit usually sends a state read instruction sequence to the rewritable nonvolatile memory module through the memory interface. When the memory management circuit receives a response signal generated by the rewritable nonvolatile memory module according to the state read instruction sequence, the memory management circuit selects a high-order instruction to be executed currently according to the response signal, converts the determined high-order instruction into an instruction sequence and transmits the instruction sequence to the rewritable nonvolatile memory module for access operation.
That is, a long delay time is usually required between two operations of generating a status read command sequence from the memory management circuit and transmitting the command sequence to the rewritable nonvolatile memory module by the memory management circuit. In particular, if the rewritable nonvolatile memory module is always in a ready state (i.e., a state capable of receiving and executing the command sequence) during the aforementioned delay time, substantially no command sequence for accessing the rewritable nonvolatile memory module is executed during the delay time, which results in a problem of poor utilization efficiency of the rewritable nonvolatile memory module.
Therefore, it is one of the problems to be solved by those skilled in the art how to more efficiently send an instruction sequence to be executed to the rewritable nonvolatile memory module and improve the utilization efficiency of the rewritable nonvolatile memory module.
Disclosure of Invention
The invention provides a command transmission method, a memory control circuit unit and a memory storage device, which can improve the use efficiency of a rewritable nonvolatile memory module.
The invention provides a command transmission method, which is used for a rewritable nonvolatile memory module and comprises the following steps: sending a plurality of instruction sequences and a state reading instruction sequence to a memory interface electrically connected with the rewritable nonvolatile memory module; and storing the plurality of instruction sequences through the memory interface and transmitting the state reading instruction sequence to the rewritable nonvolatile memory module.
In an embodiment of the present invention, wherein the plurality of instruction sequences includes a first instruction sequence and a second instruction sequence, the method further includes: receiving a response signal returned by the rewritable nonvolatile memory module through the memory interface and used for responding to the state reading instruction sequence; and selecting the first instruction sequence from the plurality of instruction sequences stored in the memory interface through the memory interface according to the response signal, and transmitting the first instruction sequence to the rewritable nonvolatile memory module.
In an embodiment of the invention, the rewritable non-volatile memory module includes a plurality of memory sub-modules, the first instruction sequence is used to access a first memory sub-module of the plurality of memory sub-modules, and the second instruction sequence is used to access a second memory sub-module of the plurality of memory sub-modules.
In an embodiment of the present invention, the step of selecting, through the memory interface, the first instruction sequence from the plurality of instruction sequences stored in the memory interface according to the response signal includes: when the response signal indicates that the first memory sub-module is in a ready state and the second memory sub-module is in a busy state, selecting the first instruction sequence from the instruction sequences stored in the memory interface through the memory interface according to the response signal is performed.
In an embodiment of the invention, before the step of sending the instruction sequences and the status reading instruction sequence to the memory interface electrically connected to the rewritable non-volatile memory module, the method further includes: receiving a plurality of high-level instructions for accessing the rewritable nonvolatile memory module from a host system; executing a program operation to arrange an execution sequence of the plurality of high-order instructions; selecting a first high-order instruction and a second high-order instruction from the plurality of high-order instructions according to the execution sequence; and converting the first high-order instruction into a first instruction sequence and converting the second high-order instruction into a second instruction sequence.
The invention provides a memory control circuit unit, which is used for controlling a rewritable nonvolatile memory module and comprises: host interface, memory interface and memory management circuit. The host interface is used for electrically connecting to a host system. The memory interface is electrically connected to the rewritable nonvolatile memory module. The memory management circuit is electrically connected to the host interface and the memory interface. The memory management circuit is used for sending a plurality of instruction sequences and a state reading instruction sequence to the memory interface. The memory interface is used for storing the instruction sequences and transmitting the state reading instruction sequence to the rewritable nonvolatile memory module.
In an embodiment of the invention, the plurality of instruction sequences includes a first instruction sequence and a second instruction sequence, and the memory interface is further configured to receive a response signal returned by the rewritable non-volatile memory module in response to the status read instruction sequence. The memory interface is further used for selecting the first instruction sequence from the instruction sequences stored in the memory interface according to the response signal and transmitting the first instruction sequence to the rewritable nonvolatile memory module.
In an embodiment of the invention, the rewritable non-volatile memory module includes a plurality of memory sub-modules, the first instruction sequence is used to access a first memory sub-module of the plurality of memory sub-modules, and the second instruction sequence is used to access a second memory sub-module of the plurality of memory sub-modules.
In an embodiment of the invention, in the operation of selecting the first instruction sequence from the instruction sequences stored in the memory interface according to the response signal, when the response signal indicates that the first memory submodule is in a ready state and the second memory submodule is in a busy state, the memory interface is further configured to perform the operation of selecting the first instruction sequence from the instruction sequences stored in the memory interface according to the response signal.
In an embodiment of the invention, before the operation of sending the command sequences and the status reading command sequence to the memory interface electrically connected to the rewritable nonvolatile memory module, the memory management circuit is further configured to receive a plurality of high-level commands for accessing the rewritable nonvolatile memory module from the host system. The memory management circuit is further configured to execute a program operation to arrange an execution order of the plurality of high-order instructions. The memory management circuit is further configured to select a first high-level instruction and a second high-level instruction from the plurality of high-level instructions according to the execution order. The memory management circuit is further configured to convert the first high-level instruction into a first instruction sequence and convert the second high-level instruction into a second instruction sequence.
The invention provides a memory storage device, comprising: the interface unit, the rewritable nonvolatile memory module and the memory control circuit unit are connected. The connection interface unit is used for electrically connecting to a host system. The memory control circuit unit comprises a memory management circuit and a memory interface, and is electrically connected to the connection interface unit and the rewritable nonvolatile memory module through the memory interface. The memory management circuit is used for sending a plurality of instruction sequences and a state reading instruction sequence to the memory interface. The memory interface is used for storing the instruction sequences and transmitting the state reading instruction sequence to the rewritable nonvolatile memory module.
In an embodiment of the invention, the plurality of instruction sequences includes a first instruction sequence and a second instruction sequence, and the memory interface is further configured to receive a response signal returned by the rewritable non-volatile memory module in response to the status read instruction sequence. The memory interface is further used for selecting the first instruction sequence from the instruction sequences stored in the memory interface according to the response signal and transmitting the first instruction sequence to the rewritable nonvolatile memory module.
In an embodiment of the invention, the rewritable non-volatile memory module includes a plurality of memory sub-modules, the first instruction sequence is used to access a first memory sub-module of the plurality of memory sub-modules, and the second instruction sequence is used to access a second memory sub-module of the plurality of memory sub-modules.
In an embodiment of the invention, in the operation of selecting the first instruction sequence from the instruction sequences stored in the memory interface according to the response signal, when the response signal indicates that the first memory submodule is in a ready state and the second memory submodule is in a busy state, the memory interface is further configured to perform the operation of selecting the first instruction sequence from the instruction sequences stored in the memory interface according to the response signal.
In an embodiment of the invention, before the operation of sending the command sequences and the status reading command sequence to the memory interface, the memory control circuit unit is further configured to receive a plurality of high-level commands for accessing the rewritable nonvolatile memory module from the host system. The memory control circuit unit is further configured to execute a program operation to arrange an execution order of the plurality of high-order instructions. The memory control circuitry is further configured to select a first high-level instruction and a second high-level instruction from the plurality of high-level instructions according to the execution order. The memory control circuit unit is further configured to convert the first high-level instruction into a first instruction sequence and convert the second high-level instruction into a second instruction sequence.
Based on the above, in the instruction transmitting method, the memory control circuit unit and the memory storage device of the invention, since the response signal does not need to be transmitted to the memory management circuit for determination but the memory interface directly selects the executable instruction sequence from the instruction sequence stored in the memory interface according to the response signal, this way can effectively solve the problem in the prior art that the delay time between two operations of generating the state read instruction sequence from the memory management circuit and transmitting the instruction sequence for accessing the rewritable nonvolatile memory module to the memory management circuit is too long, and can improve the use efficiency of the rewritable nonvolatile memory module.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an example embodiment of the present invention;
FIG. 2 is a diagram illustrating a host system, a memory storage device, and an I/O device according to another example embodiment of the present invention;
FIG. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention;
FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;
FIG. 5 is a schematic block diagram illustrating a memory control circuit unit according to an exemplary embodiment of the present invention;
FIG. 6 is a schematic block diagram of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention;
FIG. 7 is a diagram illustrating a method of instruction delivery, according to an example embodiment of the present invention;
FIG. 8 is a flowchart illustrating a method of instruction delivery according to an exemplary embodiment of the invention.
The reference numbers illustrate:
30. 10: memory storage device
31. 11: host system
110: system bus
111: processor with a memory having a plurality of memory cells
112: random access memory
113: read-only memory
114: data transmission interface
12: input/output (I/O) device
20: main machine board
201: portable disk
202: memory card
203: solid state disk
204: wireless memory storage device
205: global positioning system module
206: network interface card
207: wireless transmission device
208: keyboard with a keyboard body
209: screen
210: horn type loudspeaker
32: SD card
33: CF card
34: embedded memory device
341: embedded multimedia card
342: embedded multi-chip packaging storage device
402: connection interface unit
404: memory control circuit unit
406: rewritable nonvolatile memory module
502: memory management circuit
504: host interface
506: memory interface
508: error checking and correcting circuit
510: buffer memory
512: power management circuit
310: first memory sub-module
320: second memory sub-module
330: third memory sub-module
340: fourth memory sub-module
316. 326, 336, 346: data bus
410(0) - (410 (N), 420(0) - (420 (N), 430(0) - (430 (N), 440(0) - (440 (N)): physical erase unit
S801: receiving a plurality of high-level instructions from a host system for accessing a rewritable non-volatile memory module
S803: a step of executing the scheduling operation to arrange an execution sequence of the high-order instructions
S805: selecting a first high-level instruction and a second high-level instruction from the plurality of high-level instructions according to the execution order
S807: converting the first high-order instruction into a first instruction sequence and converting the second high-order instruction into a second instruction sequence
S809: sending the first instruction sequence, the second instruction sequence and the state reading instruction sequence to the memory interface
S811: storing the first instruction sequence and the second instruction sequence through the memory interface, and transmitting the state reading instruction sequence to the rewritable nonvolatile memory module
S813: receiving a response signal returned by the rewritable nonvolatile memory module via the memory interface in response to the status read command sequence
S815: selecting the first instruction sequence from the first instruction sequence and the second instruction sequence stored in the memory interface through the memory interface according to the response signal, and transmitting the first instruction sequence to the rewritable nonvolatile memory module
Detailed Description
Generally, a memory storage device (also referred to as a memory storage system) includes a rewritable non-volatile memory module (rewritable non-volatile memory module) and a controller (also referred to as a control circuit). Typically, memory storage devices are used with a host system so that the host system can write data to or read data from the memory storage devices.
FIG. 1 is a diagram illustrating a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the invention. FIG. 2 is a diagram illustrating a host system, a memory storage device and an I/O device according to another example embodiment of the invention.
Referring to fig. 1 and 2, the host system 11 generally includes a processor 111, a Random Access Memory (RAM) 112, a Read Only Memory (ROM) 113, and a data transmission interface 114. The processor 111, the RAM 112, the ROM 113, and the data transmission interface 114 are all electrically connected to the system bus (system bus) 110.
In the present exemplary embodiment, the host system 11 is electrically connected to the memory storage device 10 through the data transmission interface 114. For example, host system 11 may store data to memory storage device 10 or read data from memory storage device 10 via data transfer interface 114. In addition, the host system 11 is electrically connected to the I/O device 12 via a system bus 110. For example, the host system 11 may transmit output signals to the I/O device 12 or receive input signals from the I/O device 12 via the system bus 110.
In the present exemplary embodiment, the processor 111, the ram 112, the rom 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11. The number of data transfer interfaces 114 may be one or more. The motherboard 20 can be electrically connected to the memory storage device 10 through the data transmission interface 114 in a wired or wireless manner. The memory storage device 10 may be, for example, a personal disk 201, a memory card 202, a Solid State Drive (SSD) 203, or a wireless memory storage device 204. The wireless memory storage device 204 can be a memory storage device based on various wireless Communication technologies, such as Near Field Communication (NFC) memory storage device, wireless facsimile (WiFi) memory storage device, Bluetooth (Bluetooth) memory storage device, or Bluetooth low energy memory storage device (e.g., iBeacon). In addition, the motherboard 20 may also be electrically connected to various I/O devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, and the like through the System bus 110. For example, in an exemplary embodiment, the motherboard 20 may access the wireless memory storage device 204 via the wireless transmission device 207.
In an exemplary embodiment, the host system referred to is substantially any system that can cooperate with a memory storage device to store data. Although the host system is described as a computer system in the above exemplary embodiment, fig. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the invention. Referring to fig. 3, in another exemplary embodiment, the host system 31 may also be a Digital camera, a video camera, a communication device, an audio player, a video player, or a tablet computer, and the memory storage device 30 may be various non-volatile memory storage devices such as a Secure Digital (SD) card 32, a Compact Flash (CF) card 33, or an embedded storage device 34. The embedded memory device 34 includes embedded Multi-Media Card (eMMC) 341 and/or embedded Multi-Chip Package (eMCP) memory device 342, which electrically connects the memory module directly to the embedded memory device on the substrate of the host system.
FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention.
Referring to fig. 4, the memory storage device 10 includes a connection interface unit 402, a memory control circuit unit 404 and a rewritable nonvolatile memory module 406.
The connection interface unit 402 is used to electrically connect the memory storage device 10 to the host system 11. In the exemplary embodiment, the connection interface unit 402 conforms to the Peripheral Component Interconnect Express (PCI Express) standard and is compatible with the NVM Express interface standard. In particular, the fast non-volatile memory interface standard is a protocol for communication between a host system and a memory device, which defines a register interface, an instruction set, and a function set between a controller of the memory storage device and an operating system of the host system, and facilitates data access speed and data transfer rate of the memory storage device based on a PCIe interface by optimizing the interface standard of the memory storage device. However, in other exemplary embodiments, the connection interface unit 402 may conform to other suitable standards. In addition, the connection interface unit 402 can be packaged with the memory control circuit unit 404 in one chip, or the connection interface unit 402 is disposed outside a chip including the memory control circuit unit 404.
The memory control circuit unit 404 is used for executing a plurality of logic gates or control commands implemented in a hardware type or a firmware type and performing operations such as writing, reading and erasing data in the rewritable nonvolatile memory module 406 according to commands of the host system 11.
The rewritable nonvolatile memory module 406 is electrically connected to the memory control circuit unit 404 and is used for storing data written by the host system 11. The rewritable nonvolatile memory module 406 may be a Single Level Cell (SLC) NAND flash memory module (i.e., a flash memory module capable of storing 1 bit in one memory Cell), a Multi-Level Cell (MLC) NAND flash memory module (i.e., a flash memory module capable of storing 2 bits in one memory Cell), a Multi-Level Cell (TLC) NAND flash memory module (i.e., a flash memory module capable of storing 3 bits in one memory Cell), other flash memory modules, or other memory modules having the same characteristics.
Each memory cell in the rewritable nonvolatile memory module 406 stores one or more bits with a change in voltage (hereinafter also referred to as a threshold voltage). Specifically, each memory cell has a charge trapping layer between the control gate and the channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be varied, thereby varying the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also referred to as "writing data to the memory cell" or "programming" the memory cell. As the threshold voltage changes, each memory cell in the rewritable nonvolatile memory module 406 has multiple memory states. The read voltage is applied to determine which memory state a memory cell belongs to, thereby obtaining one or more bits stored by the memory cell.
In the exemplary embodiment, the memory cells of the rewritable nonvolatile memory module 406 form a plurality of physical programming cells, and the physical programming cells form a plurality of physical erasing cells. Specifically, the memory cells on the same word line constitute one or more physically programmed cells. If each memory cell can store more than 2 bits, the physical program cells on the same word line can be classified into at least a lower physical program cell and an upper physical program cell. For example, the Least Significant Bit (LSB) of a memory cell belongs to the lower physical program cell, and the Most Significant Bit (MSB) of a memory cell belongs to the upper physical program cell. Generally, in the MLC NAND flash memory, the writing speed of the lower physical program cell is faster than that of the upper physical program cell, and/or the reliability of the lower physical program cell is higher than that of the upper physical program cell.
In the present exemplary embodiment, the physical program cell is a programmed minimum cell. That is, the physical programming unit is the minimum unit for writing data. For example, the physical programming unit is a physical page (page) or a physical fan (sector). If the physical program cells are physical pages, the physical program cells usually include a data bit region and a redundancy (redundancy) bit region. The data bit region includes a plurality of physical sectors for storing user data, and the redundant bit region stores system data (e.g., management data such as error correction codes). In the present exemplary embodiment, the data bit area includes 32 physical fans, and the size of one physical fan is 512 bytes (B). However, in other example embodiments, the data bit region may also include 8, 16, or a greater or lesser number of physical fans, and the size of each physical fan may also be greater or lesser. On the other hand, the physically erased cell is the minimum unit of erase. That is, each physically erased cell contains the minimum number of memory cells that are erased together. For example, the physical erase unit is a physical block (block).
FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.
Referring to fig. 5, the memory control circuit unit 404 includes a memory management circuit 502, a host interface 504, and a memory interface 506.
The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control commands, and the control commands are executed to perform data writing, reading, and erasing operations during the operation of the memory storage device 10. When the operation of the memory management circuit 502 is explained below, it is equivalent to the operation of the memory control circuit unit 404.
In the exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in firmware. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read only memory (not shown), and the control instructions are burned into the read only memory. When the memory storage device 10 is in operation, the control instructions are executed by the microprocessor unit to perform operations such as writing, reading, and erasing data.
In another example embodiment, the control instructions of the memory management circuit 502 can also be stored in a program code type in a specific area of the rewritable nonvolatile memory module 406 (e.g., a system area dedicated to storing system data in the memory module). Further, the memory management circuit 502 has a microprocessor unit (not shown), a read only memory (not shown), and a random access memory (not shown). In particular, the ROM has a boot code (BOOT code), and when the memory control circuit 404 is enabled, the microprocessor unit first executes the boot code to load the control instructions stored in the rewritable nonvolatile memory module 406 into the RAM of the memory management circuit 502. Then, the microprocessor unit operates the control commands to perform data writing, reading, erasing, and the like.
In another exemplary embodiment, the control instructions of the memory management circuit 502 can also be implemented in a hardware form. For example, the memory management circuit 502 includes a microcontroller, a memory cell management circuit, a memory write circuit, a memory read circuit, a memory erase circuit, and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are electrically connected to the microcontroller. The memory cell management circuit is used for managing the memory cells or groups thereof of the rewritable nonvolatile memory module 406. The memory write circuit is configured to issue a write command sequence to the rewritable nonvolatile memory module 406 to write data into the rewritable nonvolatile memory module 406. The memory read circuit is configured to issue a read command sequence to the rewritable nonvolatile memory module 406 to read data from the rewritable nonvolatile memory module 406. The memory erasing circuit is used for issuing an erasing command sequence to the rewritable nonvolatile memory module 406 so as to erase data from the rewritable nonvolatile memory module 406. The data processing circuit is used for processing data to be written into the rewritable nonvolatile memory module 406 and data read from the rewritable nonvolatile memory module 406. The write command sequence, the read command sequence, and the erase command sequence may include one or more program codes or command codes respectively and instruct the rewritable nonvolatile memory module 406 to perform corresponding operations of writing, reading, and erasing. In an example embodiment, the memory management circuit 502 may issue other types of command sequences to the rewritable nonvolatile memory module 406 to instruct the corresponding operations to be performed.
The host interface 504 is electrically connected to the memory management circuit 502 and is used for receiving and recognizing commands and data transmitted by the host system 11. That is, commands and data transmitted by the host system 11 are transmitted to the memory management circuit 502 through the host interface 504. In the exemplary embodiment, host interface 504 is compatible with the PCI Express standard. However, it should be understood that the present invention is not limited thereto, and the host interface 504 may be compatible with the PATA standard, the IEEE 1394 standard, the SATA standard, the USB standard, the SD standard, the UHS-I standard, the UHS-II standard, the MS standard, the MMC standard, the eMMC standard, the UFS standard, the CF standard, the IDE standard or other suitable data transmission standards.
The memory interface 506 is electrically connected to the memory management circuit 502 and is used for accessing the rewritable nonvolatile memory module 406. That is, the data to be written to the rewritable nonvolatile memory module 406 is converted into a format accepted by the rewritable nonvolatile memory module 406 through the memory interface 506. Specifically, if the memory management circuit 502 wants to access the rewritable nonvolatile memory module 406, the memory interface 506 transmits a corresponding instruction sequence. For example, the instruction sequences may include a write instruction sequence for indicating to write data, a read instruction sequence for indicating to read data, an erase instruction sequence for indicating to erase data, and corresponding instruction sequences for indicating various memory operations (e.g., changing read voltage levels or performing garbage collection operations, etc.). The instruction sequences are generated by the memory management circuit 502 and transmitted to the rewritable nonvolatile memory module 406 through the memory interface 506, for example. The sequences of instructions may include one or more signals or data on a bus. These signals or data may include instruction code or program code. For example, the read command sequence includes read identification codes, memory addresses, and other information.
In an exemplary embodiment, the memory control circuitry 404 further includes error checking and correction circuitry 508, buffer memory 510, and power management circuitry 512.
The error checking and correcting circuit 508 is electrically connected to the memory management circuit 502 and is used for performing error checking and correcting operations to ensure the correctness of data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correcting circuit 508 generates an Error Correcting Code (ECC) and/or an Error Detecting Code (EDC) for data corresponding to the write command, and the memory management circuit 502 writes the data corresponding to the write command and the corresponding ECC and/or EDC into the rewritable nonvolatile memory module 406. Thereafter, when the memory management circuit 502 reads data from the rewritable nonvolatile memory module 406, the error correction code and/or the error check code corresponding to the data are simultaneously read, and the error checking and correcting circuit 508 performs an error checking and correcting operation on the read data according to the error correction code and/or the error check code.
The buffer memory 510 is electrically connected to the memory management circuit 502 and is used for temporarily storing data and instructions from the host system 11 or data from the rewritable nonvolatile memory module 406. The power management circuit 512 is electrically connected to the memory management circuit 502 and is used for controlling the power of the memory storage device 10.
FIG. 6 is a schematic block diagram of a rewritable nonvolatile memory module according to an exemplary embodiment of the present invention.
Referring to FIG. 6, the rewritable non-volatile memory module 406 includes a first memory sub-module 310, a second memory sub-module 320, a third memory sub-module 330, and a fourth memory sub-module 340. For example, the first, second, third and fourth memory sub-modules 310, 320, 330 and 340 are memory dies (die), respectively. The first memory sub-module 310 has physically erased cells 410(0) -410 (N). The second memory sub-module 320 has physically erased cells 420(0) -420 (N). The third memory sub-module 330 has physically erased cells 430(0) -430 (N). The fourth memory sub-module 340 has physically erased cells 440(0) -440 (N).
For example, the first, second, third and fourth memory sub-modules 310, 320, 330 and 340 are electrically connected to the memory control circuit unit 404 through independent data buses 316, 326, 336 and 346, respectively. Accordingly, the memory management circuit 502 may write data in parallel (parallel) to the first, second, third and fourth memory sub-modules 310, 320, 330 and 340 via the data buses 316, 326, 336 and 346.
However, it should be understood that, in another exemplary embodiment of the present invention, the first, second, third and fourth memory sub-modules 310, 320, 330 and 340 may also be electrically connected to the memory control circuit unit 404 only through 1 data bus. Here, the memory management circuit 502 may write data to the first, second, third, and fourth memory sub-modules 310, 320, 330, and 340 in an interleaved (interleave) manner through a single data bus.
In particular, the first, second, third and fourth memory sub-modules 310, 320, 330 and 340 may respectively include a plurality of word lines, and a plurality of memory cells on the same word line form a plurality of physical pages, and the plurality of physical pages of the same word line may be referred to as a physical page group. Each of the physically erased cells of the first, second, third and fourth memory sub-modules 310, 320, 330 and 340 has a plurality of physical pages, wherein the physical pages belonging to the same physically erased cell can be independently written and simultaneously erased. For example, each physical erase unit consists of 128 physical pages. However, it should be understood that the present invention is not limited thereto, and each physical erase unit can be composed of 64 physical pages, 256 physical pages, or any other physical pages.
In more detail, the physically erased cell is the minimum unit of erase. That is, each physically erased cell contains the minimum number of memory cells that are erased together. The physical page is the smallest unit of programming. That is, the physical page is the smallest unit of write data. However, it should be understood that in another exemplary embodiment of the present invention, the minimum unit of the written data may be a Sector (Sector) or other size. Each physical page typically includes a data bit region and a redundancy bit region. The data bit area is used for storing user data, and the redundant bit area is used for storing system data (such as error checking and correcting codes). It should be noted that, in another exemplary embodiment, a physically erased cell may also refer to a physical address, a physically programmed cell, or consist of multiple continuous or discontinuous physical addresses.
It should be noted that although the exemplary embodiment of the present invention is described with respect to the rewritable nonvolatile memory module 406 including four memory sub-modules. However, the invention is not limited thereto, and in other embodiments, the rewritable non-volatile memory module 406 may include six, eight, or ten memory sub-modules.
FIG. 7 is a diagram illustrating a method of instruction delivery according to an exemplary embodiment of the invention.
Referring to FIG. 7, first, it is assumed that the memory management circuit 502 receives high-level commands C1-C4 from the host system 11 for accessing the rewritable nonvolatile memory module 406. Each of the high-level commands C1-C4 may be of the type of read command, write command, or erase command, and is not limited herein. Thereafter, the memory management circuit 502 may perform scheduling operations to arrange the execution order of the high-level instructions C1-C4. In this example, it is assumed that the memory management circuit 502 performs the scheduled operations in the order of the high-level instruction C1, the high-level instruction C2, the high-level instruction C3, and the high-level instruction C4. However, the present invention is not limited to the execution order generated after the scheduling operation is executed.
After generating the execution sequence, the memory management circuit 502 may select the first two high-level instructions (i.e., the high-level instructions C1-C2) to be executed from the high-level instructions C1-C4 according to the execution sequence. Thereafter, the memory management circuit 502 converts the selected high-level command C1 (also referred to as the first high-level command) into the command sequence CS1 (also referred to as the first command sequence) and converts the selected high-level command C2 (also referred to as the second high-level command) into the command sequence CS2 (also referred to as the second command sequence). In particular, in the exemplary embodiment, it is assumed that the command sequence CS1 is used to access the first memory sub-module 310 and the command sequence CS2 is used to access the second memory sub-module 320.
Thereafter, the memory management circuit 502 sends the command sequences CS 1-CS 2 and a state read command sequence SRCS to the memory interface 506 at the same time. In the present example, the status read command sequence SRCS is used to query the status of the first memory sub-module 310 and the second memory sub-module 320. It should be noted that the status of a memory submodule can be at least divided into a ready state (ready state) and a busy state (busy state), for example. Assuming that the status of a memory sub-module is ready, it means that the memory sub-module is available to receive and execute instruction sequences to access the memory sub-module. Assuming the status of a memory sub-module is busy, it indicates that the memory sub-module is busy and is currently unable to receive and execute the command sequence.
After the memory management circuit 502 sends the command sequences CS 1-CS 2 and the status read command sequence SRCS to the memory interface 506, the memory interface 506 stores the command sequences CS 1-CS 2, and when the command sequences CS 1-CS 2 are stored in the memory interface 506, the status read command sequence SRCS is first transferred to the first memory sub-module 310 and the second memory sub-module 320 of the rewritable non-volatile memory module 406 through the memory interface 506.
Thereafter, the memory interface 506 receives a response signal R _ signal returned by the rewritable nonvolatile memory module 406 in response to the status read command sequence SRCS. In the exemplary embodiment, when the response signal R _ signal indicates that the first memory sub-module 310 is in the ready state and the second memory sub-module 320 is in the busy state, the memory interface 506 selects the command sequence CS1 for accessing the first memory sub-module 310 from the command sequences CS 1-CS 2 stored in the memory interface 506 according to the response signal R _ signal. The memory interface 506 transmits the selected command sequence CS1 to the rewritable non-volatile memory module 406 to access the first memory sub-module 310.
It should be noted that in the command transferring method of the present invention, since the response signal R _ signal does not need to be transferred to the memory management circuit 502 for determination but directly selects the executable command sequence from the command sequences CS 1-CS 2 stored in the memory interface 506 according to the response signal R _ signal through the memory interface 506, this way can effectively solve the problem of too long delay time between two operations of generating the state read command sequence SRCS from the memory management circuit 502 to the memory management circuit 502 for transferring the command sequence for accessing the rewritable nonvolatile memory module 406 to the rewritable nonvolatile memory module 406 in the prior art, and can improve the utilization efficiency of the rewritable nonvolatile memory module 406.
It should be noted that although the foregoing example illustrates the memory interface 506 storing two instruction sequences, the invention is not limited thereto. In other embodiments, memory interface 506 may store more than two sequences of instructions. In addition, although the memory interface 506 transmits only one command sequence to the rewritable nonvolatile memory module 406 according to the response signal R _ signal in the foregoing embodiments, the invention is not limited thereto. In other embodiments, the memory interface 506 can also select and transmit a plurality of command sequences to the rewritable nonvolatile memory module 406 according to the response signal R _ signal.
FIG. 8 is a flowchart illustrating a method of instruction delivery according to an exemplary embodiment of the invention.
Referring to FIG. 8, in step S801, the memory management circuit 502 receives a plurality of high-level commands for accessing the rewritable nonvolatile memory module 406 from the host system 11. In step S803, the memory management circuit 502 executes a scheduling operation to arrange the execution order of the high-level instructions. In step S805, the memory management circuit 502 selects a first high-order instruction and a second high-order instruction from the plurality of high-order instructions according to the execution order. In step S807, the memory management circuit 502 converts the first high-order instruction into a first instruction sequence, and converts the second high-order instruction into a second instruction sequence. In step S809, the memory management circuit 502 sends the first instruction sequence, the second instruction sequence, and the status read instruction sequence to the memory interface 506. In step S811, the memory interface 506 stores the first instruction sequence and the second instruction sequence, and transmits the state read instruction sequence to the rewritable nonvolatile memory module 406. In step S813, the memory interface 506 receives a response signal returned by the rewritable nonvolatile memory module 406 in response to the status read command sequence. In step S815, the memory interface 506 selects a first command sequence from the first command sequence and the second command sequence stored in the memory interface 506 according to the response signal, and transmits the first command sequence to the rewritable non-volatile memory module 406.
In summary, in the instruction transmitting method, the memory control circuit unit and the memory storage device of the invention, since the response signal does not need to be transmitted to the memory management circuit for determination but the memory interface directly selects the executable instruction sequence from the instruction sequence stored in the memory interface according to the response signal, this way can effectively solve the problem in the prior art that the memory management circuit generates the state read instruction sequence and the memory management circuit transmits the instruction sequence for accessing the rewritable nonvolatile memory module to the rewritable nonvolatile memory module, and the delay time between the two operations is too long, and can improve the utilization efficiency of the rewritable nonvolatile memory module.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.
Claims (15)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910840718.4A CN112463018B (en) | 2019-09-06 | 2019-09-06 | Instruction transmission method, memory control circuit unit and memory storage device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910840718.4A CN112463018B (en) | 2019-09-06 | 2019-09-06 | Instruction transmission method, memory control circuit unit and memory storage device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112463018A true CN112463018A (en) | 2021-03-09 |
| CN112463018B CN112463018B (en) | 2022-11-08 |
Family
ID=74806912
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910840718.4A Active CN112463018B (en) | 2019-09-06 | 2019-09-06 | Instruction transmission method, memory control circuit unit and memory storage device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112463018B (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114115739A (en) * | 2021-11-25 | 2022-03-01 | 群联电子股份有限公司 | Memory management method, memory storage device and memory control circuit unit |
| CN114610236A (en) * | 2022-03-08 | 2022-06-10 | 群联电子股份有限公司 | Memory control method, memory storage device, and memory control circuit unit |
| US12292825B2 (en) | 2022-03-02 | 2025-05-06 | Phison Electronics Corp. | Memory control method, memory storage device and memory control circuit unit |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1549134A (en) * | 2003-05-19 | 2004-11-24 | 群联电子股份有限公司 | Interleaving execution new management method for raising processing speed of plasticity flash memory |
| US20070255898A1 (en) * | 2006-04-28 | 2007-11-01 | Kabushiki Kaisha Toshiba | Storage device using nonvolatile flash memory and control method thereof |
| CN101281513A (en) * | 2008-05-15 | 2008-10-08 | 中国人民解放军国防科学技术大学 | Stream Processor IP Core Based on Avalon Bus |
| CN102955751A (en) * | 2011-08-17 | 2013-03-06 | 群联电子股份有限公司 | Memory storage device, memory controller and data writing method |
| CN103985404A (en) * | 2005-09-30 | 2014-08-13 | 莫塞德技术公司 | Multiple independent serial link memory |
| US20160239373A1 (en) * | 2015-02-13 | 2016-08-18 | Sandisk Technologies Inc. | Multi-die status mode for non-volatile storage |
| US10235309B1 (en) * | 2017-11-28 | 2019-03-19 | Western Digital Technologies, Inc. | Combined control for multi-die flash |
-
2019
- 2019-09-06 CN CN201910840718.4A patent/CN112463018B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1549134A (en) * | 2003-05-19 | 2004-11-24 | 群联电子股份有限公司 | Interleaving execution new management method for raising processing speed of plasticity flash memory |
| CN103985404A (en) * | 2005-09-30 | 2014-08-13 | 莫塞德技术公司 | Multiple independent serial link memory |
| US20070255898A1 (en) * | 2006-04-28 | 2007-11-01 | Kabushiki Kaisha Toshiba | Storage device using nonvolatile flash memory and control method thereof |
| CN101281513A (en) * | 2008-05-15 | 2008-10-08 | 中国人民解放军国防科学技术大学 | Stream Processor IP Core Based on Avalon Bus |
| CN102955751A (en) * | 2011-08-17 | 2013-03-06 | 群联电子股份有限公司 | Memory storage device, memory controller and data writing method |
| US20160239373A1 (en) * | 2015-02-13 | 2016-08-18 | Sandisk Technologies Inc. | Multi-die status mode for non-volatile storage |
| US10235309B1 (en) * | 2017-11-28 | 2019-03-19 | Western Digital Technologies, Inc. | Combined control for multi-die flash |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114115739A (en) * | 2021-11-25 | 2022-03-01 | 群联电子股份有限公司 | Memory management method, memory storage device and memory control circuit unit |
| CN114115739B (en) * | 2021-11-25 | 2023-11-07 | 群联电子股份有限公司 | Memory management method, memory storage device and memory control circuit unit |
| US12292825B2 (en) | 2022-03-02 | 2025-05-06 | Phison Electronics Corp. | Memory control method, memory storage device and memory control circuit unit |
| CN114610236A (en) * | 2022-03-08 | 2022-06-10 | 群联电子股份有限公司 | Memory control method, memory storage device, and memory control circuit unit |
| CN114610236B (en) * | 2022-03-08 | 2025-07-15 | 群联电子股份有限公司 | Memory control method, memory storage device and memory control circuit unit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112463018B (en) | 2022-11-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN107844431B (en) | Mapping table updating method, memory control circuit unit and memory storage device | |
| CN109491588B (en) | Memory management method, memory control circuit unit and memory storage device | |
| TWI650639B (en) | Memory management method, memory control circuit unit and mempry storage device | |
| CN111078146B (en) | Memory management method, memory storage device and memory control circuit unit | |
| TWI688953B (en) | Memory management method, memory storage device and memory control circuit unit | |
| CN106775436B (en) | Data access method, memory control circuit unit and memory | |
| CN112463018B (en) | Instruction transmission method, memory control circuit unit and memory storage device | |
| CN111258505B (en) | Data merging method of flash memory, control circuit unit and storage device | |
| CN109273033B (en) | Memory management method, memory control circuit unit and memory storage device | |
| TW202046113A (en) | Data writing method, memory control circuit unit and memory storage device | |
| CN106920572B (en) | Memory management method, memory control circuit unit and memory storage device | |
| TW201908957A (en) | Data writing method, memory control circuit unit and memory storage device | |
| CN108958640B (en) | Memory management method, memory control circuit unit, and memory storage device | |
| CN109032957B (en) | Memory management method, memory control circuit unit and memory storage device | |
| CN114333930B (en) | Multi-channel memory storage device, control circuit unit and data reading method thereof | |
| TWI730600B (en) | Data writing method, memory controlling circuit unit and memory storage device | |
| TWI711048B (en) | Value adjusting method, memory control circuit unit and memory storage device for flash memory | |
| TWI724427B (en) | Data writing method, memory storage device and memory control circuit unit | |
| TWI728448B (en) | Command transmitting method, memory control circuit unit and memory storage device | |
| CN109308930B (en) | Data writing method, memory control circuit unit, and memory storage device | |
| TWI734370B (en) | Data merging method, memory control circuit unit and memory storage device for flash memory | |
| CN114115737B (en) | Data storage allocation method, memory storage device and control circuit unit | |
| TWI769386B (en) | Data erasing method, memory control circuit unit and memory storage device | |
| CN112015327B (en) | Data writing method, memory storage device and memory control circuit unit | |
| CN112347010B (en) | Memory control method, memory storage device and memory control circuit unit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |