CN112444526B - Defect detection method and defect detection system - Google Patents
Defect detection method and defect detection system Download PDFInfo
- Publication number
- CN112444526B CN112444526B CN201910838099.5A CN201910838099A CN112444526B CN 112444526 B CN112444526 B CN 112444526B CN 201910838099 A CN201910838099 A CN 201910838099A CN 112444526 B CN112444526 B CN 112444526B
- Authority
- CN
- China
- Prior art keywords
- unit
- screening
- value
- pattern
- image
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000007547 defect Effects 0.000 title claims abstract description 100
- 238000001514 detection method Methods 0.000 title claims abstract description 75
- 238000013461 design Methods 0.000 claims abstract description 78
- 238000012216 screening Methods 0.000 claims abstract description 73
- 238000000034 method Methods 0.000 claims description 22
- 238000004519 manufacturing process Methods 0.000 claims description 10
- 238000005259 measurement Methods 0.000 claims description 3
- 238000004458 analytical method Methods 0.000 abstract description 5
- 239000004065 semiconductor Substances 0.000 description 6
- 230000002950 deficient Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000001914 filtration Methods 0.000 description 2
- 238000007689 inspection Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000011161 development Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01N—INVESTIGATING OR ANALYSING MATERIALS BY DETERMINING THEIR CHEMICAL OR PHYSICAL PROPERTIES
- G01N21/00—Investigating or analysing materials by the use of optical means, i.e. using sub-millimetre waves, infrared, visible or ultraviolet light
- G01N21/84—Systems specially adapted for particular applications
- G01N21/88—Investigating the presence of flaws or contamination
- G01N21/95—Investigating the presence of flaws or contamination characterised by the material or shape of the object to be examined
- G01N21/9501—Semiconductor wafers
- G01N21/9505—Wafer internal defects, e.g. microcracks
Landscapes
- Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Life Sciences & Earth Sciences (AREA)
- Chemical & Material Sciences (AREA)
- Analytical Chemistry (AREA)
- Biochemistry (AREA)
- General Health & Medical Sciences (AREA)
- General Physics & Mathematics (AREA)
- Immunology (AREA)
- Pathology (AREA)
- Investigating Materials By The Use Of Optical Means Adapted For Particular Applications (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
A defect detection method and a defect detection system comprise the steps of providing a wafer, scanning the detection surface to obtain a scanning image of the detection surface, providing a design image, wherein the design image comprises a plurality of second unit patterns corresponding to the first unit patterns, screening the scanning image according to the design image, and removing interference defect unit patterns in the first unit patterns. According to the technical scheme, the interference defect unit patterns in the first unit patterns are partially screened and removed, so that the number of the first unit patterns for subsequent detection and analysis is effectively reduced, the detection time is shortened, and the detection efficiency is improved.
Description
Technical Field
The present invention relates to the field of semiconductor testing, and in particular, to a defect detection method and a defect detection system.
Background
In recent years, semiconductor manufacturing technology has advanced greatly, and the minimum feature size can be reduced to below 10 nanometers, so that the pattern density is higher than ever before. Semiconductor foundry develops more defect modes (hot spots) in developing next generation technology, especially at an early stage. Therefore, a method for rapidly and accurately finding and analyzing such weak links is highly demanded, so as to accelerate the development of technology and improve the yield.
However, the detection efficiency in the existing defect detection method is to be improved.
Disclosure of Invention
The invention solves the problem of providing a defect detection method and a defect detection system, which can screen and remove part of interference defect unit patterns, effectively reduce the number of first unit patterns of subsequent detection analysis, shorten the detection time and further improve the detection efficiency.
In order to solve the problems, the invention provides a defect detection method, which comprises the steps of providing a wafer, scanning the detection surface to obtain a scanning image of the detection surface, providing a design image, wherein the design image comprises a plurality of second unit patterns corresponding to the first unit patterns, and screening the scanning image according to the design image to remove interference defect unit patterns in the first unit patterns.
Optionally, the method for screening the scanned image according to the design image comprises the steps of obtaining screening values according to the design image and the scanned image, providing screening conditions corresponding to the screening values, comparing the screening values with the screening conditions according to the screening values, judging whether each first unit pattern is an interference defect unit pattern or not, and deleting the interference defect unit pattern from the scanned image when the first unit pattern is the interference defect unit pattern.
Optionally, the screening value comprises an overlapping value of the first unit graph and the second unit graph corresponding to the first unit graph, a characteristic size value of the second unit graph and a graph interval value of the second unit graph.
Optionally, the screening conditions include an overlap ratio threshold, a feature size threshold, and a pattern pitch threshold.
Optionally, the method for judging whether each first unit pattern is an interference defect unit pattern according to comparison of the screening value and the screening condition comprises judging that each first unit pattern is an interference defect unit pattern when the overlap rate value is smaller than or equal to the overlap rate threshold, the feature size value is larger than or equal to the feature size threshold and the pattern interval value is larger than or equal to the pattern interval threshold.
Optionally, the overlap value is a ratio of an overlap area of the first unit pattern and the corresponding second unit pattern to an area of the second unit pattern.
Optionally, the method for obtaining the overlapping area of the first unit graph and the corresponding second unit graph comprises the steps of overlapping and aligning the design image and the scanning image, wherein the first unit graph corresponds to the second unit graph, and obtaining the overlapping area of the first unit graph and the corresponding second unit graph through Boolean operation.
Optionally, the pattern pitch value is a minimum pitch value between a single second unit pattern and another adjacent second unit pattern in the design image.
Optionally, the range of the overlapping rate threshold is 60% -90%.
Optionally, the method for acquiring the feature size threshold comprises the steps of providing a first magnification and a minimum feature size value specified in a design rule of the design image, wherein the feature size threshold is the product of the minimum feature size value and the first magnification.
Optionally, the range of the first magnification is 2-5 times.
Optionally, the method for obtaining the graphic spacing threshold comprises the steps of providing a second magnification and a minimum spacing size value specified in a design rule of the design image, wherein the spacing size threshold is the product of the minimum spacing size value and the second magnification.
Optionally, the second magnification range is 2-5 times.
Correspondingly, the invention also provides a defect detection system which comprises a scanning unit and a screening unit, wherein the scanning unit is used for acquiring a scanning image of the wafer detection surface, the scanning image comprises a plurality of first unit patterns, the design image unit is used for providing a design image, the design image comprises a plurality of second unit patterns corresponding to the first unit patterns, and the screening unit is used for screening the scanning image according to the design image to remove the interference defect unit patterns in the first unit patterns.
The screening unit comprises a measuring module for measuring the design image and the scanning image to obtain screening values, a screening condition module for providing screening conditions corresponding to the screening values, a judging module for comparing the screening values with the screening conditions to judge whether each first unit pattern is an interference defect unit pattern or not, and an operation module for deleting the interference defect unit pattern from the scanning image when the first unit pattern is the interference defect unit pattern.
Optionally, the screening conditions include an overlap ratio threshold, a feature size threshold, and a pattern pitch threshold.
Optionally, the screening value comprises an overlapping value of the first unit graph and the second unit graph corresponding to the first unit graph, a characteristic size value of the second unit graph and a graph interval value of the second unit graph.
Compared with the prior art, the technical scheme of the invention has the following advantages:
in the defect detection method provided by the technical scheme of the invention, the scanning image is screened by designing the image, and part of interference defect unit patterns in the first unit patterns of the scanning image are screened and removed, so that the number of the first unit patterns of subsequent detection and analysis is effectively reduced, the detection time is shortened, and the detection efficiency is improved.
Drawings
FIG. 1 is a flow chart of steps of a defect detection method;
FIG. 2 is a flowchart illustrating steps of a defect detection method according to an embodiment of the present invention;
FIGS. 3 to 8 are schematic structural diagrams illustrating steps of a defect detecting method according to an embodiment of the present invention;
FIG. 9 is a schematic diagram of a defect detection system according to an embodiment of the present invention.
Detailed Description
As described in the background art, the detection efficiency in the defect detection method of the prior art needs to be improved.
FIG. 1 is a flow chart of an embodiment of a defect detection method, comprising:
step S11, providing a wafer, wherein the wafer comprises a detection surface;
step S12, scanning the detection surface to obtain a scanning image of the detection surface, wherein the scanning image comprises a plurality of defect unit patterns;
and S13, detecting and analyzing a plurality of defect unit patterns in the scanned image one by one, and judging whether the defect unit patterns are interference defect unit patterns or not.
In the above-mentioned detection method, a computer is used to automatically find a plurality of defect unit patterns on the wafer scan image, however, only a small part of the defect unit patterns are designed defect unit patterns formed due to design reasons, and the rest of the defect unit patterns are interference defect unit patterns formed due to deviations in the manufacturing process, so that the part of interference defect unit patterns can be modified and eliminated by adjusting parameters in the manufacturing process, and the improvement process is simpler and has a short period. And the other part of the design defect unit patterns need to be modified again, the modification process is complex, and therefore, the part of the design defect unit patterns need to be separately detected and separated. However, in the existing inspection and analysis method, it is still necessary to inspect and analyze all the defective cell patterns one by one to determine which is actually formed due to design reasons, and the number of defective cell patterns required to be inspected and analyzed in this process is large, which is time-consuming, resulting in low inspection efficiency.
In order to solve the problems, the invention provides a defect detection method and a defect detection system, which effectively reduce the number of first unit patterns for subsequent detection analysis and shorten the detection time by partially screening and removing the interference defect unit patterns in the first unit patterns, thereby improving the detection efficiency.
In order that the above-recited objects, features and advantages of the present invention will become more readily apparent, a more particular description of the invention briefly described above will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings.
FIG. 2 is a flow chart of a defect detection method according to an embodiment of the present invention, including:
step S21, providing a wafer, wherein the wafer comprises a detection surface;
step S22, scanning the detection surface to obtain a scanning image of the detection surface, wherein the scanning image comprises a plurality of first unit patterns;
step S23, providing a design image, wherein the design image comprises a plurality of second unit graphs corresponding to the first unit graphs;
And step S24, screening the scanned image according to the design image, and removing the interference defect unit pattern in the first unit pattern.
The defect detection step is described in detail below with reference to the accompanying drawings.
Fig. 3 to 8 are schematic structural diagrams illustrating steps of a defect detection method according to an embodiment of the present invention.
Referring to fig. 3, a wafer 200 is provided, the wafer 200 including a detection surface.
The wafer 200 has a semiconductor structure therein including an electrical interconnect structure, a gate structure, and a device structure, and the detection surface of the wafer exposes one or more top surfaces of the electrical interconnect structure, gate structure, and device structure.
Defects exist on the top surface of the semiconductor structure exposed by the detection surface, and are partially the process defects caused by process deviation, and partially the design defects generated during design, in this embodiment, the design defects are required to be obtained.
Referring to fig. 4, the detection surface is scanned to obtain an overall scan image of the detection surface, and it should be noted that, the scan image 210 in fig. 4 is a portion of the overall scan image of the detection surface, and the scan image 210 includes a plurality of first unit patterns 211.
In this embodiment, the first unit pattern 211 includes an interference defective unit pattern formed due to a deviation in a manufacturing process and a design defective unit pattern formed due to a design reason.
In this embodiment, the scan image 210 is an image of an exposed electrical interconnection structure of the detection surface, and in other embodiments, the scan image may also be an image of a gate structure or an image of a device structure of the detection surface.
Referring to fig. 5, a design image 220 is provided, the design image 220 includes a plurality of second unit patterns 221 corresponding to the first unit patterns 211.
Fig. 5 is a design image corresponding to the scan image in fig. 4.
In this embodiment, the design image 220 is used to form the semiconductor structure.
The scan image 210 is filtered according to the design image 220 to remove the interference defect unit pattern in the first unit pattern 211, please refer to fig. 6 to 8.
In this embodiment, please continue to refer to fig. 4 and fig. 5, the method for screening the scanned image 210 according to the design image 220 includes obtaining screening values according to the design image 220 and the scanned image 210, providing screening conditions corresponding to the screening values, and comparing the screening values with the screening conditions to determine whether each of the first unit patterns 211 is an interference defect unit pattern.
In this embodiment, the filtering values include an overlap value OR of the first unit pattern 211 and the second unit pattern 221 corresponding thereto, a feature size value a CD of the second unit pattern 221, and a pattern pitch value a S of the second unit pattern 221.
In this embodiment, the screening conditions include an overlap ratio threshold T OR, a feature size threshold T CD, and a pattern pitch threshold T S.
In this embodiment, the method for determining whether each first unit pattern 211 is an interference defect unit pattern according to the comparison between the screening value and the screening condition includes determining that the first unit pattern 211 is an interference defect unit pattern when the overlap rate value OR is less than OR equal to the overlap rate threshold T OR, the feature size value a CD is greater than OR equal to the feature size threshold T CD, and the pattern pitch value a S is greater than OR equal to the pattern pitch threshold T S.
In this embodiment, the overlap value OR is a ratio of the overlapping area A1 of the first unit pattern 211 and the corresponding second unit pattern 221 to the area A2 of the second unit pattern 221, that is, or=a1/A2.
In this embodiment, please refer to fig. 6 and 7, fig. 7 is a partially enlarged schematic diagram 7 of fig. 6, and the method for obtaining the overlapping area of the first unit pattern 211 and the corresponding second unit pattern 221 includes overlapping the design image 220 with the scan image 210, the first unit pattern 211 and the second unit pattern 221 corresponding, and obtaining the overlapping area A1 of the first unit pattern 211 and the corresponding second unit pattern 221 through boolean operation (Boolean Operation).
In this embodiment, the feature size value a CD is the size of each side length of each second unit graphic 221 in the design image, and the shapes of different second unit graphics 221 may be different, such as rectangles or polygons in other forms.
In this embodiment, the pattern pitch value a S is a minimum pitch value between a single second unit pattern 221 and another second unit pattern adjacent thereto in the design image.
In this embodiment, the range of the overlapping rate threshold is 60% -90%.
The first unit pattern 211 in the scan image 210 corresponding to the defect and the second unit pattern 221 in the design image 220 are relatively deviated due to the defect generated by the manufacturing process deviation, and the overlapping area between the first unit pattern 211 in the scan image 210 corresponding to the defect and the second unit pattern 221 in the design image 220 is relatively smaller due to the defect generated by the design, and the overlapping area between the first unit pattern 211 in the scan image 210 corresponding to the defect and the second unit pattern 221 is relatively larger due to the defect generated by the design, so that the overlapping rate threshold value is set according to the difference, and whether the overlapping rate value is smaller than or equal to the set overlapping rate threshold value is judged by comparison.
In this embodiment, the method for obtaining the feature size threshold includes providing a first magnification α and a minimum feature size value R CD specified in a design rule of the design image 220, where the feature size threshold is a product of the minimum feature size value and the first magnification.
Since the specified minimum feature size value in the design rule is the minimum feature size in the design image, the feature size of the second unit pattern 221 in the design image may not be smaller than the minimum feature size value, and thus by amplifying the minimum feature size value and further making the feature size value of the second unit pattern 221 be greater than or equal to the value, it is required to further detect whether the first unit pattern 211 corresponding to the second unit pattern 221 is an interference defect unit pattern formed by the manufacturing process deviation.
In this embodiment, the range of the first magnification α is 2 to 5 times.
In this embodiment, the method for obtaining the graphic pitch threshold includes providing a second magnification β and a minimum pitch size value R S specified in the design rule of the design image 220, where the pitch size range is a product of the minimum pitch size value and the second magnification.
Since the specified minimum pitch size value in the design rule is the minimum pitch size in the design image, the pitch size of the second unit pattern 221 in the design image may not be smaller than the minimum pitch size value, and thus by amplifying the minimum pitch size value, and the pitch size value of the second unit pattern 221 is also greater than or equal to the value, it is indicated that the design of the second unit pattern 221 is satisfactory, and it is necessary to further detect whether the first unit pattern 211 corresponding to the second unit pattern 221 is an interference defect unit pattern formed by the manufacturing process deviation.
In this embodiment, the range of the second magnification β is 2-5 times.
Referring to fig. 8, when the first unit pattern 211 is a disturbance defect unit pattern, the disturbance defect unit pattern is deleted from the scan image 210.
In this embodiment, after the interference defect unit patterns in the scanned image are deleted, the remaining first unit patterns 211 still need to be detected one by one.
Because the above method can partially remove the interference defect unit patterns formed by the deviation of the manufacturing process in the scanned image 210, the number of the first unit patterns which need to be detected and analyzed one by one in the following process can be greatly reduced, so that the detection time is shortened, and the detection efficiency is improved.
Accordingly, referring to fig. 9, an embodiment of the present invention further provides a defect detection system, including:
the scanning unit 300 is configured to obtain a scanned image of the wafer detection surface, where the scanned image includes a plurality of first unit patterns;
A design image unit 310 for providing a design image including a plurality of second unit patterns corresponding to the first unit patterns;
And a screening unit 320, for screening the scanned image according to the design image, so as to remove the interference defect unit pattern in the first unit pattern.
The following detailed description will be given with reference to the accompanying drawings.
In this embodiment, please continue to refer to fig. 9, the filtering unit 320 includes:
a measurement module 321 for obtaining a screening value according to the measurement of the design image and the scanning image;
A screening condition module 322 providing a screening condition corresponding to the screening value;
a judging module 323, configured to judge whether each of the first unit patterns is an interference defect unit pattern according to comparison between the screening value and the screening condition;
and an operation module 324, configured to delete the disturbing defect unit pattern from the scanned image when the first unit pattern is the disturbing defect unit pattern.
In this embodiment, the screening value includes an overlap value of the first unit pattern and the second unit pattern corresponding to the first unit pattern, a feature size value of the second unit pattern, and a pattern pitch value of the second unit pattern.
In this embodiment, the screening conditions include an overlap ratio threshold, a feature size threshold, and a pattern pitch threshold.
In this embodiment, the determining module 323 compares the screening value with the screening condition, and determines whether each first unit pattern is an interference defect unit pattern according to the specific implementation that when the overlap rate value is less than or equal to the overlap rate threshold, the feature size value is greater than or equal to the feature size threshold, and the pattern pitch value is greater than or equal to the pattern pitch threshold, the first unit pattern is determined to be an interference defect unit pattern.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (9)
1. A defect detection method, comprising:
providing a wafer, wherein the wafer comprises a detection surface;
scanning the detection surface to obtain a scanning image of the detection surface, wherein the scanning image comprises a plurality of first unit patterns;
Providing a design image, wherein the design image comprises a plurality of second unit patterns corresponding to the first unit patterns;
Screening the scanned image according to the design image to remove the interference defect unit pattern formed by the deviation of the manufacturing process in the first unit pattern,
The method for screening the scanning image according to the design image comprises the steps of obtaining screening values according to measurement of the design image and the scanning image, providing screening conditions corresponding to the screening values, comparing the screening values with the screening conditions according to the screening values, judging whether each first unit graph is an interference defect unit graph or not, and deleting the interference defect unit graph from the scanning image when the first unit graph is the interference defect unit graph;
The screening value comprises an overlapping value of the first unit graph and the corresponding second unit graph, a characteristic size value of the second unit graph and a graph interval value of the second unit graph, wherein the overlapping value is a ratio of the overlapping area of the first unit graph and the corresponding second unit graph to the area of the second unit graph;
The screening conditions comprise an overlapping rate threshold value, a characteristic size threshold value and a pattern interval threshold value;
And comparing the screening value with the screening condition, and judging whether each first unit pattern is an interference defect unit pattern or not, wherein when the overlapping rate value is smaller than or equal to the overlapping rate threshold value, the characteristic size value is larger than or equal to the characteristic size threshold value and the pattern interval value is larger than or equal to the pattern interval threshold value, judging that the first unit pattern is an interference defect unit pattern.
2. The defect detection method of claim 1, wherein the step of obtaining the overlapping area of the first cell pattern and the corresponding second cell pattern comprises overlapping the design image and the scan image, the first cell pattern corresponding to the second cell pattern, and obtaining the overlapping area of the first cell pattern and the corresponding second cell pattern by Boolean operation.
3. The defect detection method of claim 1, wherein the pattern pitch value is a minimum pitch value between a single second cell pattern and another second cell pattern adjacent thereto in the design image.
4. The defect detection method of claim 1, wherein the overlap ratio threshold is in the range of 60% -90%.
5. The defect detection method of claim 1 wherein the method of obtaining the feature size threshold comprises providing a first magnification and a minimum feature size value specified in a design rule of the design image, the feature size threshold being a product of the minimum feature size value and the first magnification.
6. The defect detection method of claim 5, wherein the first magnification is in a range of 2-5 times.
7. The defect detection method of claim 1 wherein the method of obtaining the pattern pitch threshold comprises providing a second magnification and a minimum pitch size value specified in a design rule of the design image, the pitch size threshold being a product of the minimum pitch size value and the second magnification.
8. The defect detection method of claim 7, wherein the second magnification is in a range of 2-5 times.
9. A defect detection system, comprising:
the scanning unit is used for acquiring a scanning image of the wafer detection surface, and the scanning image comprises a plurality of first unit patterns;
A design image unit for providing a design image, wherein the design image comprises a plurality of second unit graphics corresponding to the first unit graphics;
The device comprises a design image, a scanning unit, a screening condition module, a judging module and an operation module, wherein the design image is used for designing a scanning image, the scanning image is used for carrying out screening according to the design image, the screening unit is used for removing interference defect unit patterns formed by deviation of a manufacturing process in the first unit patterns, the screening unit comprises a measuring module, a screening condition module, a judging module and an operation module, the measuring module is used for measuring the design image and the scanning image to obtain screening values, the screening condition module is used for providing screening conditions corresponding to the screening values, the judging module is used for comparing the screening values with the screening conditions to judge whether each first unit pattern is the interference defect unit pattern, and the operation module is used for deleting the interference defect unit pattern from the scanning image when the first unit pattern is the interference defect unit pattern;
the screening conditions comprise an overlapping rate threshold value, a characteristic size threshold value and a graph spacing threshold value;
The screening value comprises an overlapping value of the first unit graph and the second unit graph corresponding to the first unit graph, a characteristic size value of the second unit graph and a graph interval value of the second unit graph, wherein the overlapping value is a ratio of an overlapping area of the first unit graph and the second unit graph corresponding to the first unit graph to an area of the second unit graph.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910838099.5A CN112444526B (en) | 2019-09-05 | 2019-09-05 | Defect detection method and defect detection system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910838099.5A CN112444526B (en) | 2019-09-05 | 2019-09-05 | Defect detection method and defect detection system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112444526A CN112444526A (en) | 2021-03-05 |
| CN112444526B true CN112444526B (en) | 2025-03-21 |
Family
ID=74733201
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910838099.5A Active CN112444526B (en) | 2019-09-05 | 2019-09-05 | Defect detection method and defect detection system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112444526B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115132599A (en) * | 2021-03-26 | 2022-09-30 | 中芯国际集成电路制造(上海)有限公司 | Defect detection method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09266235A (en) * | 1996-03-28 | 1997-10-07 | Sony Corp | Failure analysis method and its system |
| CN102142355A (en) * | 2010-02-02 | 2011-08-03 | 吕一云 | Application method of object manufacturing defects |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3752849B2 (en) * | 1997-07-04 | 2006-03-08 | 株式会社日立製作所 | Pattern defect inspection apparatus and pattern defect inspection method |
| JP2000068342A (en) * | 1998-08-21 | 2000-03-03 | Sony Corp | Wafer appearance inspection apparatus and wafer appearance inspection method |
| JP4105809B2 (en) * | 1998-09-08 | 2008-06-25 | 株式会社ルネサステクノロジ | Appearance inspection method and appearance inspection apparatus |
| JP2000346627A (en) * | 1999-06-07 | 2000-12-15 | Toray Eng Co Ltd | Inspection system |
| KR20010039251A (en) * | 1999-10-29 | 2001-05-15 | 윤종용 | Method of detecting defects in reticle pattern by comparing pattern of chip with normal pattern |
| JP2007081293A (en) * | 2005-09-16 | 2007-03-29 | Toshiba Corp | Inspection method, semiconductor device manufacturing method, and program |
| JP5068591B2 (en) * | 2007-06-29 | 2012-11-07 | 株式会社日立ハイテクノロジーズ | Semiconductor defect classification method, semiconductor defect classification device, semiconductor defect classification device program, semiconductor defect inspection method, and semiconductor defect inspection system |
| JP5470008B2 (en) * | 2009-11-25 | 2014-04-16 | 株式会社日立ハイテクノロジーズ | Defect review equipment and defect inspection system using design data |
| CN102623368A (en) * | 2012-03-31 | 2012-08-01 | 上海集成电路研发中心有限公司 | Wafer defect detection method |
| JP5948138B2 (en) * | 2012-05-11 | 2016-07-06 | 株式会社日立ハイテクノロジーズ | Defect analysis support device, program executed by defect analysis support device, and defect analysis system |
| US8826200B2 (en) * | 2012-05-25 | 2014-09-02 | Kla-Tencor Corp. | Alteration for wafer inspection |
| CN102789999A (en) * | 2012-08-16 | 2012-11-21 | 上海华力微电子有限公司 | Defect detecting method for utilizing graphic features to scan and manufacturing method of semiconductor chip |
| CN103915361A (en) * | 2014-04-08 | 2014-07-09 | 上海华力微电子有限公司 | Method for detecting chip defects |
| CN107978536A (en) * | 2016-10-25 | 2018-05-01 | 中芯国际集成电路制造(上海)有限公司 | The CDSEM scan methods of pattern in a kind of wafer domain |
| TWI641961B (en) * | 2017-07-21 | 2018-11-21 | Elite Semiconductor, Inc. | Design and layout-based fast online defect diagnosis, classification and sampling method and system |
| US11016035B2 (en) * | 2017-09-18 | 2021-05-25 | Elite Semiconductor Inc. | Smart defect calibration system and the method thereof |
| US10445452B2 (en) * | 2017-10-04 | 2019-10-15 | Mentor Graphics Corporation | Simulation-assisted wafer rework determination |
| CN109712902B (en) * | 2018-12-25 | 2021-07-27 | 上海华力微电子有限公司 | Method for automatically scanning defects |
-
2019
- 2019-09-05 CN CN201910838099.5A patent/CN112444526B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09266235A (en) * | 1996-03-28 | 1997-10-07 | Sony Corp | Failure analysis method and its system |
| CN102142355A (en) * | 2010-02-02 | 2011-08-03 | 吕一云 | Application method of object manufacturing defects |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112444526A (en) | 2021-03-05 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP4014379B2 (en) | Defect review apparatus and method | |
| US7760929B2 (en) | Grouping systematic defects with feedback from electrical inspection | |
| KR101600209B1 (en) | Region setting device, inspection device, region setting method, and inspection method using region setting method | |
| CN101785009B (en) | Computer-implemented method of determining whether an actual defect is a potentially systematic or a potentially random defect | |
| JP3668215B2 (en) | Pattern inspection device | |
| US7681159B2 (en) | System and method for detecting defects in a semiconductor during manufacturing thereof | |
| US8289508B2 (en) | Defect detection recipe definition | |
| KR20180095715A (en) | Improved defect sensitivity of semiconductor wafer testers using design data with wafer image data | |
| CN103500722B (en) | A kind of electron beam defect detection method | |
| CN114994073B (en) | Die defect scanning detection and analysis method | |
| JP2010034138A (en) | Pattern inspection apparatus, pattern inspection method, and program | |
| US20080225284A1 (en) | Method, apparatus, and computer program product for optimizing inspection recipes using programmed defects | |
| US7101722B1 (en) | In-line voltage contrast determination of tunnel oxide weakness in integrated circuit technology development | |
| CN112038248A (en) | Method and system for establishing semiconductor defect scanning program | |
| CN118587150A (en) | A wafer defect detection method | |
| CN112444526B (en) | Defect detection method and defect detection system | |
| JPH11231507A (en) | Method and device for inspecting mask | |
| CN116263559A (en) | Method for predicting optical proximity defect on graph to be detected based on machine learning | |
| TW201925804A (en) | Method for diagnosing a semiconductor wafer | |
| JP3314217B2 (en) | Appearance inspection device | |
| JP4755833B2 (en) | Sample defect inspection and sample inspection method | |
| JP2005123566A (en) | Method of controlling defect | |
| KR20080061938A (en) | Process defect inspection method on wafer | |
| JP2010019561A (en) | Flaw inspection device and flaw inspection method | |
| CN1249800C (en) | A method to monitor real defects by excluding repetitive defects that do not affect yield |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |