CN112436749B

CN112436749B - Control method and control circuit of inverter

Info

Publication number: CN112436749B
Application number: CN202011073312.7A
Authority: CN
Inventors: 曾志成; 徐晖; 吴春; 何原明; 林森
Original assignee: Hangzhou Silan Microelectronics Co Ltd
Current assignee: Hangzhou Silan Microelectronics Co Ltd
Priority date: 2020-10-09
Filing date: 2020-10-09
Publication date: 2022-03-15
Anticipated expiration: 2040-10-09
Also published as: CN112436749A

Abstract

The embodiment of the invention discloses a control method and a control circuit of an inverter. The control method divides a current sampling process into a first stage and a second stage, any two-phase current of the inverter is sampled in the first stage to obtain three-phase current of the inverter, direct-current bus current of the inverter is sampled in the second stage to calculate the three-phase current of the inverter, a high modulation area and a low modulation area of the inverter do not need to be specially avoided, a current sampling reconstruction area is wide, the implementation is simple, phase shifting is not needed, and the method is beneficial to realizing current sampling of the inverter in a full modulation ratio range and obtaining accurate three-phase current.

Description

Control method and control circuit of inverter

Technical Field

The invention relates to the technical field of motor control, in particular to a control method and a control circuit of an inverter.

Background

With the rapid development of power electronic technology, a three-phase inverter system with an inverter as a main structure is widely used. The three-phase inverter system converts direct current into alternating current by using control methods such as Sinusoidal Pulse Width Modulation (SPWM) and Space Vector Pulse Width Modulation (SVPWM), and is widely applied to uninterruptible power supply systems of communication, factories and enterprises.

The current detection of the inverter is an important feedback link in a control system, and is related to the vector control performance and the current-limiting protection capability of the inverter. The three-phase inverter system can adjust the optimal control state of the three-phase inverter in real time only by accurately obtaining three-phase current in the full modulation ratio range.

The existing control methods of the three-phase inverter include the following steps: the first method is to install an isolated current sensor (e.g., a hall sensor) on the phase line of the three-phase inverter, and directly sample the current of the phase line, which has the disadvantage that the cost of the sensor is too high to be acceptable for some cost-effective systems. Secondly, sampling resistors are respectively installed on the lower bridge arms of the three-phase inverter to perform phase current sampling, and the method has the defects of more sampling channels and larger occupied resources. The third method is that peak current sampling is carried out on a sampling resistor connected in series with a direct current bus to reconstruct three-phase current, and the three-phase current finally passes through the direct current bus, so the current of the direct current bus can accurately reflect the change of the three-phase current.

Therefore, there is a need for an improvement to existing three-phase inverters to provide a low-cost control method that can perform reconstructed sampling of three-phase currents within the full modulation ratio range of the three-phase inverter.

Disclosure of Invention

In view of the above, an object of the present invention is to provide a method and a circuit for controlling an inverter having a wide current sampling reconstruction area.

According to an aspect of an embodiment of the present invention, there is provided a control method of an inverter, including:

selecting one of the first mode and the second mode according to the determination condition;

in a first mode, phase currents of any two phases of the inverter are sampled and reconstructed to obtain three-phase currents;

in a second mode, the DC bus current is sampled and reconstructed to obtain three phase current.

Optionally, the selecting one of the first mode and the second mode according to the determination condition includes:

setting a modulation boundary value;

comparing a modulation factor of the inverter with a modulation demarcation value;

selecting the first mode in case the modulation factor is less than or equal to the modulation demarcation value, an

Selecting the second mode if the modulation factor is greater than the modulation demarcation value.

Optionally, the setting the modulation boundary value includes:

according to a space vector pulse width modulation algorithm, two adjacent basic voltage vectors required by synthesizing expected output voltage are obtained;

obtaining a first action time and a second action time of the two adjacent basic voltage vectors in each PWM control period;

obtaining a third action time of a zero voltage vector in the PWM control period according to the first action time and the second action time; and

and obtaining the modulation boundary value according to the sampling control time and the third acting time.

Optionally, the first action time and the second action time are obtained according to the following formulas:

T_X＝mT_s sin(60°-θ_X)

T_Y＝mT_s sinθ_X

wherein, T_sFor PWM control period, T_XAnd T_YRespectively corresponding to two adjacent basic voltage vectors U_XAnd U_Y(X, Y) ═ 4,6, (6,2), (2,3), (3,1), (1,5), or (5,4)) at a first action time and a second action time of one PWM control period, m is a modulation coefficient of the space vector pulse width modulation algorithm, θ is_XFor a desired output voltage Uref and a basic voltage vector U_XAnd 0 is not more than theta_X＜60°。

Optionally, the modulation factor is obtained according to the following formula:

where | Uref | is the absolute value of the desired output voltage, U_dcIs the voltage of the dc bus of the inverter.

Optionally, the modulation boundary value satisfies the following condition: such that the third action time is greater than the sampling control time.

Optionally, the space vector pulse width modulation algorithm includes a seven-segment output and a five-segment output.

Optionally, when the space vector pulse width modulation algorithm is a seven-segment output, the third action time is obtained according to the following formula:

T₀＝(T_s-T_X-T_Y)/2

wherein, T_XAnd T_YRespectively corresponding to two adjacent basic voltage vectors U_XAnd U_Y(X, Y) ═ 4,6, (6,2), (2,3), (3,1), (1,5), or (5,4)) at the first and second active times, T, of the PWM control period_sIs the PWM control period.

Optionally, the modulation boundary value is obtained according to the following formula:

M_min＝1-2T_set/T_s

wherein M is_minFor modulating the boundary value, T_setControlling the time for said sampling, T_sIs the PWM control period.

Optionally, when the space vector pulse width modulation algorithm is output in a five-segment manner, the third action time is obtained according to the following formula:

T₀＝T_s-T_X-T_Y

wherein, T_XAnd T_YRespectively corresponding to two adjacent basic voltage vectors U_XAnd U_Y(X, Y) ═ 4,6, (6,2), (2,3), (3,1), (1,5), or (5,4)) in the first role of the PWM control periodTime and second action time, T_sIs the PWM control period.

M_min＝1-T_set/T_s

Optionally, the inverter includes multiple phase bridge arms connected in parallel between a positive end and a negative end of the dc power supply, each phase bridge arm includes power switching tubes respectively disposed in an upper bridge arm and a lower bridge arm of each phase bridge arm, and the power switching tube of the lower bridge arm of the phase sampled in an actual sampling window of the phase end is in a conducting state under the action of a PWM control signal, where setting the modulation boundary value further includes:

modulating the expected output voltage according to the space vector pulse width modulation algorithm to obtain a PWM control signal of the inverter; and

and obtaining the sampling control time according to the dead time of the PWM control signal, the delay on-time and delay off-time of a lower bridge arm power switching tube of the inverter, the current sampling signal oscillation time of a phase line end of the inverter, and the sampling holding time and the sampling starting delay time of a sampling reconstruction module of the inverter.

Optionally, the sampling control time is obtained according to the following formula:

T_set＝T_dead+T_on-T_off+T_ring+T_adsmp+T_wait

wherein, T_setControlling the time for said sampling, T_deadIs the dead time, T, of the PWM control signal_onIs the delayed conduction time, T, of the lower bridge arm power switching tube of the inverter_offIs the delayed turn-off time, T, of the lower bridge arm power switching tube of the inverter_ringSampling the oscillation time of the signal for the current at the phase line end of the inverter, T_adsmpFor sampling of the inverterSample and hold time, T, of building blocks_waitA sample start delay time for a sample reconstruction module of the inverter.

setting a desired minimum sample time value;

obtaining a duration value of an actual samplable window in each PWM control period;

wherein the first mode is selected if the duration values of the actual samplable windows in a plurality of consecutive PWM control periods are all greater than/equal to the desired minimum sampling time value,

selecting the second mode if the duration values of the actual samplable windows in a plurality of consecutive PWM control periods are not satisfied to be greater than/equal to the desired minimum sampling time value.

Optionally, the selecting one of the first mode and the second mode according to the determination condition further includes:

in each PWM control period, judging whether the duration value is smaller than the expected minimum sampling time value;

selecting the second mode if the duration value is less than the desired minimum sample time value;

if the duration value is greater than or equal to the expected minimum sampling time value, judging whether the duration values in a plurality of continuous PWM control periods adjacent to the current PWM control period are all greater than or equal to the expected minimum sampling time value;

and if the duration values in a plurality of continuous PWM control periods adjacent to the current PWM control period are all larger than or equal to the expected minimum sampling time value, selecting the first mode.

Optionally, the consecutive plurality of PWM control periods includes all PWM control periods in at least one current fundamental period.

Optionally, the desired minimum sampling time value is set according to the following formula:

T_E＝T_ring+T_adsmp+T_wait

wherein, T_ERepresenting said desired minimum sample time value, T_ringRepresenting the current sampling signal oscillation time, T, of the phase terminal of the inverter_adsmpRepresenting a sample-and-hold time, T, of a sample reconstruction module of the inverter_waitA sample on delay time of a sample reconstruction module of the inverter is represented.

Optionally, the inverter includes multiple phase bridge arms connected in parallel between a positive end and a negative end of the dc power supply, each phase bridge arm includes power switching tubes respectively disposed in an upper bridge arm and a lower bridge arm of each phase bridge arm, the power switching tube of the lower bridge arm of the phase sampled in an actual sampling window of the phase end is in a conducting state under the action of a PWM control signal, where obtaining a duration value of the actual sampling window in each PWM control period includes:

obtaining the delayed on-time and the delayed off-time of a lower bridge arm power switching tube of the inverter in the PWM control period and the dead time of a PWM control signal;

obtaining a time window which can be sampled in each PWM control period; and

and calculating the duration value of the actual sampling window in each PWM control period according to the delay on-time, the delay off-time, the dead time and the sampling available time window.

Optionally, the duration value of the actual samplable window in each PWM control period is calculated according to the following formula:

T_R＝T_G-T_dead-T_on+T_off

wherein, T_RRepresenting said value of duration, T_GRepresenting said time window in which sampling can be performed, T_deadRepresenting said dead time, T_onRepresenting said delayed on-time, T_offRepresenting the delayed turn-off time.

Optionally, the control method further includes: the time window in which sampling can be performed is calculated according to the following formula:

T_G＝T_s-max(T_a,T_b,T_c)

wherein, T_sRepresenting the PWM control period, T_a、T_b、T_cRespectively representing the conduction time max (T) of the power switching tubes of the upper bridge arm of the three-phase bridge arm of the inverter in each PWM control period_a,T_b,T_c) And the maximum value of the conduction time of the power switching tubes of the upper bridge arm of the three-phase bridge arm of the inverter in each PWM control period is represented.

Optionally, the control method further includes: modulating a desired output voltage based on a voltage modulation algorithm to obtain the PWM control signal, the voltage modulation algorithm comprising SPWM, SVPWM, or DPWM.

Optionally, in the second mode, sampling the dc bus current and reconstructing to obtain a three-phase current includes: in a second mode, a peak current of the dc bus is sampled.

Optionally, in the second mode, sampling the dc bus current and reconstructing to obtain a three-phase current includes:

dividing PWM control signals of an upper bridge arm power switching tube of the inverter into a maximum phase control signal, a middle phase control signal and a minimum phase control signal according to the conduction time of the upper bridge arm power switching tube in each PWM control period;

sampling a direct current bus current at a first time interval between edges of the maximum phase control signal and the intermediate phase control signal to obtain a phase current of a phase corresponding to the maximum phase control signal;

sampling a direct current bus current at a second time interval between edges of the minimum phase control signal and the intermediate phase control signal to obtain a phase current of a corresponding phase of the minimum phase control signal; and

and calculating the phase current of the bridge arm corresponding to the intermediate phase control signal according to the phase current of the phase corresponding to the maximum phase control signal and the phase current of the phase corresponding to the minimum phase control signal.

According to another aspect of the embodiments of the present invention, there is provided a control circuit of an inverter, including:

the first sampling reconstruction module is used for sampling phase currents of any two phases of the inverter and reconstructing the phase currents to obtain three-phase currents;

the second sampling reconstruction module is used for sampling the direct current bus current in the inverter and reconstructing to obtain a three-phase current; and

and the selection module is used for selecting one of the first sampling reconstruction module and the second sampling reconstruction module according to the judgment condition.

Optionally, the selecting module includes:

a first setting unit for setting a modulation boundary value;

the first comparison unit is used for comparing the modulation coefficient of the inverter with a modulation boundary value, selecting the first sampling reconstruction module when the modulation coefficient is smaller than or equal to the modulation boundary value, and selecting the second sampling reconstruction module when the modulation coefficient is larger than the modulation boundary value.

Optionally, the first setting unit includes:

the vector voltage calculation unit is used for obtaining two adjacent basic voltage vectors required by synthesizing the expected output voltage according to a space vector pulse width modulation algorithm;

the first time calculation unit is used for obtaining a first action time and a second action time of the two adjacent basic voltage vectors in each PWM control period;

the second time calculation unit is used for obtaining a third action time of a zero voltage vector in the PWM control period according to the first action time and the second action time; and

and the output unit is used for obtaining the modulation boundary value according to the sampling control time and the third acting time.

Optionally, the first time calculating unit obtains the first acting time and the second acting time according to the following formulas:

T_X＝mT_s sin(60°-θ_X)

T_Y＝mT_s sinθ_X

Optionally, the output unit obtains the modulation factor according to the following formula:

Optionally, when the space vector pulse width modulation algorithm is output in a seven-segment manner, the second time calculation unit obtains the third action time according to the following formula:

T₀＝(T_s-T_X-T_Y)/2

wherein, T_XAnd T_YRespectively corresponding to two adjacent basic voltage vectors U_XAnd U_Y(X, Y) ═ 4,6, (6,2), (2,3), (3,1), (1,5), or (5,4)) at the first and second active times, T, of the PWM control period_sIs said PThe WM controls the cycle.

Optionally, the output unit obtains the modulation boundary value according to the following formula:

M_min＝1-2T_set/T_s

Optionally, when the space vector pulse width modulation algorithm is output in a five-segment manner, the second time calculation unit obtains the third action time according to the following formula:

T₀＝T_s-T_X-T_Y

M_min＝1-T_set/T_s

Optionally, the first setting unit further includes a sampling control time calculating unit, and the sampling control time calculating unit obtains the sampling control time according to the following formula:

T_set＝T_dead+T_on-T_off+T_ring+T_adsmp+T_wait

wherein, T_setControlling the time for said sampling, T_deadFor dead time of PWM control signal, T_onIs the delayed conduction time, T, of the lower bridge arm power switching tube of the inverter_offIs the delayed turn-off time, T, of the lower bridge arm power switching tube of the inverter_ringFor the production of said inverterCurrent sampling signal oscillation time, T, of sample reconstruction module_adsmpSample and hold time, T, for a sample reconstruction module of the inverter_waitA sample start delay time for a sample reconstruction module of the inverter.

Optionally, the first sampling reconstruction module is configured to sample and reconstruct the phase currents of any two phases in the inverter to obtain three-phase currents, when the duration values of the actual samplable windows in a plurality of consecutive PWM control periods are all greater than or equal to the expected minimum sampling time value,

the second sampling reconstruction module is used for sampling the direct current bus current and reconstructing to obtain a three-phase current under the condition that the duration values of the actual sampling windows in a plurality of continuous PWM control periods are not larger than/equal to the expected minimum sampling time value.

Optionally, the selecting module includes:

a second setting unit for setting a desired minimum sampling time value;

the sampling time acquisition unit is used for acquiring the duration value of an actual sampling window in each PWM control period;

the first judging unit is used for judging whether the duration value is smaller than the expected minimum sampling time value or not in each PWM control period, and selecting the second sampling reconstruction module to sample the direct current bus current and reconstruct the direct current bus current to obtain a three-phase current when the duration value is smaller than the expected minimum sampling time value; and

and the second judging unit is used for judging whether the duration values in a plurality of continuous PWM control periods adjacent to the current PWM control period are all larger than or equal to the expected minimum sampling time value when the duration value is larger than or equal to the expected minimum sampling time value, selecting the first sampling reconstruction module to sample the phase current of any two phases in the inverter and reconstruct the phase current to obtain a three-phase current when the duration values in the plurality of continuous PWM control periods adjacent to the current PWM control period are all larger than or equal to the expected minimum sampling time value, and otherwise selecting the second sampling reconstruction module to sample the direct-current bus current and reconstruct the direct-current bus current to obtain the three-phase current.

Optionally, the second setting unit sets the expected minimum sampling time value according to the following formula:

T_E＝T_ring+T_adsmp+T_wait

Optionally, the sampling time obtaining unit calculates a duration value of the actual sampling window in each PWM control period according to the following formula:

T_R＝T_G-T_dead-T_on+T_off

wherein, T_RRepresenting said value of duration, T_GRepresenting said time window in which sampling can be performed, T_deadRepresenting the dead time, T, of the PWM control signal_onRepresenting the delay conduction time T of the lower bridge arm power switching tube of the inverter in the PWM control period_offAnd representing the delayed turn-off time of a lower bridge arm power switching tube of the inverter in the PWM control period.

Optionally, the sampling time obtaining unit obtains the time window capable of sampling according to the following formula:

T_G＝T_s-max(T_a,T_b,T_c)

wherein, T_sRepresenting the PWM control period, T_a、T_b、T_cRespectively representing each PWM control periodThe conduction time, max (T), of the power switching tube of the upper bridge arm of the three-phase bridge arm of the inverter_a,T_b,T_c) And the maximum value of the conduction time of the power switching tubes of the upper bridge arm of the three-phase bridge arm of the inverter in each PWM control period is represented.

Optionally, the control circuit is further configured to modulate the desired output voltage based on a voltage modulation algorithm to obtain the PWM control signal, where the voltage modulation algorithm includes SPWM, SVPWM, or DPWM.

Optionally, the second sampling reconstruction module is configured to sample a peak current of a dc bus in the inverter and reconstruct the peak current to obtain a three-phase current.

Optionally, in each PWM control period, dividing the PWM control signal of the upper arm power switching tube into a maximum phase control signal, a middle phase control signal and a minimum phase control signal according to the on-time of the upper arm of the inverter,

the second sampling reconstruction module is suitable for sampling the current of the direct current bus at a first time interval between the edges of the maximum phase control signal and the middle phase control signal respectively to obtain the phase current of the phase corresponding to the maximum phase control signal, sampling the current of the direct current bus at a second time interval between the edges of the minimum phase control signal and the middle phase control signal to obtain the phase current of the phase corresponding to the minimum phase control signal, and calculating the phase current of the phase corresponding to the middle phase control signal according to the phase current of the phase corresponding to the maximum phase control signal and the phase current of the phase corresponding to the minimum phase control signal.

Optionally, the control circuit further includes: the first sampling unit is arranged on a direct-current bus of the inverter, and the second sampling reconstruction module is suitable for sampling through the first sampling unit to obtain direct-current bus current.

Optionally, the first sampling unit is selected from a sampling resistor or a current sensor.

Optionally, the control circuit further includes: the first sampling reconstruction module samples the current of the corresponding phase through the plurality of second sampling units to obtain the phase current.

Optionally, each second sampling unit includes a sampling resistor disposed on a bridge arm of the inverter, and the first sampling reconstruction module is adapted to sample voltage signals at two ends of the sampling resistor to obtain a current sampling signal of a phase current, and obtain the phase current of a corresponding phase according to the current sampling signal.

Optionally, each second sampling unit includes a current sensor disposed on a phase line of the inverter, and the first sampling reconstruction module samples through the current sensor to obtain a current sampling signal of a phase current, and obtains the phase current of a corresponding phase according to the current sampling signal.

Optionally, the first sampling reconstruction module is adapted to sample a voltage signal on an internal resistance of a power switch tube of a lower bridge arm of any two-phase bridge arm of the inverter to obtain a phase current of a corresponding phase.

The control method of the inverter and the control circuit thereof have the following advantages.

The control method of the embodiment of the invention divides the current sampling process into the first stage and the second stage, samples any two-phase current of the inverter in the first stage to obtain the three-phase current of the inverter, samples and reconstructs the direct current bus current of the inverter in the second stage to obtain the three-phase current of the inverter, a high modulation area and a low modulation area of the three-phase inverter do not need to be specially avoided, the current sampling reconstruction area is wide, the realization is simple, the phase shifting is not needed, and the current sampling of the inverter in the full modulation ratio range and the accurate three-phase current can be favorably realized.

Further, the control method of the present embodiment implements switching of the sampling control mode by comparing the duration value of the actual sampling window in the control period with the expected minimum sampling time value, and does not need to calculate the square root, so that the control method can be applied to a low-cost microcontroller with weak computing capability.

Furthermore, the switching method of the embodiment is smoother and simpler, does not cause the system to switch back and forth between two sampling modes to reduce the control performance of the system, and can be applied to general voltage modulation algorithms such as SPWM and DPWM.

In addition, the control method and the control circuit do not need to use expensive current sensors, the number of channels of the sampling module can be simplified, and the sampling cost of the inverter is reduced. The control mode has simple operation, can be realized without adopting an expensive control chip, and is beneficial to further reducing the production cost.

Drawings

The above and other objects, features and advantages of the present invention will become more apparent from the following description of the embodiments of the present invention with reference to the accompanying drawings.

Fig. 1 shows a schematic view of a principle for controlling an electric machine with an inverter;

FIG. 2 shows a vector diagram of a control scheme of a space vector pulse width modulation algorithm;

fig. 3 shows a flow chart diagram of a control method of an inverter according to a first embodiment of the invention;

FIG. 4 shows a schematic diagram of the synthesis of the desired output voltage in a sector in a space vector pulse width modulation algorithm;

fig. 5 shows a flow chart diagram of a control method of an inverter according to a second embodiment of the invention;

FIG. 6 illustrates a PWM control signal waveform during a PWM control period according to an embodiment of the present invention;

fig. 7A to 7C respectively show waveforms of PWM modulated waves obtained based on the SPWM, SVPWM and DPWM modulation methods;

fig. 8A to 8C respectively show three kinds of structural schematic diagrams of an inverter according to a third embodiment of the present invention;

FIG. 9 is a schematic diagram of a control circuit according to a fourth embodiment of the present invention;

fig. 10 illustrates a schematic configuration diagram of the first setup unit in fig. 9;

fig. 11 shows a schematic configuration diagram of another control circuit according to a fifth embodiment of the present invention.

Detailed Description

The invention will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. Moreover, certain well-known elements may not be shown in the figures.

In the following description, numerous specific details of the invention, such as structure, materials, dimensions, processing techniques and techniques of components, are set forth in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present invention may be practiced without these specific details.

It should be understood that in the following description, a "circuit" refers to a conductive loop formed by at least one element or sub-circuit through an electrical or electromagnetic connection. When an element or circuit is referred to as being "connected to" another element or element/circuit is referred to as being "connected between" two nodes, it may be directly coupled or connected to the other element or intervening elements may be present, and the connection between the elements may be physical, logical, or a combination thereof. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, it is intended that there are no intervening elements present.

Fig. 1 shows a schematic diagram of a motor controlled by an inverter. As shown in fig. 1, the inverter 100 is, for example, a three-phase inverter, and includes a first phase arm a, a second phase arm B, and a third phase arm C, where each phase arm is formed by connecting two power switching tubes (e.g., power switching tubes SW1-SW6) in series. Inverter 100 for converting dc power source V_DCThe supplied direct current is converted into three-phase alternating current, and modulated waves are output by controlling the on and off of the power switching tubes SW1-SW6, so that the purpose of driving the three-phase alternating current motor 200 is achieved.

Further, the inverter 100 controls the on and off of the power switching tubes on the three-phase bridge arm by using a control method such as SPWM (Sinusoidal Pulse Width Modulation), SVPWM (Space Vector Pulse Width Modulation), and DPWM (Discontinuous Pulse Width Modulation) to convert the direct current into the alternating current.

It should be appreciated that the power switches SW1-SW6 in inverter 100 are turned on in a complementary symmetrical manner, i.e., only one and only one power switch in the upper and lower legs of each phase of inverter 100 is in a conducting state at the same time, and the PWMPWM control signals provided to the upper and lower legs of the same phase have a complementary relationship. In the control process of the inverter 100, the power switching tube of the upper bridge arm of each phase is turned on, and the off state of the power switching tube of the lower bridge arm is represented by "1"; the power switch tube of the upper bridge arm of each phase is turned off, and the state that the power switch tube of the lower bridge arm is turned on is represented by "0". There are a total of eight switching states in inverter 100 as shown in table 1 below. Comprising six basic voltage vectors U₄、U₆、U₂、U₃、U₁And U₅And two zero voltage vectors U₀And U₇。

TABLE 1 space vector pulse width modulation algorithm voltage vector table

FIG. 2 shows a vector diagram of a control scheme of a space vector pulse width modulation algorithm, as shown in FIG. 2, with six basic voltage vectors U₄、U₆、U₂、U₃、U₁And U₅Are put together to form a radial pattern. Further, six basic voltage vectors U can be used₄、U₆、U₂、U₃、U₁And U₅Are connected together to form a regular hexagon. These six basic voltage vectors U₄、U₆、U₂、U₃、U₁And U₅Is 2Udc/3, Udc being the dc bus voltage in fig. 1. The six basic voltage vectors divide the regular hexagon into six sectors, each 60 °.

Further, the space vector pulse width modulation algorithm mainly uses the principle of average value equivalence, that is, the average value of basic voltage vectors is equal to the expected output voltage by combining the basic voltage vectors in one switching period. At a certain moment in time, the desired output voltage is rotated to a certain sector in the vector diagram, and the desired output voltage can be obtained by different combinations in time of two adjacent basic voltage vectors and a zero voltage vector which constitute the sector:

Uref×T_s＝U_X×T_X+U_Y×T_Y+U₀×T₀

where Uref is the desired output voltage, T_sFor the control period of the PWM control signal, T_X、T_YAnd T₀Corresponding to two basic voltage vectors U respectively_X、U_Y(wherein, (X, Y) ═ 4,6), (6,2), (2,3), (3,1), (1,5), or (5,4)) and a zero-voltage vector U₀The active time in one PWM control period.

Therefore, the above voltage vector synthesis technique can be used to set the voltage vector from U on the voltage space vector₄(100) Starting from the position, adding a small increment each time, each small increment setting voltage vector can be synthesized by two adjacent basic voltage vectors and a zero voltage vector in the sector, so that the obtained setting voltage vector is equivalent to a voltage space vector which smoothly rotates on a voltage space vector plane, and the aim of a space vector pulse width modulation algorithm is fulfilled.

When a three-phase inverter is used to control a three-phase ac motor, it is necessary to acquire three-phase currents of the three-phase ac motor for closed-loop control. The existing control method of the three-phase inverter has the technical problems of high cost, large occupied resource, insufficient effective vector action time at ultralow modulation ratio, noise introduced by phase shift and the like. Therefore, it is desirable to improve the sampling unit and the sampling method of the existing three-phase inverter to provide a low-cost control method, which can perform sampling reconstruction of the phase current within the full modulation ratio range of the three-phase inverter to obtain the three-phase current.

Based on this, an embodiment of the present invention provides a control method for an inverter, including: selecting one of the first mode and the second mode according to the determination condition; in a first mode, phase currents of any two phases of the inverter are sampled and reconstructed to obtain three-phase currents; in a second mode, the DC bus current is sampled and reconstructed to obtain three phase current. The decision condition is for example a comparison of the modulation factor of the inverter modulation algorithm with the magnitude of the modulation demarcation value or a comparison of the duration value of the actual samplable window within each PWM control period with the magnitude of the desired minimum sampling time value.

Fig. 3 shows a flow chart of a control method of an inverter according to a first embodiment of the present invention. The inverter of this embodiment is implemented by, for example, the inverter 100 shown in fig. 1, and includes a dc bus, and a first phase bridge arm a, a second phase bridge arm B, and a third phase bridge arm C connected in parallel between a positive end and a negative end of a dc power supply, where the bridge arm of each phase is formed by two power switching tubes connected in series (for example, power switching tubes SW1-SW6), and the power switching tubes SW1-SW6 are selected from IGBTs (Insulated Gate Bipolar transistors) or MOSFETs (Metal-Oxide-Semiconductor Field-Effect transistors, for example). The power switching tubes of the upper or lower leg of each phase are turned on and off based on a space vector pulse width modulation algorithm. As shown in fig. 3, the control method of the present embodiment includes steps S101 to S104.

In step S101, a modulation limit value is set.

In step S102, it is determined whether the modulation factor of the space vector pulse width modulation algorithm is greater than the modulation threshold. Continuing to step S103 when the modulation factor is less than or equal to the modulation boundary value; in the case where the modulation factor is larger than the modulation limit value, the step S104 is continued.

In step S103, phase currents of any two phases of the inverter are sampled and reconstructed to obtain three-phase currents.

In step S104, the dc bus current is sampled and reconstructed to obtain three-phase currents.

Specifically, the modulation boundary value divides the current sampling process of the present embodiment into a first stage and a second stage within the full modulation ratio range. The method comprises the steps of respectively sampling and reconstructing current of lower bridge arms of any two phases in a three-phase inverter in a first stage to obtain first-third phase currents, and sampling and reconstructing direct-current bus current in a second stage to obtain the first-third phase currents.

Further, the step of setting the modulation boundary value of this embodiment includes: obtaining two adjacent basic voltage vectors of the expected output voltage in a vector diagram of a space vector pulse width modulation algorithm, then obtaining action time of the two basic voltage vectors in a PWM control period, respectively recording the action time as a first action time and a second action time, obtaining a third action time of a zero voltage vector in the PWM control period according to the first action time and the second action time, and finally obtaining the modulation boundary value according to sampling control time and the third action time required by sampling.

Further, sampling phase currents of any two phases of the inverter in the first stage needs to be performed within a third action time of the zero voltage vector, so that the modulation boundary value needs to meet the requirement that the third action time of the zero voltage vector is longer than the sampling control time.

It should be understood that the operation principle of the space vector pulse width modulation algorithm is described in the above embodiments and known to those skilled in the art, and will not be described herein.

FIG. 4 shows a schematic diagram of the synthesis of the desired output voltage in a sector in a space vector pulse width modulation algorithm; as shown in FIG. 4, in a two-phase stationary reference frame, let the desired output voltage Uref and the basic voltage vector U_XThe included angle between is theta_XThe action time of the basic voltage vector adjacent to the expected output voltage Uref in one PWM control period, which can be obtained by the sine theorem, is respectively:

T_X＝mT_s sin(60°-θ_X)

T_Y＝mT_s sinθ_X

wherein, T_XAnd T_YCorresponding to two basic voltage vectors U respectively_XAnd U_Y(X, Y) ═ 4,6, (6,2), (2,3), (3,1), (1,5) orThe first action time and the second action time of the PWM control period, m is the modulation coefficient of the space vector pulse width modulation algorithm, and theta is_XFor a desired output voltage Uref and a basic voltage vector U_XAnd 0 is not more than theta_X＜60°。

Further, the modulation coefficient of the space vector pulse width modulation algorithm is as follows:

where | Uref | is the absolute value of the desired output voltage, U_dcIs the dc bus voltage.

Further, in order to reduce the switching times, the space vector pulse width modulation algorithm of the present embodiment sets the action sequence of the basic voltage vector as: and when the switching state is switched every time, the switching state of one phase is only changed, and the zero voltage vector is evenly distributed in time, so that the generated PWM control signals are symmetrical, and the harmonic component of the three-phase inverter can be effectively reduced. Based on the control principle, the space vector pulse width modulation algorithm is divided into seven-segment output and five-segment output.

When the space vector pulse width modulation algorithm is seven-segment output, the third action time of the zero voltage vector in the PWM control period is as follows:

T₀＝(T_s-T_X-T_Y)/2

or, when the space vector pulse width modulation algorithm is a five-segment output, the third acting time of the zero voltage vector in the PWM control period is:

T₀＝T_s-T_X-T_Y

when the space vector pulse width modulation algorithm is seven-segment output, the modulation boundary value meets the following conditions:

T₀＝(T_s-T_X-T_Y)/2>T_set

wherein, T_sFor said PWM control period, T_X、T_YAnd T₀Corresponding to two basic voltage vectors U respectively_X、U_Y((X, Y) ═ 4,6), (6,2), (2,3), (3,1), (1,5), or (5,4)) and zero voltage vector U₀First, second and third active times, T, in a PWM control period_setThe time is controlled for the sampling.

Combining the above formula can obtain:

wherein M is a third action time T satisfying a zero voltage vector₀Greater than the sampling control time T_setAt theta, of all modulation coefficients_XTaking the minimum value at 30 °, i.e. the modulation limit value M_minComprises the following steps:

when the space vector pulse width modulation algorithm is output in a five-segment mode, the modulation boundary value meets the following conditions:

T₀＝T_s-T_X-T_Y>T_set

Combining the above formula can obtain:

wherein M is a third operation satisfying a zero voltage vectorTime of use T₀Greater than the sampling control time T_setAt theta, of all modulation coefficients_XTaking the minimum value at 30 °, i.e. the modulation limit value M_minComprises the following steps:

further, the control method of this embodiment further includes: calculating the sampling control time Tset according to the following formula:

T_set＝T_dead+T_on-T_off+T_ring+T_adsmp+T_wait

wherein, T_setControlling the time for said sampling, T_deadFor dead time of PWM control signal, T_onIs the delayed conduction time, T, of the lower bridge arm power switching tube of the inverter_offIs the delayed turn-off time, T, of the lower bridge arm power switching tube of the inverter_ringSampling the current of the inverter with a signal oscillation time, T_adsmpSample and hold time, T, for a sample reconstruction module of the inverter_waitA sample start delay time for a sample reconstruction module of the inverter.

Fig. 5 shows a flow chart of a control method of an inverter according to a second embodiment of the present invention. As shown in fig. 5, the control method includes steps S201 to S206.

In step S201, a desired minimum sampling time value is set.

In step S202, the duration value of the actual samplable window within each PWM control period is calculated.

In step S203, it is determined whether the duration value is less than a desired minimum sampling time value within each PWM control period. If the duration value is less than the desired minimum sample time value, continue with step S204; in case the duration value is greater than/equal to the desired minimum sample time value, step S205 is continued.

In step S204, the dc bus current is sampled and reconstructed to obtain three-phase currents. Further, the method also comprises the step of sampling the peak current of the direct current bus.

In step S205, it is determined whether the duration values in consecutive PWM control periods adjacent to the current PWM control period are each greater than/equal to the desired minimum sampling time value. If the duration values in a plurality of consecutive PWM control periods adjacent to the current PWM control period are all greater than/equal to the expected minimum sampling time value, continuing to step S206; otherwise, the process returns to step S204.

In step S206, phase currents of any two phases of the inverter are sampled and reconstructed to obtain three-phase currents.

Specifically, the control method of this embodiment implements switching of the sampling mode by comparing the duration value of the actual sampling window in each PWM control period with the expected minimum sampling time value, and performs peak current sampling and reconstruction on the dc bus of the inverter to obtain the three-phase current when the duration value of the actual sampling window in the current PWM control period is smaller than the expected minimum sampling time value. And in the case that the duration values of the actual sampling windows in all PWM control periods in one current fundamental wave period are larger than/equal to the expected minimum sampling time value, sampling and reconstructing the phase currents of any two phases of the inverter to obtain three-phase currents. Wherein the plurality of successive PWM control periods includes at least one current fundamental period.

Fig. 7A to 7C respectively show waveforms of PWM modulated waves obtained based on the SPWM, SVPWM, and DPWM modulation methods. In fig. 7A to 7C, the abscissa indicates the position of the fundamental wave voltage, the ordinate indicates the on-time of the upper arm of the multi-phase arm in the inverter, and A, B, C indicates the first phase arm, the second phase arm, and the third phase arm of the inverter, respectively. In addition, each current fundamental wave period includes a plurality of PWM control periods, the length of one current fundamental wave period is 2 pi, and since PWM modulation waveforms of different modulation schemes are different, it is necessary to determine the duration value of the actual samplable window of at least one current fundamental wave period.

Further, in step S201, it is required to obtain the current sampling signal oscillation time of the lower bridge arm of any two phase bridge arms of the inverter at the conduction instant in advance, obtain the sample hold time and the start sampling delay time of the sampling module of the inverter, and calculate the expected minimum sampling time value according to the current sampling signal oscillation time, the sample hold time and the start sampling delay time. For example, the expected minimum sampling time value may be calculated according to the following formula:

T_E＝T_ring+T_adsmp+T_wait

Further, in step S202, it is required to obtain the delay on-time, the delay off-time, and the dead time of the lower arm power switching tube of the inverter, obtain a time window in which sampling can be performed in each PWM control period, and calculate a duration value of the actual sampling window in each PWM control period according to the delay on-time, the delay off-time, the dead time, and the time window in which sampling can be performed. For example, the duration value may be calculated according to the following formula:

T_R＝T_G-T_dead-T_on+T_off

wherein, T_RRepresenting said value of duration, T_GRepresenting said time window in which sampling can be performed, T_deadRepresenting said dead time, T_onRepresenting said delayed on-time, T_offRepresenting the delayed turn-off time. Further, the time window over which sampling can be performed can be calculated according to the following formula:

T_G＝T_s-max(T_a,T_b,T_c)

wherein, T_sIndicating the PWM control period, T, of the PWM control signal_a、T_b、T_cRespectively representing the conduction time, max (T), of the upper bridge arm of the three-phase bridge arm of the inverter in each PWM control period_a,T_b,T_c) And the maximum value of the conduction time of the upper bridge arm of the three-phase bridge arm of the inverter in each PWM control period is represented.

Fig. 6 is a schematic diagram showing waveforms of three-phase PWM control signals in one PWM control period according to an embodiment of the present invention. In fig. 6, control signals PWMA to PWMC control the on and off of the upper arm power switching tubes of the first, second and third phase arms a, B and C, respectively, and T controls the inverter 100 in fig. 1_a、T_bAnd T_cRespectively showing the high level time of the control signals PWMA-PWMC, namely the conduction time of the upper bridge arm power switching tubes of the first phase bridge arm A, the second phase bridge arm B and the third phase bridge arm C, and T_a>T_b>T_c，T_sIndicating the PWM control period of the PWM control signal. Further, the control signal PWMA, the control signal PWMB, and the control signal PWMC are divided into a maximum phase control signal, an intermediate phase control signal, and a minimum phase control signal according to a high level time of the PWM control signal, and max (T)_a,T_b,T_c) Indicating the high time of the maximum phase control signal, i.e. the active time T of the control signal PWMA_aFrom this, the time window in which sampling can be performed in the above equation is obtained as follows:

T_G＝T_s-T_a

the control method of the embodiment is based on the high level time T of the PWM control signal of the three-phase upper bridge arm power switching tube_a、T_bAnd T_cThe maximum value in the method is calculated to obtain the duration value of the actual sampling window in each PWM control period, then the duration value is compared with the expected minimum sampling time value, and the sampling mode is switched according to the comparison result, so that the control method of the embodiment does not specify a specific voltage modulation algorithm and can be applied to general voltage modulation algorithms such as SVPWM, SPWM and DPWM.

With further continued reference to fig. 6, the control methods of both the first and second embodiments of the present invention further include: in one PWM control period, the control signal PWMA, the control signal PWMB, and the control signal PWMC are divided into a maximum phase control signal (i.e., the control signal PWMA), a middle phase control signal (i.e., the control signal PWMB), and a minimum phase control signal (i.e., the control signal PWMC) according to the on-time of the upper arm power switching transistor of each phase of the inverter, the current of the direct current bus is sampled at a first time interval between edges of the maximum phase control signal and the middle phase control signal (i.e., between an upper edge of the maximum phase control signal and an upper edge of the middle phase control signal, or between a lower edge of the maximum phase control signal and a lower edge of the middle phase control signal) to obtain a phase current of the phase corresponding to the maximum phase control signal, the current of the direct current bus is sampled at a first time interval between edges of the maximum phase control signal and the middle phase control signal (i.e., the upper edge of the minimum phase control signal and the upper edge of the intermediate phase control signal, or the lower edge of the minimum phase control signal and the lower edge of the intermediate phase control signal) to obtain the phase current of the phase corresponding to the minimum phase control signal, wherein the phase current of the phase corresponding to the minimum phase control signal is the opposite number of the sampled phase current, and finally, the phase current of the phase corresponding to the intermediate phase control signal is calculated according to the known phase currents of the two phases. Further, the phase current of the phase corresponding to the middle phase control signal is equal to the opposite number of the sum of the phase current of the phase corresponding to the maximum phase control signal and the phase current of the phase corresponding to the minimum phase control signal.

Fig. 8A to 8C respectively show three kinds of structural schematic diagrams of an inverter according to a third embodiment of the present invention. As shown in fig. 8A to 8C, the motor system includes an inverter 100, a motor 200, a control circuit 300, and a first sampling unit 110 and a plurality of second sampling units 120 provided in the inverter 100.

Inverter 100 is used to drive motor 200. The inverter 100 is implemented, for example, by a three-phase inverter, and includes a first phase arm a, a second phase arm B, and a third phase arm C, where each phase arm is formed by connecting two power switching tubes in series (e.g., power switching tubes)SW1-SW6), the power switch transistors SW1-SW6 are selected from IGBTs (Insulated Gate Bipolar Transistor) or MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistor), for example. Inverter 100 for converting dc power source V_DCThe supplied direct current is converted into alternating current, and modulated waves are output by controlling the on and off of the power switching tubes SW1-SW6, so that the purpose of driving the electrodes 200 is achieved.

Further, the inverter 100 controls the power switching tubes of the three-phase bridge arm to be turned on and off by a control method such as SVPWM, SPWM, or DPWM, for example, so as to convert the direct current into the alternating current.

It should be understood that the power switches SW1-SW6 in the inverter 100 are turned on in a complementary symmetrical manner, i.e., only one and only one power switch in the upper and lower arms of each phase of the inverter 100 is in a conducting state at the same time, and the PWM driving signals provided to the upper and lower arms of the same phase have a complementary relationship. In the control process of the inverter 100, the power switching tube of the upper bridge arm of each phase is turned on, and the off state of the power switching tube of the lower bridge arm is represented by "1"; the power switch tube of the upper bridge arm of each phase is turned off, and the state that the power switch tube of the lower bridge arm is turned on is represented by "0". There are a total of eight switching states in inverter 100 as shown in table 1 above.

Specifically, the first sampling unit 110 is disposed on a dc bus of the inverter 100, and the two second sampling units 120 are respectively disposed on any two phase lines or any two phase arms of the phase line ends of the inverter 100. The control circuit 300 is configured to sample the dc bus current through the first sampling unit 110 to obtain a first phase current, a second phase current, and a third phase current, or sample the phase currents of any two phases of the inverter 100 through the plurality of second sampling units 120 to obtain the first phase current, the second phase current, and the third phase current.

As shown in fig. 8A, the second sampling unit 120 is a sampling resistor disposed on any two-phase bridge arm of the inverter 100, and the control circuit 300 obtains a current sampling signal of a phase current by sampling voltage signals at two ends of the sampling resistor connected in series to a lower bridge arm of any two-phase bridge arm, and obtains the phase current of a corresponding phase according to the current sampling signal.

As shown in fig. 8B, the second sampling unit 120 is a current sensor disposed on any two phase lines of the inverter 100, and the control circuit 300 obtains a current sampling signal of a phase current by sampling a current at any two phase line ends, and obtains a phase current of a corresponding phase according to the current sampling signal.

As shown in fig. 8C, the control circuit 300 may directly sample the voltage signal of the internal resistance of the power switch tube of the lower arm of any two-phase arm of the inverter 100 to obtain the phase currents of the two phases.

In addition, in an embodiment, the first sampling unit 110 is a sampling resistor, the first sampling unit 110 is connected in series to the dc bus loop, and the control circuit 300 obtains a current sampling signal by sampling a voltage signal across the sampling resistor of the dc bus and performs reconstruction to obtain a three-phase current. In another embodiment, a current sensor is connected in series with a dc bus of the inverter, and the phase current is obtained by sampling and reconstructing a peak current signal of the dc bus.

Fig. 9 shows a schematic diagram of a control circuit according to a fourth embodiment of the present invention. As shown in fig. 9, the control circuit 300 includes a selection module 310, a first sample reconstruction module 320, and a second sample reconstruction module 330. The first sampling reconstruction module 320 and the second sampling reconstruction module 330 each include an analog-to-digital converter, the first sampling reconstruction module 320 is configured to sample any two-phase current of the inverter 100 and reconstruct the two-phase current to obtain a three-phase current, the second sampling reconstruction module 330 is configured to sample a direct-current bus current of the inverter 100 and reconstruct the three-phase current, and the selection module 310 is configured to select to sample by using the first sampling reconstruction module 320 or select the second sampling reconstruction module 330 to sample according to the determination condition and the determination result.

Further, the selection module 310 includes a first setting unit 311-1 and a first comparing unit 312-1. The first setting unit 311-1 is configured to set a modulation boundary value, and the first comparing unit 312-1 is configured to compare a modulation coefficient of a space vector pulse width modulation algorithm with the modulation boundary value, and select one of the first sample reconstructing module 320 and the second sample reconstructing module 330 for sampling according to a comparison result. Wherein the first comparing unit 312-1 is configured to select the first sample reconstructing module 320 if the modulation factor is smaller than or equal to the modulation boundary value, and select the second sample reconstructing module 330 if the modulation factor is greater than the modulation boundary value.

Specifically, the modulation boundary value divides the sampling process of the control circuit 300 of the present embodiment into a first phase and a second phase within the full modulation ratio range. In the first stage, the first sampling reconstruction module 320 samples the current of any two phases of the phase current of the inverter 100 to obtain the first to third phase currents, and in the second stage, the second sampling reconstruction module 330 samples the dc bus current of the inverter 100 to obtain the first to third phase currents.

As shown in fig. 10, the first setting unit 311-1 includes a vector voltage calculation unit 3101, a first time calculation unit 3102, a second time calculation unit 3103, and an output unit 3104. The vector voltage calculation unit 3101 is used to obtain two adjacent basic voltage vectors U according to the desired output voltage Uref_XAnd U_Y. First time calculation unit 3102 is used to obtain a base voltage vector U_XAnd U_YIn a PWM control period T_sFirst action time T in_XAnd a second action time T_Y. The second time calculation unit 3103 is used for calculating the first action time T_XAnd a second action time T_YObtaining zero voltage vector in PWM control period T_sThird action time T in₀. The output unit 3104 is used for controlling the time T according to the sampling_setAnd a third application time T₀Obtaining the modulation boundary value M_min。

Further, the first sample reconstruction module 320 needs a third action time T at zero voltage vector₀Inner sampling, thus modulating the boundary value M_minNeed to meet so as to be zeroThird action time T of voltage vector₀Greater than the sampling control time T_set。

Further, the first time calculation unit 3102 obtains a basic voltage vector U adjacent to the desired output voltage Uref according to the following formula_XAnd U_YIn a PWM control period T_sThe action time in (1):

T_X＝mT_s sin(60°-θ_X)

T_Y＝mT_s sinθ_X

wherein, T_sFor PWM control period, T_XAnd T_YCorresponding to two basic voltage vectors U respectively_XAnd U_Y(X, Y) ═ 4,6, (6,2), (2,3), (3,1), (1,5), or (5,4)) at the first action time and the second action time of one PWM control period, m is the modulation coefficient of the space vector pulse width modulation algorithm, θ is_XFor a desired output voltage Uref and a basic voltage vector U_XAnd 0 is not more than theta_X＜60°。

where | Uref | is the absolute value of the desired output voltage, U_dcIs the voltage of the dc bus.

Further, when the space vector pulse width modulation algorithm is output in a seven-segment manner, the second time calculation unit 3103 obtains the zero voltage vector in the PWM control period T according to the following formula_sThird action time of (1):

T₀＝(T_s-T_X-T_Y)/2

alternatively, when the space vector pulse width modulation algorithm is a five-segment output, the second time calculation unit 3103 calculates the zero voltage vector in the PWM control period T according to the following formula_sThird action time of (1):

T₀＝T_s-T_X-T_Y

when the space vector pulse width modulation algorithm is seven-segment output, the modulation boundary value satisfies the following condition in six sectors of a vector diagram of the space vector pulse width modulation algorithm:

T₀＝(T_s-T_X-T_Y)/2>T_set

Combining the above formula can obtain:

when the space vector pulse width modulation algorithm is output in five segments, the modulation boundary value satisfies the following condition in six sectors of a vector diagram of the space vector pulse width modulation algorithm:

T₀＝T_s-T_X-T_Y>T_set

Combining the above formula can obtain:

further, the first setting unit 311-1 further includes a sampling control time calculation unit 3105, and the sampling control time calculation unit 3105 is configured to calculate the sampling control time T according to the following formula_setI.e. by

T_set＝T_dead+T_on-T_off+T_ring+T_adsmp+T_wait

Wherein, T_deadFor dead time of PWM control signal, T_onIs the delayed conduction time, T, of the lower bridge arm power switching tube of the inverter_offFor the delayed turn-off time, T, of the lower leg power switching tube of each phase of the inverter_ringFor the current sampling signal oscillation time, T, of the sampling reconstruction module of the inverter_adsmpSample and hold time, T, for a sample reconstruction module of the inverter_waitA sample start delay time for a sample reconstruction module of the inverter.

Fig. 11 shows a schematic configuration diagram of another control circuit according to a fifth embodiment of the present invention. As shown in fig. 11, the control circuit 300 includes a selection module 310, a first sample reconstruction module 320, and a second sample reconstruction module 330. The first sampling reconstruction module 320 and the second sampling reconstruction module 330 each include an analog-to-digital converter, the first sampling reconstruction module 320 is configured to sample any two-phase currents in the inverter 100 and reconstruct the two-phase currents to obtain three-phase currents, the second sampling reconstruction module 330 is configured to sample a direct-current bus current in the inverter 100 and reconstruct the direct-current bus current to obtain three-phase currents, and the selection module 310 is configured to select the first sampling reconstruction module 320 to sample or select the second sampling reconstruction module 330 to sample according to the determination condition and the determination result.

The control circuit of the present embodiment is different from the control circuit of the fourth embodiment in that the first sampling reconstruction module 320 of the present embodiment is configured to sample and reconstruct any two-phase current of the inverter to obtain a three-phase current if the duration values of the actual samplable windows in a plurality of consecutive PWM control periods are all greater than or equal to the expected minimum sampling time value, and the second sampling reconstruction module 330 is configured to sample and reconstruct the dc bus current to obtain a three-phase current if the duration values of the actual samplable windows in a plurality of consecutive PWM control periods are not greater than or equal to the expected minimum sampling time value.

Further, the selection module 310 includes a second setting unit 311-2, a sampling time obtaining unit 312-2, a first judging unit 313-2, and a second judging unit 314-2. The second setting unit 311-2 is used to set a desired minimum sampling time value. Illustratively, the second setting unit 311-2 sets the desired minimum sampling time value according to the following formula:

T_E＝T_ring+T_adsmp+T_wait

The sampling time acquisition unit 312-2 is used to obtain the duration value of the actual samplable window in each PWM control period. The multi-phase bridge arms of the inverter 100 are connected in parallel between the positive end and the negative end of the dc power supply, and the upper bridge arm and the lower bridge arm of each phase bridge arm are respectively provided with a power switching tube, and the power switching tubes on the lower bridge arm of the phase sampled in the actual sampling window of the phase end are in a conducting state under the action of a PWM control signal. The sampling time obtaining unit 312-2 calculates a duration value of the actual samplable window in each PWM control period according to the following formula:

T_R＝T_G-T_dead-T_on+T_off

wherein, T_RA value representing the duration of said actual sampleable window, T_GRepresenting said time window in which sampling can be performed, T_deadRepresents the dead time T of the lower bridge arm power switching tube of the inverter in the PWM control period_onRepresenting the delay conduction time T of the lower bridge arm power switching tube of the inverter in the PWM control period_offAnd representing the delayed turn-off time of the lower bridge arm power switching tube of the inverter in a PWM control period. Further, the sampling time obtaining unit 312-2 further calculates a time window that can be sampled in each PWM control period according to the following formula:

T_G＝T_s-max(T_a,T_b,T_c)

wherein, T_sIndicating the PWM control period, T, of the PWM control signal_a、T_b、T_cRespectively representing the conduction time, max (T), of the upper bridge arm of each phase of the inverter in each PWM control period_a,T_b,T_c) And the maximum value of the conduction time of the upper bridge arm of the three-phase bridge arm of the inverter in each PWM control period is represented.

The first determining unit 313-2 and the second determining unit 314-2 are configured to determine whether the obtained duration value of the actual sampling window satisfies a preset condition, and start the first sampling reconstruction module 320 or the second sampling reconstruction module 330 according to the determination result.

Specifically, the first determining unit 313-2 is configured to determine whether the duration value is smaller than the expected minimum sampling time value in each PWM control period, and control the second sampling reconfiguration module 330 to sample the dc bus current and reconfigure the dc bus current to obtain the three-phase current when the duration value is smaller than the expected minimum sampling time value. The second determining unit 314-2 is configured to determine, when the duration value is greater than or equal to the expected minimum sampling time value, whether the duration values in consecutive PWM control periods adjacent to the current PWM control period are all greater than or equal to the expected minimum sampling time value, and control the first sampling reconstruction module 320 to sample and reconstruct phase currents of any two phases in the inverter to obtain three-phase currents when the duration values in consecutive PWM control periods adjacent to the current PWM control period are all greater than or equal to the expected minimum sampling time value, otherwise control the second sampling reconstruction module 330 to sample and reconstruct direct-current bus currents of the inverter to obtain three-phase currents.

Further, the first sampling reconstruction module 320 in the fourth and fifth embodiments of the present invention is configured to sample phase currents of any two phases of the inverter during the first phase, and calculate a phase current of a third phase according to the sampled phase currents.

Specifically, taking a three-phase inverter as an example, the phase current of the third phase is equal to the opposite of the sum of the phase currents of the two phases that have been obtained.

Further, the second sampling reconstruction module 330 is configured to sample and reconstruct the dc bus current of the inverter according to the time interval between the maximum phase control signal, the middle phase control signal and the minimum phase control signal edge in the second phase to obtain the phase current of each phase of the inverter.

Specifically, the second sampling reconstruction module 330 samples the current of the direct current bus at a first time interval between waveform edges of the maximum phase control signal and the intermediate phase control signal, a value output by the analog-to-digital converter in the second sampling reconstruction module 330 is the phase current of the phase corresponding to the maximum phase control signal, the current of the direct current bus is sampled at a second time interval between the waveform edges of the minimum phase control signal and the intermediate phase control signal, the opposite number of the values output by the analog-to-digital converter in the second sampling reconstruction module 330 is the phase current of the phase corresponding to the minimum phase control signal, and finally, the phase current of the phase corresponding to the intermediate phase control signal is calculated according to the phase currents of the two phases. For example, the phase current of the phase corresponding to the middle phase control signal is equal to the opposite number of the sum of the phase current of the phase corresponding to the maximum phase control signal and the phase current of the phase corresponding to the minimum phase control signal.

It should be understood that the control method and control circuit of embodiments of the present invention are applicable not only to current sampling of three-phase inverters, but also to current sampling of multiphase inverters. Therefore, modifications of the multiphase inverter based on the technical idea of the present invention also fall into the protection scope of the present invention.

In summary, the control method and the control circuit of the inverter according to the embodiments of the present invention divide the current sampling process into the first stage and the second stage, sample and reconstruct the phase currents of any two phases of the inverter in the first stage to obtain the three-phase currents of the inverter, and sample and reconstruct the dc bus of the inverter in the second stage to obtain the three-phase currents of the inverter, which does not need to specially avoid the high modulation region and the low modulation region of the three-phase inverter, has a wide current sampling reconstruction region, is simple to implement, does not need to shift phases, and is beneficial to implementing current sampling in the full modulation ratio range of the three-phase inverter.

In addition, the control method and the control circuit do not need to use expensive current sensors, the number of channels of the sampling module can be simplified, and the sampling cost of the three-phase inverter is reduced. The control mode has simple operation, can be realized without adopting an expensive control chip, and is beneficial to further reducing the production cost.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A control method of an inverter, characterized by comprising:

in a first mode, the phase currents of any two phases of the inverter are directly sampled and reconstructed to obtain three-phase currents;

2. The control method according to claim 1, wherein the selecting one of the first mode and the second mode according to the determination condition includes:

setting a modulation boundary value;

3. The control method according to claim 2, wherein the setting the modulation limit value includes:

4. The control method according to claim 3, characterized in that the first action time and the second action time are obtained according to the following formulas:

T_X＝mT_ssin(60°-θ_X)

T_Y＝mT_ssinθ_X

wherein, T_sFor PWM control period, T_XAnd T_YRespectively correspond to the phasesTwo adjacent basic voltage vectors U_XAnd U_YWherein X and Y represent the numbers of basic voltage vectors and (X, Y) ═ 4,6), (6,2), (2,3), (3,1), (1,5), or (5,4), respectively, at a first action time and a second action time of one PWM control period, m is a modulation coefficient of the space vector pulse width modulation algorithm, θ_XFor a desired output voltage Uref and a basic voltage vector U_XAnd 0 is not more than theta_X＜60°。

5. The control method according to claim 4, wherein the modulation factor is obtained according to the following formula:

6. The control method according to claim 3, wherein the modulation boundary value satisfies the following condition: such that the third action time is greater than the sampling control time.

7. The control method of claim 6, wherein the space vector pulse width modulation algorithm comprises a seven segment output and a five segment output.

8. The control method according to claim 7, wherein when the space vector pulse width modulation algorithm is a seven-segment output, the third action time is obtained according to the following formula:

T₀＝(T_s-T_X-T_Y)/2

wherein, T_XAnd T_YRespectively corresponding to two adjacent basic voltage vectors U_XAnd U_Y(X, Y) ═ 4,6, (6,2), (2,3), (3,1), (1,5), or (5,4)) at the first of the PWM control periodWith time and a second action time, T_sIs the PWM control period.

9. The control method of claim 8, wherein the modulation boundary value is obtained according to the following formula:

M_min＝1-2T_set/T_s

10. The control method according to claim 7, wherein when the space vector pulse width modulation algorithm is a five-segment output, the third action time is obtained according to the following formula:

T₀＝T_s-T_X-T_Y

11. The control method of claim 10, wherein the modulation boundary value is obtained according to the following formula:

M_min＝1-T_set/T_s

12. The control method according to claim 3, wherein the inverter includes multi-phase bridge arms connected in parallel between a positive end and a negative end of the dc power supply, each phase bridge arm includes power switching tubes respectively disposed in an upper bridge arm and a lower bridge arm of each phase bridge arm, and the power switching tubes of the lower bridge arm of the phase sampled within an actual sampling window at the phase end are in a conducting state under the action of the PWM control signal, wherein the setting of the modulation boundary value further includes:

13. The control method of claim 12, wherein the sampling control time is obtained according to the following formula:

T_set＝T_dead+T_on-T_off+T_ring+T_adsmp+T_wait

wherein, T_setControlling the time for said sampling, T_deadIs the dead time, T, of the PWM control signal_onIs the delayed conduction time, T, of the lower bridge arm power switching tube of the inverter_offIs the delayed turn-off time, T, of the lower bridge arm power switching tube of the inverter_ringSampling the oscillation time of the signal for the current at the phase line end of the inverter, T_adsmpSample and hold time, T, for a sample reconstruction module of the inverter_waitA sample start delay time for a sample reconstruction module of the inverter.

14. The control method according to claim 1, wherein the selecting one of the first mode and the second mode according to the determination condition includes:

setting a desired minimum sample time value;

15. The control method according to claim 14, wherein the selecting one of the first mode and the second mode according to the determination condition further comprises:

16. The control method of claim 14, wherein the consecutive plurality of PWM control periods comprises all PWM control periods of at least one current fundamental period.

17. The control method of claim 14, wherein the desired minimum sample time value is set according to the following formula:

T_E＝T_ring+T_adsmp+T_wait

18. The control method according to claim 14, wherein the inverter includes multi-phase bridge arms connected in parallel between a positive end and a negative end of the dc power supply, each phase bridge arm includes power switching transistors respectively disposed in an upper bridge arm and a lower bridge arm of each phase bridge arm, and the power switching transistor of the lower bridge arm of the phase sampled in an actual sampling window at the phase end is in a conducting state under the action of the PWM control signal, wherein obtaining the duration value of the actual sampling window in each PWM control period includes:

obtaining a time window which can be sampled in each PWM control period; and

19. The control method of claim 18, wherein the actual value of the duration of the sampleable window in each PWM control period is calculated according to the following equation:

T_R＝T_G-T_dead-T_on+T_off

20. The control method according to claim 19, characterized by further comprising: the time window in which sampling can be performed is calculated according to the following formula:

T_G＝T_s-max(T_a,T_b,T_c)

21. The control method according to claim 18, characterized by further comprising: modulating a desired output voltage based on a voltage modulation algorithm to obtain the PWM control signal, the voltage modulation algorithm comprising SPWM, SVPWM, or DPWM.

22. The control method of claim 1, wherein in the second mode, sampling the dc bus current and reconstructing the dc bus current to obtain three-phase currents comprises: in a second mode, a peak current of the dc bus is sampled.

23. The control method of claim 1, wherein in the second mode, sampling the dc bus current and reconstructing the dc bus current to obtain three-phase currents comprises:

24. A control circuit for an inverter, comprising:

the first sampling reconstruction module is used for directly sampling any two phases of phase currents of the inverter and reconstructing the phase currents to obtain three-phase currents;

25. The control circuit of claim 24, wherein the selection module comprises:

a first setting unit for setting a modulation boundary value;

26. The control circuit according to claim 25, wherein the first setting unit includes:

27. The control circuit of claim 26, wherein the first time calculation unit obtains the first action time and the second action time according to the following equations:

T_X＝mT_ssin(60°-θ_X)

T_Y＝mT_ssinθ_X

wherein, T_sFor PWM control period, T_XAnd T_YRespectively corresponding to two adjacent basic voltage vectors U_XAnd U_YWherein X and Y represent the numbers of basic voltage vectors and (X, Y) ═ 4,6), (6,2), (2,3), (3,1), (1,5), or (5,4), respectively, at a first action time and a second action time of one PWM control period, m is a modulation coefficient of the space vector pulse width modulation algorithm, θ_XFor a desired output voltage Uref and a basic voltage vector U_XAnd 0 is not more than theta_X＜60°。

28. The control circuit of claim 26, wherein the output unit obtains the modulation factor according to the following equation:

29. The control circuit of claim 26, wherein the modulation boundary value satisfies the following condition: such that the third action time is greater than the sampling control time.

30. The control circuit of claim 26 wherein the space vector pulse width modulation algorithm comprises a seven segment output and a five segment output.

31. The control circuit of claim 30, wherein when the space vector pulse width modulation algorithm is a seven-segment output, the second time calculation unit obtains the third action time according to the following equation:

T₀＝(T_s-T_X-T_Y)/2

32. The control circuit of claim 31, wherein the output unit derives the modulation boundary value according to the following equation:

M_min＝1-2T_set/T_s

33. The control circuit of claim 30, wherein when the space vector pulse width modulation algorithm is a five-segment output, the second time calculation unit obtains the third action time according to the following formula:

T₀＝T_s-T_X-T_Y

wherein, T_XAnd T_YRespectively correspond toTwo adjacent basic voltage vectors U_XAnd U_Y(X, Y) ═ 4,6, (6,2), (2,3), (3,1), (1,5), or (5,4)) at the first and second active times, T, of the PWM control period_sIs the PWM control period.

34. The control circuit of claim 33, wherein the output unit derives the modulation boundary value according to the following equation:

M_min＝1-T_set/T_s

35. The control circuit of claim 26, wherein the first setting unit further comprises a sampling control time calculation unit, and the sampling control time calculation unit obtains the sampling control time according to the following formula:

T_set＝T_dead+T_on-T_off+T_ring+T_adsmp+T_wait

wherein, T_setControlling the time for said sampling, T_deadFor dead time of PWM control signal, T_onIs the delayed conduction time, T, of the lower bridge arm power switching tube of the inverter_offIs the delayed turn-off time, T, of the lower bridge arm power switching tube of the inverter_ringFor the current sampling signal oscillation time, T, of the sampling reconstruction module of the inverter_adsmpSample and hold time, T, for a sample reconstruction module of the inverter_waitA sample start delay time for a sample reconstruction module of the inverter.

36. The control circuit of claim 24, wherein the first sampling reconstruction module is configured to sample phase currents of any two phases in the inverter and reconstruct the phase currents of the three phases if a duration value satisfying an actual sampleable window in a plurality of consecutive PWM control periods is greater than or equal to a desired minimum sampling time value,

37. The control circuit of claim 36, wherein the selection module comprises:

a second setting unit for setting a desired minimum sampling time value;

38. The control circuit of claim 36 wherein the consecutive plurality of PWM control periods comprises all of the at least one current fundamental period.

39. The control circuit of claim 37, wherein the second setting unit sets the desired minimum sample time value according to the following formula:

T_E＝T_ring+T_adsmp+T_wait

40. The control circuit of claim 37, wherein the sampling time obtaining unit calculates the duration value of the actual samplable window in each PWM control period according to the following formula:

T_R＝T_G-T_dead-T_on+T_off

wherein, T_RRepresenting said value of duration, T_GRepresenting a time window in which sampling can be performed, T_deadRepresenting the dead time, T, of the PWM control signal_onRepresenting the delay conduction time T of the lower bridge arm power switching tube of the inverter in the PWM control period_offAnd representing the delayed turn-off time of a lower bridge arm power switching tube of the inverter in the PWM control period.

41. The control circuit of claim 40, wherein the sampling time obtaining unit calculates the time window in which sampling can be performed according to the following formula:

T_G＝T_s-max(T_a,T_b,T_c)

wherein, T_sRepresenting the PWM control period, T_a、T_b、T_cEach PW is respectively expressedThe conduction time, max (T), of the power switch tube of the upper bridge arm of the three-phase bridge arm of the inverter in the M control period_a,T_b,T_c) And the maximum value of the conduction time of the power switching tubes of the upper bridge arm of the three-phase bridge arm of the inverter in each PWM control period is represented.

42. The control circuit of claim 40 wherein the control circuit is further configured to modulate a desired output voltage based on a voltage modulation algorithm to obtain the PWM control signal, the voltage modulation algorithm comprising SPWM, SVPWM, or DPWM.

43. The control circuit of claim 24, wherein the second sampling reconstruction module is configured to sample a peak current of a dc bus in the inverter and reconstruct a three-phase current.

44. The control circuit of claim 24, wherein in each PWM control period, the PWM control signals of the upper arm power switching tubes are divided into a maximum phase control signal, a middle phase control signal, and a minimum phase control signal according to the on-time of the upper arm of the inverter,

45. The control circuit of claim 24, further comprising:

the first sampling unit is arranged on a direct-current bus of the inverter, and the second sampling reconstruction module is suitable for sampling through the first sampling unit to obtain direct-current bus current.

46. The control circuit of claim 45, wherein the first sampling unit is selected from a sampling resistor or a current sensor.

47. The control circuit of claim 24, further comprising:

the first sampling reconstruction module samples the current of the corresponding phase through the plurality of second sampling units to obtain the phase current.

48. The control circuit according to claim 47, wherein each of the second sampling units comprises a sampling resistor disposed on a bridge arm of the inverter, and the first sampling reconstruction module is adapted to sample a voltage signal across the sampling resistor to obtain a current sampling signal of a phase current, and obtain the phase current of a corresponding phase according to the current sampling signal.

49. The control circuit according to claim 47, wherein each of the second sampling units comprises a current sensor disposed on a phase line of the inverter, and the first sampling reconstruction module performs sampling by the current sensor to obtain a current sampling signal of a phase current, and obtains the phase current of the corresponding phase according to the current sampling signal.

50. The control circuit of claim 24, wherein the first sampling reconstruction module is adapted to sample a voltage signal across a power switch tube resistor of a lower leg of any two-phase leg of the inverter to obtain a phase current of a corresponding phase.