CN112435697A - High-reliability nonvolatile memory and memory cell array thereof - Google Patents
High-reliability nonvolatile memory and memory cell array thereof Download PDFInfo
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- CN112435697A CN112435697A CN202011593924.9A CN202011593924A CN112435697A CN 112435697 A CN112435697 A CN 112435697A CN 202011593924 A CN202011593924 A CN 202011593924A CN 112435697 A CN112435697 A CN 112435697A
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Abstract
The invention discloses a high-reliability nonvolatile memory and a memory cell array thereof, wherein each bit line is connected with only one memory cell on the bit line, which may waste most of the memory space in NOR Flash, but for the condition that some memory cells of a chip are required to be small and the cost can be accepted, the reliability of NOR Flash is the best, each bit line is connected with one memory cell, and when the data of the memory cell is read, the data reading reliability is ensured because no other memory cell on the bit line can cause over-erasing influence on the memory cell connected with the bit line, thereby effectively avoiding the risk of data misreading caused by over-erasing and improving the reliability of the memory cell array.
Description
Technical Field
The invention relates to the technical field of NOR Flash, in particular to a high-reliability nonvolatile memory and a memory cell array thereof.
Background
As shown in fig. 1, in the common NOR Flash memory cell array, a bit line is connected to a plurality of memory cells at the same time, and there is a possibility that an over-erased cell in the same bit line causes a data misreading in a memory cell of an adjacent address (i.e., a memory cell on the same bit line as the over-erased cell), which reduces the reliability of the memory cell of NOR Flash, and especially for a very important non-volatile status register, the common NOR Flash memory cell array cannot meet the requirement of high reliability.
Therefore, the prior art still needs to be improved and developed.
Disclosure of Invention
The invention aims to provide a high-reliability nonvolatile memory cell array and a nonvolatile memory, and aims to solve the problem that the existing NOR Flash memory cell array cannot meet the requirement of high reliability for positioning due to over-erasure.
The technical scheme of the invention is as follows: a high-reliability memory cell array of a nonvolatile memory comprises a plurality of bit lines and a plurality of word lines, wherein the word lines and the bit lines are distributed and connected according to a # -shaped arrangement, a memory cell is arranged at the intersection of each word line and each bit line, and each bit line is only connected with one memory cell on the bit line.
The memory cell array of the high-reliability nonvolatile memory is provided, wherein the number of the word lines and the number of the bit lines are as large; or the number of word lines is greater than the number of bit lines; or the number of word lines is less than the number of bit lines.
The memory cell array of the high-reliability nonvolatile memory is characterized in that all the memory cells connected with the corresponding bit lines are positioned on the same word line.
In the memory cell array of the high-reliability nonvolatile memory, when the number of the word lines is consistent with that of the bit lines, each word line is provided with a memory cell connected with the corresponding bit line.
In the memory cell array of the high-reliability nonvolatile memory, when the number of the word lines is consistent with that of the bit lines, each word line is provided with a memory cell connected with the corresponding bit line, and all the memory cells connected with the corresponding bit lines are positioned on the same diagonal line.
In the memory cell array of the high-reliability nonvolatile memory, when the number of the word lines is the same as that of the bit lines, one memory cell is connected with the nth bit line, the memory cell is positioned on the (n + 1) th word line, and the memory cell connected with the last bit line is positioned on the first word line.
In the memory cell array of the high-reliability nonvolatile memory, when the number of the word lines is greater than that of the bit lines, one memory cell is connected with the nth bit line, and the memory cell is positioned on the (n + 1) th word line.
When the number of the bit lines is larger than that of the word lines, different memory cells connected with the corresponding bit lines are positioned on the same word line or different word lines.
A non-volatile memory comprising a memory cell array of a highly reliable non-volatile memory as claimed in any one of the preceding claims.
The invention has the beneficial effects that: the invention provides a high-reliability nonvolatile memory and a memory cell array thereof, wherein each bit line is connected with only one memory cell on the bit line, which may waste most of the memory space in NOR Flash, but for the condition that the chip memory capacity is small and the cost can be accepted, the reliability of NOR Flash is the best, each bit line is connected with one memory cell, when the data of the memory cell is read, the data reading reliability is ensured because no other memory cell on the bit line can cause over-erasing influence on the memory cell connected with the bit line, thereby effectively avoiding the risk of data reading error caused by over-erasing and improving the reliability of the memory cell array.
Drawings
FIG. 1 is a schematic diagram of a NOR Flash memory cell array in the prior art.
FIG. 2 is a schematic diagram of a memory cell array of the nonvolatile memory of the present invention.
FIG. 3 is a schematic view of example 1 of the present invention.
FIG. 4 is a schematic view of example 2 of the present invention.
FIG. 5 is a schematic view of example 3 of the present invention.
FIG. 6 is a schematic view of example 4 of the present invention.
FIG. 7 is a schematic view of example 5 of the present invention.
FIG. 8 is a schematic view of example 6 of the present invention.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations. Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the present application without making any creative effort, shall fall within the protection scope of the present application.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. Meanwhile, in the description of the present application, the terms "first", "second", and the like are used only for distinguishing the description, and are not to be construed as indicating or implying relative importance.
As shown in fig. 1, a memory cell array of a high-reliability nonvolatile memory includes a plurality of bit lines and a plurality of word lines, the word lines and the bit lines are distributed and connected according to a # -shaped arrangement, a memory cell is disposed at an intersection of each word line and each bit line, and each bit line is connected to only one memory cell on the bit line.
In the technical scheme, each bit line is only connected with one storage unit on the bit line, so that most of storage space in NOR Flash can be wasted, but for the conditions that the storage capacity of a chip is required to be small and the cost can be accepted, the reliability of the NOR Flash is the best, one storage unit is connected to each bit line, and when the data of the storage unit is read, because no other storage unit on the bit line can cause over-erasing influence on the storage unit connected with the bit line, the reliability of data reading is ensured, the risk of data misreading caused by over-erasing can be effectively avoided, and the reliability of the storage unit array is improved.
In some embodiments, the number of the word lines and the bit lines can be set according to actual needs, such as the number of the word lines and the bit lines is as large as the number of the bit lines, or the number of the word lines is larger than the number of the bit lines, or the number of the word lines is smaller than the number of the bit lines.
The arrangement of each memory cell connected to the corresponding bit line on the word line can be set according to actual needs, as long as each bit line is only connected to one memory cell on the bit line:
example 1
In some embodiments, all of the memory cells connected to the corresponding bit lines are located on the same word line, as shown in FIG. 3.
Example 2
In some embodiments, when the number of word lines and bit lines is the same, each word line is provided with a memory cell connected to the corresponding bit line, as shown in fig. 4.
Example 3
In some embodiments, when the number of word lines and bit lines is the same, each word line has a memory cell connected to the corresponding bit line, and all the memory cells connected to the corresponding bit line are located on the same diagonal line, as shown in fig. 5.
Example 4
In some embodiments, when the number of word lines and bit lines is the same, a memory cell is connected to the nth bit line, the memory cell is located on the (n + 1) th word line, and the memory cell connected to the last bit line is located on the first word line, as shown in fig. 6.
Example 5
In some embodiments, when the number of word lines is greater than the number of bit lines, a memory cell is connected to the nth bit line, and the memory cell is located on the (n + 1) th word line, as shown in fig. 7.
Example 6
In some embodiments, when the number of bit lines is greater than the number of word lines, different memory cells connected to the corresponding bit lines are located on the same word line or on different word lines, as shown in FIG. 8.
The technical scheme also protects a nonvolatile memory which comprises the memory cell array of the high-reliability nonvolatile memory.
In the embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
In addition, units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
Furthermore, the functional modules in the embodiments of the present application may be integrated together to form an independent part, or each module may exist separately, or two or more modules may be integrated to form an independent part.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions.
The above description is only an example of the present application and is not intended to limit the scope of the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims (9)
1. The memory cell array of the high-reliability nonvolatile memory is characterized by comprising a plurality of bit lines and a plurality of word lines, wherein the word lines and the bit lines are distributed and connected according to a # -shaped arrangement, a memory cell is arranged at the intersection of each word line and each bit line, and each bit line is only connected with one memory cell on the bit line.
2. The memory cell array of a high-reliability nonvolatile memory according to claim 1, wherein the number of the word lines and the bit lines is as large as that of the bit lines; or the number of word lines is greater than the number of bit lines; or the number of word lines is less than the number of bit lines.
3. The memory cell array of a high reliability nonvolatile memory according to any one of claims 1 or 2, wherein all the memory cells connected to the corresponding bit lines are located on the same word line.
4. The memory cell array of claim 2, wherein when the number of the word lines and the number of the bit lines are the same, each word line is provided with a memory cell connected to the corresponding bit line.
5. The memory cell array of claim 2, wherein when the number of the word lines and the number of the bit lines are the same, each word line is provided with a memory cell connected to the corresponding bit line, and all the memory cells connected to the corresponding bit line are located on the same diagonal line.
6. The memory cell array of claim 2, wherein when the number of the word lines and the number of the bit lines are the same, one memory cell is connected to the nth bit line, the memory cell is located on the (n + 1) th word line, and the memory cell connected to the last bit line is located on the first word line.
7. The memory cell array of claim 2, wherein when the number of word lines is greater than the number of bit lines, one memory cell is connected to the nth bit line, and the memory cell is located on the (n + 1) th word line.
8. The memory cell array of claim 2, wherein when the number of bit lines is greater than the number of word lines, different memory cells connected to the corresponding bit lines are located on the same word line or on different word lines.
9. A nonvolatile memory comprising a memory cell array of the highly reliable nonvolatile memory according to any one of claims 1 to 8.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113409840A (en) * | 2021-06-30 | 2021-09-17 | 芯天下技术股份有限公司 | State register and write operation method, chip and device thereof |
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- 2020-12-29 CN CN202011593924.9A patent/CN112435697A/en active Pending
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