CN112434774A - Electronic tag demodulation circuit and electronic tag - Google Patents
Electronic tag demodulation circuit and electronic tag Download PDFInfo
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- CN112434774A CN112434774A CN202011313999.7A CN202011313999A CN112434774A CN 112434774 A CN112434774 A CN 112434774A CN 202011313999 A CN202011313999 A CN 202011313999A CN 112434774 A CN112434774 A CN 112434774A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
- G06K19/0775—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card arrangements for connecting the integrated circuit to the antenna
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/06—Clock generators producing several clock signals
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
- G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
- G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
- G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
- G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
- G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
- G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card
- G06K19/07773—Antenna details
- G06K19/07775—Antenna details the antenna being on-chip
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The invention discloses a demodulation circuit of an electronic tag and the electronic tag. The demodulation circuit includes: the device comprises an amplitude modulation module, a modulation depth clamping module, a switch module, a clock detection module and a digital processing module; the control end of the amplitude modulation module is electrically connected with the output end of the digital processing module and is used for receiving the modulation signal output by the digital processing module so as to perform amplitude modulation on the waveform of the antenna module; the modulation depth clamping module is connected between the amplitude modulation module and the antenna module; the control end of the switch module is electrically connected with the antenna module, the first end of the switch module is electrically connected with the input end of the clock detection module, and the second end of the switch module is connected with the reference signal; the output end of the clock detection module is electrically connected with the input end of the digital processing module, and the clock detection module is used for outputting a demodulation signal. The invention realizes that only the command groove of the reader-writer is demodulated, and the return of the electronic tag is not demodulated.
Description
Technical Field
The embodiment of the invention relates to an electronic tag technology, in particular to a demodulation circuit of an electronic tag and the electronic tag.
Background
In most of the existing low-frequency communication protocols of electronic tags, after the electronic tags are powered on in the field of a reader-writer, modulated data frames are returned circularly and repeatedly, and the data frames are stopped from being returned until an instruction groove sent by the reader-writer is detected, so that the electronic tags enter a mode of receiving instructions. This communication mode is called ttf (tag Talk first).
In this mode, if the command is demodulated by using the conventional antenna end carrier envelope demodulation method, the command of the reader-writer and the return modulation signal of the electronic tag cannot be distinguished, because the command notch of the reader-writer and the return modulation signal of the electronic tag both cause the waveform of the antenna end to appear as notches, and both are demodulated by the envelope demodulator.
Disclosure of Invention
The invention provides a demodulation circuit of an electronic tag and the electronic tag, which are used for demodulating only an instruction groove of a reader-writer without demodulating the return of the electronic tag.
In a first aspect, an embodiment of the present invention provides a demodulation circuit of an electronic tag, where the electronic tag includes an antenna module, and the demodulation circuit includes: the device comprises an amplitude modulation module, a modulation depth clamping module, a switch module, a clock detection module and a digital processing module;
the control end of the amplitude modulation module is electrically connected with the output end of the digital processing module and is used for receiving the modulation signal output by the digital processing module so as to perform amplitude modulation on the waveform of the antenna module;
the modulation depth clamping module is connected between the amplitude modulation module and the antenna module and is used for clamping the waveform of the antenna module;
the control end of the switch module is electrically connected with the antenna module, the first end of the switch module is electrically connected with the input end of the clock detection module, and the second end of the switch module is connected with a reference signal;
the input end of the clock detection module is connected with a pull-up level signal, the output end of the clock detection module is electrically connected with the input end of the digital processing module, and the clock detection module is used for outputting a demodulation signal according to a signal input by the input end of the clock detection module;
the output end of the digital processing module is electrically connected with the control end of the amplitude modulation module, and the digital processing module is used for inputting the demodulation signal according to the input end of the digital processing module and continuously or stopping outputting the modulation signal.
Optionally, the modulation depth clamping module includes a first modulation depth clamping unit; a first end of the first modulation depth clamping unit is electrically connected with the antenna module, a control end of the first modulation depth clamping unit is electrically connected with a first end of the first modulation depth clamping unit, and a second end of the first modulation depth clamping unit is electrically connected with a first end of the amplitude modulation module; and the second end of the amplitude modulation module is accessed to the reference signal.
Optionally, the switch module includes a first switch unit; the control end of the first switch unit is electrically connected with the antenna module, the first end of the first switch unit is electrically connected with the input end of the clock detection module, and the second end of the first switch unit is connected to the reference signal.
Optionally, the clock detection module includes a first clock detection unit; the input end of the first clock detection unit is electrically connected with the first output end of the first switch unit, and the output end of the first clock detection unit is electrically connected with the input end of the digital processing module.
Optionally, the antenna module includes a first antenna unit and a second antenna unit in a differential structure; the modulation depth clamping module comprises a first modulation depth clamping unit and a second modulation depth clamping unit; a first end of the first modulation depth clamping unit is electrically connected with the first antenna unit, a control end of the first modulation depth clamping unit is electrically connected with a first end of the first modulation depth clamping unit, and a second end of the first modulation depth clamping unit is electrically connected with a first end of the amplitude modulation module; the first end of the second modulation depth clamping unit is electrically connected with the second antenna unit, the control end of the second modulation depth clamping unit is electrically connected with the first end of the second modulation depth clamping unit, and the third end of the second modulation depth clamping unit is electrically connected with the second end of the amplitude modulation module.
Optionally, the switch module includes a first switch unit and a second switch unit; the control end of the first switch unit is electrically connected with the first antenna unit, the first end of the first switch unit is electrically connected with the first input end of the clock detection module, and the second end of the first switch unit is electrically connected with the second antenna unit; the control end of the second switch unit is electrically connected with the second antenna unit, the first end of the second switch unit is electrically connected with the second input end of the clock detection module, and the second end of the second switch unit is electrically connected with the first antenna unit.
Optionally, the clock detection module includes a first clock detection unit and a second clock detection unit, an input end of the first clock detection unit is electrically connected to the first end of the first switch unit, and an output end of the first clock detection unit is electrically connected to an input end of the digital processing module; the input end of the second clock detection unit is electrically connected with the first end of the second switch unit, and the output end of the second clock detection unit is electrically connected with the input end of the digital processing module.
Optionally, the demodulation circuit of the electronic tag further includes: a hysteresis module;
the first end of the hysteresis module is electrically connected with the power supply, the second end of the hysteresis module is electrically connected with the input end of the clock detection module, and the control end of the hysteresis module is electrically connected with the output end of the clock detection module and used for increasing the conduction voltage of the switch module when the control end of the hysteresis module receives the demodulation signal.
Optionally, the demodulation circuit of the electronic tag further includes: an amplitude clamping module;
the first end of the amplitude clamping module is electrically connected with the antenna module, the second end of the amplitude clamping module is electrically connected with the control end of the switch module, and the third end of the amplitude clamping module is connected to the reference signal and is used for clamping the waveform of the antenna module.
In a second aspect, an embodiment of the present invention further provides an electronic tag, where the electronic tag includes the demodulation circuit of the electronic tag according to the first aspect, and further includes an antenna module.
According to the invention, by arranging the amplitude modulation module and the modulation depth clamping module, when the returned modulation signal is at a high level, the amplitude of the waveform of the antenna module is the threshold voltage of the modulation depth clamping module. When the reader-writer does not send the command groove and the returned modulation signal is at a high level, the amplitude of the waveform of the antenna module is clamped to the threshold voltage of the modulation depth clamping module by the modulation depth clamping module, so that the switch module is in a conducting state, the clock detection module can output the demodulation signal as a high level according to the low level signal of the reference signal, and the demodulation signal of the low level can not be demodulated when the electronic tag returns the modulation signal. When the reader-writer sends the instruction groove, no matter the returned modulation signal is high level or low level, the waveform of the antenna module is low level, so that the switch module is in a cut-off state, the clock detection module cannot acquire the reference signal but acquires a pull-up level signal, the clock detection module overturns to output a demodulation signal which is a low level signal, and the instruction groove of the reader-writer is demodulated. The problem that the waveform of the antenna end can be recessed due to the command recess of the reader-writer and the return modulation signal of the electronic tag and can be demodulated by the envelope demodulator is solved, and the effect that only the command recess is demodulated, but the return modulation signal is not demodulated is achieved.
Drawings
Fig. 1 is a schematic structural diagram of a demodulation circuit of an electronic tag according to the present invention;
fig. 2 is a schematic structural diagram of a demodulation circuit of another electronic tag provided by the invention;
FIG. 3 is a schematic structural diagram of a clock detection module according to the present invention;
fig. 4 is a schematic structural diagram of a demodulation circuit of another electronic tag provided by the present invention;
fig. 5 is a schematic structural diagram of an electronic tag provided by the present invention.
Detailed Description
The present invention will be described in further detail with reference to the accompanying drawings and examples. It is to be understood that the specific embodiments described herein are merely illustrative of the invention and are not limiting of the invention. It should be further noted that, for the convenience of description, only some of the structures related to the present invention are shown in the drawings, not all of the structures.
Fig. 1 is a schematic structural diagram of a demodulation circuit of an electronic tag according to an embodiment of the present invention, where the embodiment is applicable to a signal demodulation situation of the electronic tag, and referring to fig. 1, the electronic tag includes an antenna module, and the demodulation circuit of the electronic tag includes: the amplitude modulation module 110, the modulation depth clamping module 120, the switching module 130, the clock detection module 140 and the digital processing module 150; the control terminal a1 of the amplitude modulation module 110 is electrically connected to the output terminal B1 of the digital processing module, and is configured to receive the modulated signal output by the digital processing module 150 to perform amplitude modulation on the waveform of the antenna module 200; the modulation depth clamping module 120 is connected between the amplitude modulation module 110 and the antenna module 200, and is configured to clamp a waveform of the antenna module 200; the control terminal C1 of the switch module 130 is electrically connected to the antenna module 200, the first terminal C2 of the switch module 130 is electrically connected to the input terminal D1 of the clock detection module 140, and the second terminal C3 of the switch module 130 is connected to the reference signal; the input end D1 of the clock detection module 140 is connected to the pull-up level signal 301, the output end D2 of the clock detection module 140 is electrically connected to the input end B2 of the digital processing module 150, and the clock detection module 140 is configured to output a demodulation signal according to a signal input by the input end thereof; the output terminal B1 of the digital processing module 150 is electrically connected to the control terminal a1 of the amplitude modulation module 110, and the digital processing module 150 is configured to continue or stop outputting the modulation signal according to the input terminal B2 of the demodulation signal.
Wherein, the electronic tag is also called as a radio frequency tag, a transponder or a data carrier; the space (non-contact) coupling of radio frequency signals is realized between the electronic tag and the reader-writer through a coupling element; and in the coupling channel, energy transfer and data exchange are realized according to a time sequence relation. The amplitude modulation module 110 is configured to receive a return modulation signal of the electronic tag, and perform amplitude modulation on the waveform of the antenna module 200 according to the return modulation signal, where the amplitude modulation module 110 may be a transistor, for example, when the return modulation signal is at a low level, the amplitude modulation module 110 is in an off state, and does not perform amplitude modulation on the waveform of the antenna end, and when the return modulation signal is at a high level, the amplitude modulation module 110 is in an on state, and performs amplitude modulation on the waveform of the antenna end. The modulation depth clamping module 120 may clamp the waveform of the antenna module 200, the modulation depth clamping module 120 may be a transistor, for example, when the returned modulation signal is at a high level, the amplitude modulation module 110 is in a conducting state, and since the control end and the first end of the modulation depth clamping module 120 are both electrically connected to the antenna module 200, the modulation depth clamping module 120 may be turned on only when the waveform of the antenna module 200 is greater than the threshold voltage of the modulation depth clamping module 120, so that the amplitude of the waveform of the antenna module 200 is clamped at the threshold voltage of the modulation depth clamping module 120. Such that the amplitude of the antenna block 200 waveform is the threshold voltage of the modulation depth clamp block 120 when the returned modulation signal is high. When the returned modulation signal is at a low level, the waveform of the antenna module 200 is a high level signal.
The switch module 130 is turned on when the waveform of the antenna module 200 is at a high level, and is turned off when the waveform of the antenna module 200 is at a low level. And the voltage required for the switching module 130 to turn on is less than the threshold voltage of the modulation depth clamp module 120. When the switch module 130 is in a conducting state, the input end of the clock detection module 140 is pulled down to a low level by the reference signal 160, the reference signal 160 is grounded, for example, at this time, a low level signal is input to the input end of the clock detection module 140, the output end of the clock detection module 140 can output a demodulation signal of a first level at this time, when the digital processing module 150 receives the demodulation signal of the first level, it is determined that the waveform voltage of the antenna module 200 is higher, that is, no instruction groove is present, and the digital processing module 150 can continuously output the modulation signal, so that the electronic tag sends data to the reader through the antenna module 200; when the switch module 130 is in an off state, the input terminal of the clock detection module 140 is a pull-up level signal 301, the pull-up level signal 301 is, for example, a high level signal, the pull-up level signal 301 may be realized by, for example, a P-type MOS transistor (metal oxide semiconductor, MOS) that is pulled up to a power supply through a pull-up current source, or the pull-up level signal 301 may be realized by other manners, which is not specifically limited herein. At this time, the voltage at the input end of the clock detection module 140 is pulled high, the output end of the clock detection module 140 outputs the demodulated signal of the second level, the digital processing module receives the demodulated signal of the second level, and determines that the waveform voltage of the antenna module at this time is low, that is, it is possible that the reader/writer sends the command slot, at this time, the digital processing module 150 stops outputting the modulated signal, and the waveform of the modulated signal on the antenna module 200 is prevented from interfering with the analysis command slot. The first level and the second level have opposite polarities, for example, the first level is a high level, and the second level is a low level, or the first level is a low level and the second level is a high level.
Specifically, when the reader/writer does not send a command slot and the returned modulation signal is at a high level, the amplitude of the waveform of the antenna module 200 is clamped to the threshold voltage of the modulation depth clamping module 120 by the modulation depth clamping module 120, so that the switch module 130 is in a conducting state, and the clock detection module 140 may output the demodulation signal as a high level according to the low level signal of the reference signal 160. When the reader/writer does not send the command slot and the returned modulation signal is at a low level, the waveform of the antenna module 200 is at a high level, so that the switch module 130 is in a conducting state, and the clock detection module 140 can output a demodulation signal at a high level according to the low level signal of the reference signal 160. When the reader-writer sends the command groove, no matter whether the returned modulation signal is a high level or a low level, the waveform of the antenna module 200 is a low level, so that the switch module 130 is in a cut-off state, the clock detection module 140 cannot acquire the reference signal 160 but acquires the pull-up level signal 301, the demodulation signal is output as a low level signal after the clock detection module 140 is turned over, the digital processing module stops outputting the modulation signal at the moment, the waveform of the modulation signal on the antenna module is prevented from interfering with the analysis command groove, and the command groove of the reader-writer is demodulated. The effect that only the command groove is demodulated, and the return modulation and demodulation are not performed is achieved.
According to the technical scheme of the embodiment, the amplitude modulation module and the modulation depth clamping module are arranged, so that when the returned modulation signal is at a high level, the amplitude of the waveform of the antenna module is the threshold voltage of the modulation depth clamping module. When the reader-writer does not send the command groove and the returned modulation signal is at a high level, the amplitude of the waveform of the antenna module is clamped to the threshold voltage of the modulation depth clamping module by the modulation depth clamping module, so that the switch module is in a conducting state, the clock detection module can output the demodulation signal as a high level according to the low level signal of the reference signal, and the demodulation signal of the low level can not be demodulated when the electronic tag returns the modulation signal. When the reader-writer sends the instruction groove, no matter the returned modulation signal is high level or low level, the waveform of the antenna module is low level, so that the switch module is in a cut-off state, the clock detection module cannot acquire the reference signal but acquires the pull-up high level signal 301, the demodulation signal is output to be a low level signal after the clock detection module is turned over, the digital processing module stops outputting the modulation signal at the moment, the waveform of the modulation signal on the antenna module is prevented from generating interference on the analysis instruction groove, and the instruction groove of the reader-writer is demodulated. The problem that the waveform of the antenna end can be recessed due to the command recess of the reader-writer and the return modulation signal of the electronic tag and can be demodulated by the envelope demodulator is solved, and the effect that only the command recess is demodulated, but the return modulation signal is not demodulated is achieved.
Optionally, fig. 2 is a schematic structural diagram of a demodulation circuit of another electronic tag according to an embodiment of the present invention, and referring to fig. 2, the modulation depth clamping module 120 includes a first modulation depth clamping unit 121; the first terminal E1 of the first modulation depth clamping unit 121 is electrically connected to the antenna module 200, the control terminal E2 of the first modulation depth clamping unit 121 is electrically connected to the first terminal E1 of the first modulation depth clamping unit 121, and the second terminal E3 of the first modulation depth clamping unit 121 is electrically connected to the first terminal a2 of the amplitude modulation module 110; a second terminal of the amplitude modulation module 110 accesses the reference signal 160.
Illustratively, the modulation depth clamping module 120 may include a first modulation depth clamping unit 121, and the first modulation depth clamping unit 121 may be, for example, a MOS transistor, and when the returned modulation signal is at a high level, the first modulation depth clamping unit 121 is in a conducting state, and since the control terminal and the first terminal of the first modulation depth clamping unit 121 are both electrically connected to the antenna module 200, the first modulation depth clamping unit is only turned on when the waveform of the antenna module 200 is greater than the threshold voltage of the first modulation depth clamping unit, so that the clamping amplitude of the waveform of the antenna module 200 is at the threshold voltage of the first modulation depth clamping unit. So that the amplitude of the antenna block 200 waveform is the threshold voltage of the first modulation depth clamping unit when the returned modulation signal is high level.
Alternatively, referring to fig. 2, the switching module 130 includes a first switching unit 131; the control terminal of the first switch unit 131 is electrically connected to the antenna module 200, the first terminal of the first switch unit 131 is electrically connected to the input terminal D1 of the clock detection module 140, and the second terminal of the first switch unit 131 is connected to the reference signal 160.
Specifically, the switch module 130 may include a first switch unit 131, and the first switch unit 131 may be, for example, a MOS transistor, and the first switch unit 131 is turned on when the waveform of the antenna module 200 is at a high level and turned off when the waveform of the antenna module 200 is at a low level. And the voltage required when the first switching unit 131 is turned on is less than the threshold voltage of the modulation depth clamp module 120. When the first switching unit 131 is in a turned-on state, the clock detection module 140 may output the demodulation signal to a high level according to a low level signal of the reference signal 160. The groove signal can not be demodulated when the return modulation signal is at a high level, and the effect of not demodulating the return modulation signal is realized. For example, the reference signal 160 may be ground.
When the reader/writer does not send a command notch and the returned modulation signal is at a high level, the amplitude of the waveform of the antenna module 200 is clamped to the threshold voltage of the modulation depth clamping module 120 by the modulation depth clamping module 120, so that the first switch unit 131 is in a conducting state, and the clock detection module 140 may output a demodulation signal at a high level according to the low level signal of the reference signal 160. When the reader/writer does not send the command slot and the returned modulation signal is at a low level, the waveform of the antenna module 200 is at a high level, so that the first switch unit 131 is in a conducting state, and the clock detection module 140 can output the demodulation signal as a high level according to the low level signal of the reference signal 160. When the reader-writer sends the command groove, no matter whether the returned modulation signal is a high level or a low level, the waveform of the antenna module 200 is a low level, so that the switch module 130 is in a cut-off state, the clock detection module 140 cannot acquire the reference signal 160 but acquires the pull-up level signal 301, the demodulation signal is output as a low level signal after the clock detection module 140 is turned over, the digital processing module stops outputting the modulation signal at the moment, the waveform of the modulation signal on the antenna module is prevented from interfering with the analysis command groove, and the command groove of the reader-writer is demodulated. The effect that only the command groove is demodulated, and the return modulation and demodulation are not performed is achieved.
Alternatively, referring to fig. 2, the clock detection module 140 includes a first clock detection unit 141; an input terminal of the first clock detection unit 141 is electrically connected to a first output terminal of the first switching unit 131, and an output terminal of the first clock detection unit 141 is electrically connected to the input terminal B2 of the digital processing module 150.
Specifically, the clock detection module 140 includes a first clock detection unit 141, referring to fig. 3, and fig. 3 is a schematic structural diagram of the clock detection module provided by the present invention, where the first clock detection unit 141 includes at least one flip-flop, and when the waveform of the antenna module 200 is at a high level, the switch module 130 is turned on, so that the input end of the clock detection module 140 is at a low level, the outputs Q of the TFF flip-flop and the DFF flip-flop are set to 0, and the demodulation signal is at a high level. When the waveform of the antenna module 200 is at a low level, the switch module 130 is turned off, the input terminal of the clock detection module 140 is at a high level, the TFF flip-flop and the DFF flip-flop start to operate normally, and the counting clock 143 is divided by the multiple stages of TFF flip-flops and transmitted to the next stage. If the time that the input terminal of the clock detection module 140 is maintained at the high level exceeds the preset time Toff, so that the D terminal is still at the high level when the CP terminal of the DFF flip-flop has a rising edge, the demodulation signal will be turned to the low level, and the command notch will be demodulated. The length of Toff is determined by the frequency of the count clock 143 and the number of stages of the TFF flip-flops. If the input of the clock detection module 140 is asserted high for less than Toff, the CP of the DFF flip-flop is reset to 0 before the rising edge, and the demodulated signal remains high. The digital processing module 150 maintains the mode of cyclically returning data frames in the TTF mode when a low level of the demodulation signal is not received. When the low level of the first demodulated signal is received, the digital processing module 150 immediately stops returning the data frame. When the first low level of the demodulated signal jumps back to the high level, the digital processing module 150 starts to cycle back to the synchronous modulated signal according to the code rate of the instruction, which is characterized in that the instruction groove coincides with the high level part of the synchronous modulated signal. The first switching unit 131 is turned on when the waveform of the antenna module 200 is at a high level, and is turned off when the waveform of the antenna module 200 is at a low level. And the voltage required when the first switching unit 131 is turned on is less than the threshold voltage of the modulation depth clamp module 120. When the first switch unit 131 is in a conducting state, the first clock detection unit 141 can obtain a low-level signal of the reference signal 160, and the signal is inverted into a high-level signal through the first clock detection unit 141, that is, the demodulated signal can be output as a high-level signal, so that when the return modulated signal is at a high level, the groove signal cannot be demodulated, and the effect of not demodulating the return modulated signal is achieved.
When the reader/writer does not send the command slot and the returned modulation signal is at a high level, the amplitude of the waveform of the antenna module 200 is clamped to the threshold voltage of the modulation depth clamping module 120 by the modulation depth clamping module 120, so that the first switch unit 131 is in a conducting state, and the first clock detection unit 141 can output the demodulation signal as a high level according to the low level signal of the reference signal 160. When the reader/writer does not send the command slot and the returned modulation signal is at a low level, the waveform of the antenna module 200 is at a high level, so that the first switching unit 131 is in a conducting state, and the first clock detection unit 141 can output a demodulation signal at a high level according to the low level signal of the reference signal 160. When the reader/writer sends the command slot, the waveform of the antenna module 200 is low no matter whether the returned modulation signal is high level or low level, so that the switch module 130 is in a cut-off state, the first clock detection unit 141 cannot acquire the reference signal 160 but acquires a pull-up level signal, and the demodulated signal is output as a low level signal after being turned over by the first clock detection unit 141, so that the command slot of the reader/writer is demodulated. The effect that only the command groove is demodulated, and the return modulation and demodulation are not performed is achieved.
Optionally, referring to fig. 4, fig. 4 is a schematic structural diagram of a demodulation circuit of another electronic tag according to an embodiment of the present invention, where the antenna module 200 includes a first antenna unit 210 and a second antenna unit 220 in a differential structure; the modulation depth clamping module 120 includes a first modulation depth clamping unit 121 and a second modulation depth clamping unit 122; a first end of the first modulation depth clamping unit 121 is electrically connected to the first antenna unit 210, a control end of the first modulation depth clamping unit 121 is electrically connected to a first end of the first modulation depth clamping unit 121, and a second end of the first modulation depth clamping unit 121 is electrically connected to a first end of the amplitude modulation module 110; a first end of the second modulation depth clamping unit 122 is connected to the second antenna unit 220, a control end of the second modulation depth clamping unit 122 is electrically connected to a first end of the second modulation depth clamping unit 122, and a third end of the second modulation depth clamping unit 122 is electrically connected to a second end of the amplitude modulation module 110.
Illustratively, the modulation depth clamp module 120 may include a first modulation depth clamp unit 121 and a second modulation depth clamp unit 122, and the first modulation depth clamp unit 121 and the second modulation depth clamp unit 122 may be, for example, MOS transistors (metal oxide semiconductors). When the returned modulation signal is at a high level, the first modulation depth clamping unit 121 is in a conducting state, and since the control terminal and the first terminal of the first modulation depth clamping unit 121 are both electrically connected to the first antenna unit 210, the first modulation depth clamping unit 121 is only conducted when the waveform of the first antenna unit 210 is greater than the threshold voltage of the first modulation depth clamping unit, so that the amplitude of the waveform of the first antenna unit 210 is clamped at the threshold voltage of the first modulation depth clamping unit. Such that the amplitude of the first antenna element 210 waveform is the threshold voltage of the first modulation depth clamping element when the returned modulation signal is high. When the returned modulation signal is at a high level, the second modulation depth clamping unit 122 is in a conducting state, and since the control terminal and the first terminal of the second modulation depth clamping unit 122 are both electrically connected to the second antenna unit 220, the second modulation depth clamping unit 122 is only conducted when the waveform of the second antenna unit 220 is greater than the threshold voltage of the second modulation depth clamping unit 122, so that the amplitude of the waveform of the second antenna unit 220 is clamped at the threshold voltage of the second modulation depth clamping unit 122. So that the amplitude of the second antenna element 220 waveform is the threshold voltage of the second modulation depth clamping unit 122 when the returned modulation signal is high level. Therefore, when the return modulation signal is at a high level, the groove signal can not be demodulated, and the effect of not demodulating the return modulation is achieved.
Alternatively, referring to fig. 4, the switching module 130 includes a first switching unit 131 and a second switching unit 132; the control end of the first switch unit 131 is electrically connected to the first antenna unit 210, the first end of the first switch unit 131 is electrically connected to the first input end of the clock detection module 140, and the second end of the first switch unit 131 is electrically connected to the second antenna unit 220; the control terminal of the second switch unit is electrically connected to the second antenna unit 220, the first terminal of the second switch unit 132 is electrically connected to the second input terminal of the clock detection module 140, and the second terminal of the second switch unit 132 is electrically connected to the first antenna unit 210.
Specifically, the switch module 130 includes a first switch unit 131 and a second switch unit 132, and the first switch unit 131 and the second switch unit 132 may be MOS transistors, for example. The first switching unit 131 is turned on when the waveform of the first antenna unit 210 is at a high level, and is turned off when the waveform of the first antenna unit 210 is at a low level. And the voltage required when the first switching unit 131 is turned on is less than the threshold voltage of the modulation depth clamp module 120. When the first switching unit 131 is in a conducting state, the clock detection module 140 may output a demodulation signal at a high level according to a low level signal of the second antenna unit 220. The second switch 132 is turned on when the waveform of the second antenna unit 220 is at a high level, and turned off when the waveform of the second antenna unit 220 is at a low level. And the voltage required for the second switching unit 132 to turn on is less than the threshold voltage of the modulation depth clamp module 120. When the second switching unit 132 is in a conducting state, the clock detecting module 140 may output the demodulated signal to a high level according to the low level signal of the first antenna unit 210. When the return modulation signal is at a high level, the groove signal can not be demodulated, and the effect of not demodulating the return modulation signal is realized.
Alternatively, referring to fig. 4, the clock detection module 140 includes a first clock detection unit 141 and a second clock detection unit 142, an input terminal of the first clock detection unit 141 is electrically connected to a first terminal of the first switch unit 131, and an output terminal of the first clock detection unit 141 is electrically connected to an input terminal of the digital processing module 150; an input end of the second clock detecting unit 142 is electrically connected to a first end of the second switching unit 132, and an output end of the second clock detecting unit 142 is electrically connected to an input end of the digital processing module 150.
Specifically, the clock detection module 140 includes a first clock detection unit 141 and a second clock detection unit 142, where the first clock detection unit 141 includes at least one flip-flop, and the second clock detection unit 142 includes at least one flip-flop. The first switching unit 131 is turned on when the waveform of the first antenna unit 210 is at a high level, and is turned off when the waveform of the antenna module 200 is at a low level. And the voltage required when the first switching unit 131 is turned on is less than the threshold voltage of the modulation depth clamp module 120. When the first switch unit 131 is in the on state, the first clock detection unit 141 may obtain the low level signal of the second antenna unit 220, and the signal is inverted into the high level signal through the first clock detection unit 141, that is, the demodulated signal is output as the high level signal. The second switch 132 is turned on when the waveform of the second antenna unit 220 is at a high level, and turned off when the waveform of the second antenna unit 220 is at a low level. And the voltage required for the second switching unit 132 to turn on is less than the threshold voltage of the modulation depth clamp module 120. When the second switch unit 132 is in the on state, the second clock detection unit 142 may obtain the low level signal of the first antenna unit 210, and the signal is inverted into the high level signal by the second clock detection unit 142, that is, the demodulated signal is output as the high level signal. When the return modulation signal is at a high level, the groove signal can not be demodulated, and the effect of not demodulating the return modulation signal is realized.
Optionally, referring to fig. 2 and 4, the demodulation circuit of the electronic tag further includes a hysteresis module 170; the first terminal of the hysteresis module 170 is electrically connected to the power supply 300, the second terminal of the hysteresis module 170 is electrically connected to the input terminal of the clock detection module 140, and the control terminal of the hysteresis module 170 is electrically connected to the output terminal of the clock detection module 140, and is configured to increase the on-voltage of the switch module when the control terminal receives the demodulation signal.
For example, referring to fig. 2, the hysteresis module 170 includes a first hysteresis current 171 and a first hysteresis unit 172. A first terminal of the first hysteresis current 171 is electrically connected to the power supply 300, a second terminal of the first hysteresis current 171 is electrically connected to a first terminal of the first hysteresis unit 172, a control terminal of the first hysteresis unit 172 is electrically connected to an output terminal of the clock detection module 140, and a second terminal of the first hysteresis unit 172 is electrically connected to a second terminal of the clock detection module. When the reader/writer sends the command slot, the waveform of the first antenna unit 210 is at a low level no matter whether the returned modulation signal is at a high level or a low level, so that the switch module 130 is in a cut-off state, the clock detection module 140 cannot acquire the second antenna unit 220, and the clock detection module 140 acquires the high level signal of the pull-up level signal 301, so that the output demodulation signal is at a low level. The first hysteresis unit 172 may be, for example, a P-type transistor, and when the demodulation signal is at a low level, the first hysteresis unit 172 is turned on, the first hysteresis current 171 is turned on, and hysteresis is added, so that the switch module 130 can be turned on only by a higher voltage, thereby suppressing misconduction of noise to the switch module 130, and ensuring that the demodulation signal is at a low level when the reader/writer sends the command notch, thereby demodulating the command signal.
It should be noted that the power supply 300 may supply power to all modules, and all modules need to be grounded.
For example, referring to fig. 4, the hysteresis module 170 includes a first hysteresis current 171, a first hysteresis unit 172, a second hysteresis current 174, and a second hysteresis unit 175. A first terminal of the first hysteresis current 171 is electrically connected to the power supply 300, a second terminal of the first hysteresis current 171 is electrically connected to a first terminal of the first hysteresis unit 172, a control terminal of the first hysteresis unit 172 is electrically connected to an output terminal of the first clock detection unit 141, and a second terminal of the first hysteresis unit 172 is electrically connected to a second terminal of the first clock detection unit 141. A first terminal of the second hysteresis current 174 is electrically connected to the power supply 300, a second terminal of the second hysteresis current 174 is electrically connected to a first terminal of the second hysteresis unit 175, a control terminal of the second hysteresis unit 175 is electrically connected to the output terminal of the second clock detecting unit 142, and a second terminal of the second hysteresis unit 175 is electrically connected to a second terminal of the second clock detecting unit 142. When the reader/writer sends the command slot, the waveform of the first antenna unit 210 is at a low level no matter whether the returned modulation signal is at a high level or a low level, so that the switch module 130 is in a cut-off state, the clock detection module 140 cannot acquire the second antenna unit 220, and the clock detection module 140 acquires the high level signal of the pull-up level signal 301, so that the output demodulation signal is at a low level. The first hysteresis unit 172 may be, for example, a P-type transistor, and when the demodulation signal is at a low level, the first hysteresis unit 172 is turned on, the first hysteresis current 171 is turned on, and hysteresis is added, so that the switch module 130 can be turned on only by a higher voltage, thereby suppressing misconduction of noise to the switch module 130, and ensuring that the demodulation signal is at a low level when the reader/writer sends the command notch, thereby demodulating the command signal.
Optionally, referring to fig. 2 and 4, the demodulation circuit of the electronic tag further includes an amplitude clamping module 180; the first end of the amplitude clamping module 180 is electrically connected to the antenna module 200, the second end of the amplitude clamping module 180 is electrically connected to the control end of the switch module, and the third end of the amplitude clamping module is connected to a reference signal for clamping the waveform of the antenna module.
Illustratively, referring to fig. 2, the amplitude clamping module 180 includes a first resistor R1 and a first amplitude clamping unit 181, a first end of the first resistor R1 is electrically connected to the antenna module 200, and a second end of the first resistor R1 is electrically connected to a control end of the first amplitude clamping unit 181. A first end of the first amplitude clamping unit 181 is electrically connected to a control end of the first amplitude clamping unit 181, and a second end of the first amplitude clamping unit 181 is electrically connected to the reference signal 160. The reference signal 160 may be, for example, ground. The first resistor R1 may clip the waveform of the antenna module 200 to protect the first amplitude clamping unit 181 from breakdown due to an excessively high input voltage, and the first amplitude clamping unit 181 may be, for example, a transistor, and may clamp the waveform of the antenna module 200 to limit the amplitude of the waveform of the antenna module 200 above a conduction threshold of the first amplitude clamping unit 181, so that the switch module 130 may be turned on.
Illustratively, referring to fig. 4, the amplitude clamping block 180 includes a first resistor R1, a first amplitude clamping unit 181, a second resistor R2, and a second amplitude clamping unit 182. A first end of the first resistor R1 is electrically connected to the first antenna unit 210, and a second end of the first resistor R1 is electrically connected to the control end of the first amplitude clamping unit 181. A first end of the first amplitude clamping unit 181 is electrically connected to a control end of the first amplitude clamping unit 181, and a second end of the first amplitude clamping unit 181 is grounded. A first end of the second resistor R2 is electrically connected to the second antenna element 220, and a second end of the second resistor R2 is electrically connected to the control end of the second amplitude clamping unit 182. A first end of the second amplitude clamping unit 182 is electrically connected to a control end of the second amplitude clamping unit 182, and a second end of the second amplitude clamping unit 182 is grounded. The second antenna element 220 may be, for example, a second antenna module. The first resistor R1 may clip the waveform of the first antenna element 210 to protect the first amplitude clamping unit 181 from breakdown due to an excessively high input voltage, and the first amplitude clamping unit 181 may be, for example, a transistor, and may clamp the waveform of the first antenna element 210 to limit the amplitude of the waveform of the first antenna element 210 above a turn-on threshold of the first amplitude clamping unit 181, so that the switching module 130 may be turned on. The second resistor R2 may clip the waveform of the second antenna element 220 to protect the second amplitude clamping unit 182 from breakdown due to an excessively high input voltage, and the second amplitude clamping unit 182 may be, for example, a transistor, and may clamp the waveform of the second antenna element 220 to limit the amplitude of the waveform of the second antenna element 220 above the turn-on threshold of the second amplitude clamping unit 182, so that the switching module 130 may be turned on.
Optionally, referring to fig. 2 and 4, the demodulation circuit of the electronic tag further includes a buffer module 190. A first end of the buffer module 190 is electrically connected to the first end of the switch module 130, and a second end of the buffer module 190 is electrically connected to the input end of the clock detection module 140.
Illustratively, referring to fig. 2, the buffer module 190 includes a first buffer 191, a first end of the first buffer 191 is electrically connected to a first end of the first switching unit 131 of the switching module 130, and a second end of the first buffer 191 is electrically connected to an input end of the first clock detecting unit 141 of the clock detecting module 140. The first buffer 191 may shape the obtained reference signal to obtain a clock signal.
Illustratively, referring to fig. 4, the buffer module 190 includes a first buffer 191 and a second buffer 192, a first end of the first buffer 191 is electrically connected to a first end of the first switching unit 131 of the switching module 130, and a second end of the first buffer 191 is electrically connected to an input end of the first clock detecting unit 141 of the clock detecting module 140. A first end of the second buffer 192 is electrically connected to a first end of the second switching unit 132 of the switching module 130, and a second end of the second buffer 192 is electrically connected to an input end of the second clock detecting unit 142 of the clock detecting module 140. The first and second buffers 191 and 192 may shape the obtained reference signal to obtain a clock signal.
Optionally, referring to fig. 2 and 4, the demodulation circuit of the electronic tag further includes a rectification circuit 400. Referring to fig. 2, a first end of the rectifying circuit 400 is electrically connected to the antenna module 200, a second end of the rectifying circuit 400 is electrically connected to the power supply 300, and a third end of the rectifying circuit 400 is connected to the reference signal 160. Referring to fig. 4, a first end of the rectifying circuit 400 is electrically connected to the antenna module 200, a second end of the rectifying circuit 400 is electrically connected to the power supply 300, a third end of the rectifying circuit 400 is connected to the reference signal 160, and a fourth end of the rectifying circuit 400 is grounded.
Specifically, the rectifier circuit is a circuit that converts ac power into dc power, and can convert ac power with a low voltage output from the ac voltage-reducing circuit into unidirectional pulsating dc power, so that the rectifier circuit 400 can convert a power signal into a pulse signal with a high or low level.
According to the technical scheme of the embodiment, the amplitude modulation module and the modulation depth clamping module are arranged, so that when the returned modulation signal is at a high level, the amplitude of the waveform of the antenna module is the threshold voltage of the modulation depth clamping module. When the reader-writer does not send the command groove and the returned modulation signal is at a high level, the amplitude of the waveform of the antenna module is clamped to the threshold voltage of the modulation depth clamping module by the modulation depth clamping module, so that the switch module is in a conducting state, the clock detection module can output the demodulation signal as a high level according to the low level signal of the reference signal, and the demodulation signal of the low level can not be demodulated when the electronic tag returns the modulation signal. When the reader-writer sends the instruction groove, no matter the returned modulation signal is high level or low level, the waveform of the antenna module is low level, so that the switch module is in a cut-off state, the clock detection module cannot acquire the reference signal but acquires a pull-up level signal, the clock detection module overturns to output a demodulation signal which is a low level signal, and the instruction groove of the reader-writer is demodulated. The problem that the waveform of the antenna end can be recessed due to the command recess of the reader-writer and the return modulation signal of the electronic tag and can be demodulated by the envelope demodulator is solved, and the effect that only the command recess is demodulated, but the return modulation signal is not demodulated is achieved.
Fig. 5 is a schematic structural diagram of an electronic tag according to an embodiment of the present invention, where the present embodiment is applicable to a signal demodulation situation of the electronic tag, and referring to fig. 5, the demodulation circuit 100 of the electronic tag according to any of the above embodiments of the electronic tag further includes a first antenna unit 210 and a second antenna unit 220.
By providing the demodulation circuit 100 of the electronic tag, when the reader/writer does not send a command slot and the returned modulation signal is at a high level, the demodulation circuit 100 of the electronic tag outputs a demodulation signal at a high level. When the reader/writer does not send the command slot and the returned modulation signal is at a low level, the demodulation circuit 100 of the electronic tag outputs a demodulation signal at a high level. When the reader/writer sends the command groove, no matter whether the returned modulation signal is high level or low level, the demodulation circuit 100 of the electronic tag outputs the demodulation signal as a low level signal, thereby demodulating the command groove of the reader/writer. The demodulation signal of low level can be demodulated only when the reader-writer sends the command groove, and the demodulation signal of low level can not be demodulated when the electronic tag returns the modulation signal. The effect that only the command groove is demodulated, and the return modulation and demodulation are not performed is achieved.
The electronic tag provided by this embodiment includes the demodulation circuit of the electronic tag of the above embodiment, and the implementation principle and technical effect of the electronic tag provided by this embodiment are similar to those of the above embodiment, and are not described here again.
It is to be noted that the foregoing is only illustrative of the preferred embodiments of the present invention and the technical principles employed. It will be understood by those skilled in the art that the present invention is not limited to the particular embodiments described herein, but is capable of various obvious changes, rearrangements and substitutions as will now become apparent to those skilled in the art without departing from the scope of the invention. Therefore, although the present invention has been described in greater detail by the above embodiments, the present invention is not limited to the above embodiments, and may include other equivalent embodiments without departing from the spirit of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims (10)
1. A demodulation circuit of an electronic tag, the electronic tag comprising an antenna module, characterized in that the demodulation circuit comprises: the device comprises an amplitude modulation module, a modulation depth clamping module, a switch module, a clock detection module and a digital processing module;
the control end of the amplitude modulation module is electrically connected with the output end of the digital processing module and is used for receiving the modulation signal output by the digital processing module so as to perform amplitude modulation on the waveform of the antenna module;
the modulation depth clamping module is connected between the amplitude modulation module and the antenna module and is used for clamping the waveform of the antenna module;
the control end of the switch module is electrically connected with the antenna module, the first end of the switch module is electrically connected with the input end of the clock detection module, and the second end of the switch module is connected with a reference signal;
the input end of the clock detection module is connected with a pull-up level signal, the output end of the clock detection module is electrically connected with the input end of the digital processing module, and the clock detection module is used for outputting a demodulation signal according to a signal input by the input end of the clock detection module;
the output end of the digital processing module is electrically connected with the control end of the amplitude modulation module, and the digital processing module is used for inputting the demodulation signal according to the input end of the digital processing module and continuously or stopping outputting the modulation signal.
2. The demodulation circuit of the electronic tag according to claim 1, wherein the modulation depth clamping module comprises a first modulation depth clamping unit; a first end of the first modulation depth clamping unit is electrically connected with the antenna module, a control end of the first modulation depth clamping unit is electrically connected with a first end of the first modulation depth clamping unit, and a second end of the first modulation depth clamping unit is electrically connected with a first end of the amplitude modulation module; and the second end of the amplitude modulation module is accessed to the reference signal.
3. The demodulation circuit of the electronic tag according to claim 2, wherein the switching module includes a first switching unit; the control end of the first switch unit is electrically connected with the antenna module, the first end of the first switch unit is electrically connected with the input end of the clock detection module, and the second end of the first switch unit is connected to the reference signal.
4. The demodulation circuit of the electronic tag according to claim 3, wherein the clock detection module comprises a first clock detection unit; the input end of the first clock detection unit is electrically connected with the first output end of the first switch unit, and the output end of the first clock detection unit is electrically connected with the input end of the digital processing module.
5. The electronic tag demodulation circuit of claim 1 wherein the antenna module comprises a first antenna element and a second antenna element in a differential configuration; the modulation depth clamping module comprises a first modulation depth clamping unit and a second modulation depth clamping unit; a first end of the first modulation depth clamping unit is electrically connected with the first antenna unit, a control end of the first modulation depth clamping unit is electrically connected with a first end of the first modulation depth clamping unit, and a second end of the first modulation depth clamping unit is electrically connected with a first end of the amplitude modulation module; the first end of the second modulation depth clamping unit is electrically connected with the second antenna unit, the control end of the second modulation depth clamping unit is electrically connected with the first end of the second modulation depth clamping unit, and the third end of the second modulation depth clamping unit is electrically connected with the second end of the amplitude modulation module.
6. The demodulation circuit of the electronic tag according to claim 5, wherein the switching module includes a first switching unit and a second switching unit; the control end of the first switch unit is electrically connected with the first antenna unit, the first end of the first switch unit is electrically connected with the first input end of the clock detection module, and the second end of the first switch unit is electrically connected with the second antenna unit; the control end of the second switch unit is electrically connected with the second antenna unit, the first end of the second switch unit is electrically connected with the second input end of the clock detection module, and the second end of the second switch unit is electrically connected with the first antenna unit.
7. The demodulation circuit of claim 6, wherein the clock detection module comprises a first clock detection unit and a second clock detection unit, an input end of the first clock detection unit is electrically connected with a first end of the first switch unit, and an output end of the first clock detection unit is electrically connected with an input end of the digital processing module; the input end of the second clock detection unit is electrically connected with the first end of the second switch unit, and the output end of the second clock detection unit is electrically connected with the input end of the digital processing module.
8. The demodulation circuit of an electronic tag according to claim 1, further comprising: a hysteresis module;
the first end of the hysteresis module is electrically connected with the power supply, the second end of the hysteresis module is electrically connected with the input end of the clock detection module, and the control end of the hysteresis module is electrically connected with the output end of the clock detection module and used for increasing the conduction voltage of the switch module when the control end of the hysteresis module receives the demodulation signal.
9. The demodulation circuit of an electronic tag according to claim 1, further comprising: an amplitude clamping module;
the first end of the amplitude clamping module is electrically connected with the antenna module, the second end of the amplitude clamping module is electrically connected with the control end of the switch module, and the third end of the amplitude clamping module is connected to the reference signal and is used for clamping the waveform of the antenna module.
10. An electronic tag, characterized in that it comprises the electronic tag's demodulation circuit of any one of claims 1-9, and further comprises an antenna module.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN114219058A (en) * | 2021-11-25 | 2022-03-22 | 深圳市芯生半导体有限公司 | Radio frequency analog circuit and electronic tag |
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| 刘鹏志: "基于IR-UWB的RFID芯片模拟电路设计", 中国优秀硕士学位论文全文数据库 (信息科技辑) * |
| 李建;曾辉;王颖;何珠玉;朱学勇;文光俊;: "UHF RFID标签芯片模拟射频前端设计", 现代电子技术, no. 06 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114219058A (en) * | 2021-11-25 | 2022-03-22 | 深圳市芯生半导体有限公司 | Radio frequency analog circuit and electronic tag |
| CN114219058B (en) * | 2021-11-25 | 2024-06-11 | 深圳市芯生半导体有限公司 | Radio frequency analog circuit and electronic tag |
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