CN112420826B - Vertical pHEMT transistor structure and switch chip - Google Patents

Abstract

The invention discloses a vertical pHEMT transistor structure and a switch chip. The transistor includes: the buffer layer, the channel layer, the first isolation layer and the barrier layer are sequentially arranged from the inner layer to the outer layer around the metalized through hole, the buffer layer, the channel layer, the first isolation layer and the barrier layer are all in a columnar structure, the axial direction of the metalized through hole is in the same direction as the normal line of the substrate, a source electrode, a grid electrode and a drain electrode are respectively arranged on the side wall of the barrier layer, the source electrode, the grid electrode and the drain electrode are horizontally or vertically arranged, and when the metalized through hole is vertically arranged, the grid electrode surrounds the columnar side wall for one circle. The switch chip is formed by connecting a plurality of vertical pHEMT transistors in series or in parallel in the vertical direction. The transistor and the switch chip have the characteristics of high isolation, large power capacity, small volume, good integration, low power consumption, high efficiency and good broadband characteristics.

Description

Vertical pHEMT transistor structure and switch chip

technical field

The invention relates to the field of semiconductor chips, in particular to a vertical pHEMT transistor structure and a switch chip formed by a vertical pHEMT transistor stack structure.

Background technique

Microwave switches are widely used in modern communication systems such as transceiver modules. There are two types of microwave switches: one is a mechanical switch, which uses electricity to control the on-off of the mechanical arm to control the on-off of the microwave channel; the other is a chip switch, which uses electricity to control the on-off of the transistor in the chip to control the on-off of the microwave channel. switch.

Compared with chip switches, mechanical switches have the advantages of high isolation, which can reach more than 60dB isolation, while chip switches can only reach about 20dB. Therefore, mechanical switches are widely used in instrumentation and other fields that require high isolation, high sensitivity, and precision measurement.

The advantages of chip switches compared to mechanical switches: small size, easy integration, and fast switching speed. A transistor of a chip switch is only about 100 microns in size, which is convenient for cascading multiple switches on the chip, as well as integrating with other control circuits and microwave circuits. Mechanical switches cannot do this. And because the chip switch is an electronic control chip transistor on and off to realize the microwave switch function, the speed is much higher than that of the mechanical switch. Mechanical switch switching takes about 100ms, while chip switches can achieve switching speeds within 10ms. Therefore, chip switches are widely used in modern communication systems that require high volume and integration, such as multi-channel transceiver chips/modules, 5G, and Wifi.

Chip switches can be implemented on various types of chips with different substrates, such as GaAs, GaN, InP, bulk silicon CMOS-RF, SOI-RF and other types. The chip switch of the new structure also includes a microelectromechanical system MEMS chip switch.

Except for MEMS chip switches, other microwave switches have roughly the same structure. Typical compound semiconductor switches such as GaAs and GaN are pHEMT transistor type chip switches. The basic structure of this switch is a pHEMT transistor, which mainly includes a substrate, gate, drain, source and other structures. The typical GaAs pHEMT structure is shown in Figure 1, and the silicon-based compound semiconductor transistor is similar.

Referring to FIG. 1 , the undoped InGaAs layer and the AlGaAs layer form a heterojunction at the interface to generate a two-dimensional electron gas. The gate controls the height of the potential barrier. When the gate reaches a certain bias voltage, the two-dimensional electron gas tunnels through the potential barrier and forms a current between the source and drain stages. To prevent current leakage into the GaAs substrate, an undoped GaAs/AlGaAs superlattice buffer layer was added.

The principle of the switch chip based on the pHEMT structure transistor is that when the gate is not applied with a control voltage, the barrier of the gate prevents the two-dimensional electron gas current from the source from flowing to the drain, and the switch is in an off state. When the control voltage is applied to the gate, the potential barrier of the gate is lowered, and the two-dimensional electron gas current of the source is no longer blocked from flowing to the drain, and the switch is turned on. Because the ability of the gate control barrier to hinder the flow of two-dimensional electron gas is weaker than that of the mechanical arm of the mechanical switch, the isolation degree of the chip switch is much smaller than that of the mechanical switch, which seriously affects the application of the chip switch.

The pHEMT transistor is a planar microwave structure fabricated on a chip. The reason why it is a planar structure is mainly to facilitate the fabrication process of semiconductor chips. The structural features of the prior art are: it is a planar chip circuit, and the gates are made of multiple The fingers are inserted between the source and drain. A typical GaAs pHEMT transistor layout design is shown in Figure 2. A fully functional multi-tube stacked SPDT switch chip based on pHEMT structure transistor is usually shown in Figure 3.

The structure shown in FIG. 3 adopts a series-parallel combined multi-tube stack structure, in order to improve the overall isolation. However, in practical applications, it is found that when the stacking reaches a certain number, the isolation will no longer increase, and it can only be improved from the isolation 10dB to the isolation of about 20dB. Moreover, due to stacking, the switching power consumption will increase and the efficiency will decrease. Therefore, in practical engineering applications, less than 10 transistors are stacked in series or parallel direction.

With the development of new communication technologies such as 5G, Wifi6, CV2X, and NBIoT, the isolation requirements for chip switches are getting higher and higher. The current chip switch technology has the following shortcomings, which need to be solved urgently:

(1) A single microwave switch based on a pHEMT structure transistor, the principle is that the gate barrier controls the current on and off between the source and the drain, and there is an inherent problem of low isolation.

(2) By stacking multiple pHEMT structure transistor switches in series or in parallel, the overall isolation can be improved, at the cost of increased power consumption and reduced efficiency, and the isolation improvement is limited.

(3) The new communication system requires chip switches with higher isolation, and maintains the advantages of low power consumption and chip integration.

SUMMARY OF THE INVENTION

The purpose of the present invention is to provide a vertical pHEMT transistor structure in view of all or part of the above-mentioned problems, so as to improve the transistor isolation. Also provided is a vertical pHEMT transistor-based switch chip with high isolation, low power consumption, and high integration.

The technical scheme adopted in the present invention is as follows:

A vertical pHEMT transistor structure comprising:

Around the metallized through hole, the buffer layer, the channel layer, the first isolation layer and the barrier layer are sequentially arranged from the inner layer to the outer layer. The metallized through hole, the buffer layer, the channel layer, the first isolation layer Both the barrier layer and the barrier layer are columnar structures, the metallized through hole axis is in the direction of the normal line of the substrate, and the source electrode, the gate electrode and the drain electrode are respectively arranged on the sidewall of the barrier layer.

Further, the source electrode, gate electrode and drain electrode are arranged horizontally or vertically.

Further, the source electrode, the gate electrode and the drain electrode are arranged vertically, and the source electrode, the gate electrode and the drain electrode respectively surround a part or a circumference of the sidewall of the barrier layer. The so-called "portion" and "circle" are relative to the perimeter of the side wall cross-section, not relative to the area of the side wall.

Further, at least the gate surrounds a circumference of the sidewall of the barrier layer.

Further, the buffer layer is an undoped GaAs/AlGaAs superlattice buffer layer, the channel layer is an undoped InGaAs channel layer, the isolation layer is an undoped AlGaAs isolation layer, and the potential barrier The layer is an N-type AlGaAs barrier layer, and the source and drain electrodes are both formed by an N-type heavily doped GaAs contact layer.

Further, the columnar structure is a column or a rectangular column.

A switch chip based on vertical pHEMT transistors is formed by vertically stacking several layers of vertical pHEMT transistors. The isolation layer vertically penetrates the second isolation layer with a metallized via hole; the upper-layer transistor and the lower-layer transistor respectively adopt the above-mentioned vertical pHEMT transistor structure.

Further, the source, gate, and drain of the upper-layer transistor and the lower-layer transistor are all arranged vertically, and between the upper-layer transistor and the lower-layer transistor, the source of one and the drain of the other pass through the Metallized via connections on the second isolation layer.

Further, the source, gate, and drain of the upper transistor and the lower transistor are arranged horizontally, and between the upper transistor and the lower transistor, the corresponding electrodes pass through the corresponding metal on the second isolation layer. via connection.

To sum up, due to the adoption of the above-mentioned technical solutions, the beneficial effects of the present invention are:

1. The vertical pHEMT microwave transistor structure and switch chip of the present invention have quite high isolation. When the gate surrounds the sidewall of the columnar transistor, it has the strongest ability to control the potential barrier, and the isolation of the microwave switch on and off is the highest. Compared with the traditional horizontally arranged planar structure pHEMT microwave switch, the isolation degree of the novel columnar structure transistor proposed by the present invention can be improved by more than 3dB.

2. The center of the columnar structure transistor designed by the present invention is a metallized through hole, which is directly grounded and has good heat dissipation characteristics, and the microwave switch chip formed by this has a higher power capacity. Compared with the traditional horizontally arranged planar structure pHEMT microwave switch, the power capacity of the transistor designed by the present invention can be increased from 5W to more than 10W.

3. The transistor of the present invention adopts a vertical stacking mode. When more switches are connected in series and parallel, the area in the horizontal direction does not increase, but the height in the vertical direction increases, and the integration of the chip and the module is better. Compared with the traditional horizontally arranged planar structure pHEMT microwave switch, the area of the novel columnar structure transistor proposed by the present invention can be reduced from 1 mm ² to 0.1 mm ² .

4. Because the switch chip of the present invention has the characteristics of miniaturization and high integration, the interconnection distance between switches is shorter, and the broadband characteristics of the chip and the module can be improved, power consumption can be reduced, and efficiency can be improved, especially the design of the present invention. The new columnar structure transistor adopts metallized through-hole TSV, which further reduces the interconnection distance between switch cells. Compared with the traditional horizontally arranged planar structure pHEMT microwave switch, the broadband characteristics of the novel columnar structure transistor proposed in the present invention can cover the millimeter wave frequency band above 28GHz, the power consumption can be reduced from 1W to 0.5W, and the efficiency can be increased from 30% to 40%.

Description of drawings

The invention will be described by way of example and with reference to the accompanying drawings, in which:

Figure 1 shows the structure of a conventional GaAs pHEMT substrate.

FIG. 2 is a layout of a conventional power transistor.

FIG. 3 is a structural diagram of an existing multi-tube stacked single-pole double-throw switch chip based on a pHEMT structure transistor.

FIG. 4 is a structural diagram of a pHEMT transistor with a vertical structure in which the source, gate and drain are arranged horizontally.

FIG. 5 is a structural diagram of a pHEMT transistor with a horizontal structure in which the source, gate and drain are arranged horizontally.

FIG. 6 is a structural diagram of a series stacking structure of pHEMT transistors.

FIG. 7 is a parallel stacking structure diagram of pHEMT transistors.

Detailed ways

All features disclosed in this specification, or all disclosed steps in a method or process, may be combined in any way except mutually exclusive features and/or steps.

Any feature disclosed in this specification (including any accompanying claims, abstract), unless expressly stated otherwise, may be replaced by other equivalent or alternative features serving a similar purpose. That is, unless expressly stated otherwise, each feature is but one example of a series of equivalent or similar features.

A vertical pHEMT transistor structure comprising:

Around the metallized through hole, the buffer layer, the channel layer, the first isolation layer and the barrier layer are sequentially arranged from the inner layer to the outer layer, and the metallized through hole is axially in the same direction as the substrate normal; The wall (obviously the outside) is provided with source, gate, and drain, and the source and drain are the contact layers set on the sidewall of the barrier layer, so that the two-dimensional electron gas is distributed axially around the metallized through hole, and the gate can be The barrier layer is well controlled, the ability to control the current on and off between the source and the drain is improved, and the isolation is improved. The metallized through hole forms a columnar structure along the normal direction of the substrate. Correspondingly, the structures of the surrounding layers of the metallized through hole (the buffer layer, the channel layer, the first isolation layer and the barrier layer are all columnar structures) also form a columnar structure. , the columnar structure can be a column or a rectangular column. The source electrode, the gate electrode and the drain electrode can be arranged horizontally or vertically along the sidewall of the barrier layer. In the case of vertical arrangement, the source electrode, the gate electrode and the drain electrode may be locally arranged on the sidewall of the barrier layer, or may surround the sidewall of the barrier layer in a circle. Figure 4 shows the transistor structure with the source, gate and drain arranged horizontally. The corresponding two-dimensional electron gas current flows horizontally from the source to the drain on the sidewall of the column, as shown in Figure 5 for the source , a transistor structure in which the gate and drain are arranged vertically (partial arrangement), and the corresponding two-dimensional electron gas current flows vertically from the source to the drain on the sidewall of the column. When the gate is arranged vertically, the gate surrounds the sidewall of the column, which has the strongest control of the potential barrier and the highest isolation between the switch on and off.

The vertical pHEMT microwave transistor structures are arranged in an array along the normal direction of the substrate to form a columnar vertical pHEMT transistor.

Embodiment 2

This embodiment discloses a vertical pHEMT microwave transistor structure, and the transistor structure includes:

Around the metallized through hole, an undoped GaAs/AlGaAs superlattice buffer layer, an undoped InGaAs channel layer, an undoped AlGaAs isolation layer and an N-type AlGaAs barrier layer are sequentially arranged from the inner layer to the outer layer. The metallized through hole axis is in the same direction as the substrate normal; the source electrode, the gate electrode and the drain electrode are arranged on the sidewall of the N-type AlGaAs barrier layer, and the source electrode and the drain electrode are N-type electrodes arranged on the sidewall of the N-type AlGaAs barrier layer. The GaAs contact layer is heavily doped so that the two-dimensional electron gas is distributed axially around the metallized via. The metallized through hole forms a columnar structure along the normal direction of the substrate. Correspondingly, each layer structure around the metallized through hole also forms a columnar structure, and the columnar structure can be a cylinder or a rectangular column. The source electrode, the gate electrode and the drain electrode can be arranged horizontally or vertically along the sidewall of the N-type AlGaAs barrier layer. In the case of vertical arrangement, the source electrode, the gate electrode and the drain electrode may be locally arranged on the sidewall of the N-type AlGaAs barrier layer, or may surround the sidewall of the N-type AlGaAs barrier layer. Figure 4 shows the transistor structure with the source, gate and drain arranged horizontally, and the corresponding two-dimensional electron gas current flows horizontally from the source to the drain on the sidewall of the column, as shown in Figure 5 for the vertical arrangement The distributed transistor structure (local arrangement), the corresponding two-dimensional electron gas current flows vertically from the source to the drain on the sidewalls of the column.

Embodiment 3

This embodiment discloses a vertical stacking structure of pHEMT transistors, which is formed by vertically stacking several vertical pHEMT microwave transistor structures in the above embodiments on a substrate, and each adjacent two layers of vertical pHEMT microwave transistors includes an upper-layer transistor and a lower-layer transistor Transistor, the upper layer transistor and the lower layer transistor are vertically stacked (that is, stacked along the normal direction of the substrate), a second isolation layer is arranged between the upper layer transistor and the lower layer transistor, and a metallized via hole for electrical conduction and heat conduction is arranged vertically through the second isolation layer . The structures of the upper-layer transistor and the lower-layer transistor respectively adopt the above-mentioned pHEMT microwave transistor structure. It should be noted that although the vertical pHEMT microwave transistor structure of the above-mentioned embodiment is adopted, the structures of the upper-layer transistor and the lower-layer transistor may be the same or different. and the lower layer transistors may correspond to the vertical pHEMT microwave transistor structures of different embodiments respectively. Vertical stacking includes two cases, series stacking and parallel stacking. The series stack is shown in Figure 6, ie the drain and source connections between the upper and lower transistors. The parallel stacking is shown in Figure 7, ie the source and source connections, and the drain and drain connections between the upper and lower transistors.

As shown in Fig. 6, a structure composed of two vertical pHEMT microwave transistor structures is stacked. On the GaAs substrate, a lower layer transistor and an upper layer transistor are grown, and a second isolation layer is arranged between the upper and lower layer transistors. The second isolation layer A metallized via hole is provided through the layer. The structures of the upper and lower transistors are: around the metallized through holes, the undoped GaAs/AlGaAs superlattice buffer layer, the undoped InGaAs channel layer, and the undoped AlGaAs isolation layer are sequentially arranged from the inner layer to the outer layer. layer and N-type AlGaAs barrier layer, the metallized through hole axis is in the same direction as the substrate normal; source, gate, and drain are arranged on the sidewall of the N-type AlGaAs barrier layer, and the source, gate, and drain are along the The sidewalls of the AlGaAs barrier layers are arranged vertically (ie, horizontally) in sequence, and the drains of the upper transistors and the sources of the lower transistors are connected through metallized vias on the isolation layer, thereby realizing series stacking. In the specific implementation, the connection between the electrodes needs to be connected by gold wire/copper wire, which belongs to the common knowledge in the art, and will not be explained in detail here. The present invention mainly introduces the columnar transistor structure and the corresponding vertical stack structure.

As shown in Figure 7, the structure of two vertical pHEMT microwave transistor structures is stacked. On the GaAs substrate, a lower layer transistor and an upper layer transistor are grown, and a second isolation layer is arranged between the upper and lower layer transistors. The second isolation layer A metallized via hole is provided through the layer. The structures of the upper and lower transistors are: around the metallized through holes, the undoped GaAs/AlGaAs superlattice buffer layer, the undoped InGaAs channel layer, and the undoped AlGaAs isolation layer are sequentially arranged from the inner layer to the outer layer. layer and N-type AlGaAs barrier layer, the metallized through hole axis is in the same direction as the substrate normal; source, gate, and drain are arranged on the sidewall of the N-type AlGaAs barrier layer, and the source, gate, and drain are along the The sidewalls of the AlGaAs barrier layer are arranged horizontally (ie, vertically), the drain of the upper transistor and the drain of the lower transistor, the gate of the upper transistor and the gate of the lower transistor, the source of the upper transistor and the source of the lower transistor Between the poles, they are respectively connected through the corresponding metallized vias on the isolation layer, so as to realize parallel stacking.

This embodiment is only an example of vertical stacking. In practical applications, for different transistors, the materials selected for each layer (buffer layer, channel layer, isolation layer and barrier layer) will be different, but the structure is the same of.

The present invention is not limited to the foregoing specific embodiments. The present invention extends to any new features or any new combination disclosed in this specification, as well as any new method or process steps or any new combination disclosed.

Claims (9)

1. A vertical pHEMT transistor structure comprising:

the buffer layer, the channel layer, the first isolation layer and the barrier layer are sequentially arranged from the inner layer to the outer layer around the metalized through hole, the buffer layer, the channel layer, the first isolation layer and the barrier layer are all of a columnar structure, the axial direction of the metalized through hole is the same as the normal direction of the substrate, and a source electrode, a grid electrode and a drain electrode are respectively arranged on the side wall of the barrier layer.

2. The vertical pHEMT transistor structure of claim 1, wherein the source, gate, and drain are arranged horizontally or vertically.

3. The vertical pHEMT transistor structure of claim 2, wherein the source, gate, and drain are vertically arranged, and the source, gate, and drain respectively surround a portion or a perimeter of a sidewall of the barrier layer.

4. The vertical pHEMT transistor structure of claim 3, in which at least the gate surrounds a perimeter of the barrier layer sidewalls.

5. The vertical pHEMT transistor structure of claim 1, wherein the buffer layer is an undoped GaAs/AlGaAs superlattice buffer layer, the channel layer is an undoped InGaAs channel layer, the isolation layer is an undoped AlGaAs isolation layer, the barrier layer is an N-type AlGaAs barrier layer, and the source and drain are both formed from N-type heavily doped GaAs contact layers.

6. The vertical pHEMT transistor structure of any one of claims 1 to 5, wherein the columnar structure is a cylindrical or rectangular column.

7. A switch chip based on vertical pHEMT transistors is characterized in that the switch chip is formed by vertically stacking a plurality of layers of vertical pHEMT transistors, each two adjacent layers of vertical pHEMT transistors comprise an upper layer transistor and a lower layer transistor, a second isolation layer is arranged between the upper layer transistor and the lower layer transistor, and metalized through holes vertically penetrate through the second isolation layer; the upper layer transistor and the lower layer transistor respectively adopt the vertical pHEMT transistor structure as claimed in any one of claims 1-5.

8. The vertical pHEMT transistor based switch chip of claim 7, wherein the source, gate, and drain of the upper and lower transistors are in a vertical arrangement, and wherein the source of one and the drain of the other are connected between the upper and lower transistors by a metalized via on the second isolation layer.

9. The vertical pHEMT transistor-based switch chip of claim 7, wherein the sources, gates, and drains of the upper and lower transistors are arranged horizontally, and corresponding electrodes between the upper and lower transistors are connected by corresponding metallized vias in the second isolation layer.

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