CN112420541B - Method for monitoring source drain annealing process of wafer product - Google Patents
Method for monitoring source drain annealing process of wafer product Download PDFInfo
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- CN112420541B CN112420541B CN202011291535.0A CN202011291535A CN112420541B CN 112420541 B CN112420541 B CN 112420541B CN 202011291535 A CN202011291535 A CN 202011291535A CN 112420541 B CN112420541 B CN 112420541B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/10—Measuring as part of the manufacturing process
- H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
- H01L22/26—Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement
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- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The invention discloses a monitoring method of a source drain annealing process of a wafer product, which comprises the following steps: firstly, arranging a plurality of test units on a current wafer, and completing source-drain injection of wafer products on the current wafer, wherein the source-drain injection is also injected into the test units at the same time; step two, forming a layer of stress silicon nitride by adopting a stress memorization technology; step three, performing a source drain annealing process; step four, removing the stress silicon nitride layer; step five, testing square resistances of a plurality of test units, forming distribution in square resistance surfaces of the test units on the current wafer, and further obtaining distribution of source drain annealing processes in a current wafer temperature surface on the current wafer; and step six, adjusting the source and drain annealing process of the wafer product according to the current wafer temperature in-plane distribution so as to improve the uniformity of the next wafer temperature in-plane distribution. The invention can monitor the temperature in-plane distribution of the source-drain annealing process in time, can improve the resistance and the uniformity of working current of the wafer product, and can improve the yield of the wafer product.
Description
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a monitoring method of a wafer product source drain annealing process.
Background
The wafer product is a product formed by semiconductor devices formed on a wafer, and a source-drain annealing process is required after source-drain injection of the semiconductor devices is completed, wherein the source-drain annealing process can influence the conductivity of a formed source region and a formed drain region, and finally can influence the resistance of the devices, namely source-drain resistance and working current; meanwhile, when the Stress Memorization Technology (SMT) is combined, after the injection of the source and the drain is completed, stress silicon nitride adopting the SMT is formed first, and then a source and drain annealing process is performed, wherein the source and drain annealing process also transfers the stress of the stress silicon nitride to a source region, a drain region and a grid structure so as to influence the stress of a channel region, and the change of the stress of the channel region also influences the working current of a device. It is known that the source drain annealing process affects the resistance and the operating current of the device. However, since the size of the wafer is generally larger, the process conditions of each region often have differences, for example, the actual temperatures reached by the same source-drain annealing process parameters in different regions of the wafer have certain deviations, and finally, the resistance and the working current of the wafer product after the source-drain annealing process may be uneven in-plane distribution.
In the prior art, the resistance and the uniformity of the working current during the source/drain annealing process of the wafer product are monitored by a direct probe characterization method (DPCV) or a Wafer Acceptance Test (WAT). When the resistance and the working current uniformity of the wafer measured by a direct probe characterization method or an acceptable test are problematic, the annealing temperature of the source drain annealing process is adjusted to ensure the uniformity of the saturated working current. However, the time required from the source and drain annealing process to the final acceptable test of the wafer product is not real-time feedback adjustment. That is, when DPCV and WAT tests are performed, all the processes of the wafer products need to be completed on the wafer, and when one wafer completes all the processes, the subsequent wafers already complete the source-drain annealing process, so that when DPCV and WAT tests find problems, many wafers complete the source-drain annealing process, which causes the same problem for many wafer products on many wafers, and finally, the yield of the products is affected.
Disclosure of Invention
The invention aims to provide a monitoring method for a source-drain annealing process of a wafer product, which can monitor the temperature in-plane distribution of the source-drain annealing process in real time and adjust the temperature in-plane distribution of the source-drain annealing process in time after the source-drain annealing process is completed, so that the uniformity of the distribution in the next wafer temperature in-plane can be improved, and finally, the resistance and the uniformity of working current of the wafer product can be improved, and the yield of the wafer product can be improved.
In order to solve the technical problems, the method for monitoring the wafer product source drain annealing process provided by the invention comprises the following steps:
Step one, arranging a plurality of test units on a current wafer, and completing source-drain injection of wafer products on the current wafer, wherein the source-drain injection is also simultaneously injected into the test units.
And secondly, forming a layer of stress silicon nitride on the surface of the current wafer by adopting a stress memory technology.
And thirdly, carrying out a source drain annealing process of the wafer product on the current wafer.
And step four, removing the stress silicon nitride layer on the current wafer.
And fifthly, testing the square resistance of each test unit, forming the distribution of the square resistance of the test unit on the current wafer in the plane, and distributing the source drain annealing process of the wafer product in the current wafer temperature on the current wafer through the distribution of the square resistance of the test unit in the plane.
And step six, adjusting the source and drain annealing process of the wafer product according to the distribution in the current wafer temperature plane so as to improve the uniformity of the distribution in the next wafer temperature plane.
The wafer product is produced on a plurality of wafers, and after the step six is completed, the next wafer is used as the current wafer, and the steps one to six are repeated.
A further improvement is that the current wafer is composed of a semiconductor substrate, and the next wafer is identical to the current wafer.
A further improvement is that the semiconductor substrate comprises a silicon substrate.
A further improvement is that the semiconductor device of the wafer product comprises a logic device or a memory device.
The semiconductor device comprises a grid structure, wherein source and drain injection is self-aligned to form a source region and a drain region at two sides of the grid structure; a channel region is located before the source region and the drain region and is covered by the gate structure.
The grid structure comprises a grid dielectric layer and a grid conductive material layer which are sequentially overlapped.
The further improvement is that the gate dielectric layer is a gate oxide layer or the gate dielectric layer is a high dielectric constant layer.
A further improvement is that the gate conductive material layer is a polysilicon gate or a metal gate.
In a fifth step, the square resistance of the test unit is measured by a four-probe method.
The testing unit is arranged on the dicing tape of the current wafer.
Further, the width of the dicing tape is 65 μm or more.
A further improvement is that the size of each test unit is greater than or equal to 3mm x 65 μm.
A further improvement is that the test units are uniformly distributed on the current wafer.
Further improvements are that the distribution positions of the test units on the current wafer comprise an upper part, a lower part, a left part, a right part and a middle part.
The number of the test units on the current wafer is more than or equal to 10.
Further improvements are that the technology nodes of the semiconductor device include 32nm, 28nm, 22nm and below 20 nm.
In the third step, the temperature of the source and drain annealing process of the wafer product is 900-1060 ℃, and the annealing mode comprises peak annealing and uniform temperature annealing.
According to the invention, the test unit is arranged on the current wafer, and the sheet resistance of the test unit can be tested after the source-drain annealing process is finished, so that the sheet resistance in-plane distribution of the test unit can be obtained, and the current wafer temperature in-plane distribution on the current wafer can be obtained, therefore, the source-drain annealing process of a wafer product can be timely adjusted after the source-drain annealing process is finished, that is, the source-drain annealing process of the wafer product can be adjusted before the source-drain annealing process of the next wafer is carried out, the temperature uniformity distribution uniformity of the source-drain annealing process of the subsequent wafer can be improved, and the resistance and the working current uniformity of the wafer product produced on the subsequent wafer can be further improved, so that the product yield can be improved.
The invention can also monitor each wafer, namely, the steps one to six are circulated when the next wafer is subjected to the source-drain annealing process, so that the source-drain annealing process of all wafers except the first wafer can be well regulated, and the resistance and the uniformity of working current of the same wafer product such as the resistance and the uniformity of working current among different batches (lot) of wafers in the same batch and wafers in the same wafer can be improved to the greatest extent.
Drawings
The invention is described in further detail below with reference to the attached drawings and detailed description:
FIG. 1 is a flow chart of a method for monitoring a source drain annealing process of a wafer product according to an embodiment of the present invention;
FIG. 2 is a diagram showing the distribution of exposure units and dies of a current wafer in an embodiment of the invention;
FIG. 3 is a block diagram of a dicing tape and test unit according to an embodiment of the invention.
Detailed Description
FIG. 1 is a flowchart of a method for monitoring a source/drain annealing process of a wafer product according to an embodiment of the present invention; as shown in fig. 2, the distribution diagram of the exposure unit and the bare chip of the current wafer 101 in the embodiment of the invention is shown; FIG. 3 is a block diagram of a dicing tape and test unit according to an embodiment of the invention; the monitoring method of the source drain annealing process of the wafer product comprises the following steps:
Step one, a plurality of test units 2 are arranged on a current wafer 101, and source and drain injection of wafer products is completed on the current wafer 101, wherein the source and drain injection is also simultaneously injected into the test units 2.
In the embodiment of the present invention, the test unit 2 is disposed on the dicing tape of the current wafer 101. As can be seen from fig. 3, the test unit 2 is arranged on the dicing tape 1.
The width of the cutting band is 65 μm or more.
The size of each test unit 2 is 3mm x 65 μm or more.
The test units 2 are uniformly distributed on the current wafer 101. The distribution positions of the test units 2 on the current wafer 101 include an upper portion, a lower portion, a left portion, a right portion, and a middle portion. The number of the test units 2 on the current wafer 101 is greater than or equal to 10.
And secondly, forming a layer of stress silicon nitride on the surface of the current wafer 101 by adopting a stress memory technology.
And thirdly, performing a source drain annealing process of the wafer product on the current wafer 101.
In the embodiment of the invention, the temperature of the source and drain annealing process of the wafer product is 900-1060 ℃, and the annealing mode comprises peak annealing and uniform temperature annealing.
And step four, removing the stress silicon nitride layer on the current wafer 101.
And fifthly, testing the square resistances of the test units 2, forming the square resistance in-plane distribution of the test units 2 on the current wafer 101, and obtaining the source and drain annealing process distribution of the wafer product in the current wafer 101 temperature in-plane distribution of the current wafer 101 through the square resistance in-plane distribution of the test units 2.
In the embodiment of the invention, the square resistance of the test unit 2 is measured by a four-probe method.
And step six, adjusting the source and drain annealing process of the wafer product according to the distribution in the current wafer 101 temperature plane so as to improve the uniformity of the distribution in the next wafer temperature plane.
More preferably, the same wafer product is produced on a plurality of wafers, and after the step six is completed, the step one to the step six are repeated with the next wafer as the current wafer 101.
In the embodiment of the present invention, the current wafer 101 is composed of a semiconductor substrate, and the next wafer is the same as the current wafer 101.
The semiconductor substrate includes a silicon substrate.
The semiconductor device of the wafer product includes a logic device or a memory device. The technology nodes of the semiconductor device comprise 32nm, 28nm, 22nm and below 20nm. As shown in fig. 2, the chips 102 corresponding to the wafer products are integrated on the current wafer 101, and a dicing tape 1 is disposed between the chips 102, so that each individual chip 102 is obtained after the wafer 101 is diced. Because of the large area of the current wafer 101, multiple exposures are typically required to expose the semiconductor devices of all wafer products on the current wafer 101.
The semiconductor device comprises a grid structure, wherein source and drain injection self-aligned to form a source region and a drain region at two sides of the grid structure; a channel region is located before the source region and the drain region and is covered by the gate structure.
The grid structure comprises a grid dielectric layer and a grid conductive material layer which are sequentially overlapped.
The gate dielectric layer is a gate oxide layer or a high dielectric constant layer.
The gate conductive material layer is a polysilicon gate or a metal gate.
According to the embodiment of the invention, the test unit 2 is arranged on the current wafer 101, and the sheet resistance of the test unit 2 can be tested to obtain the sheet resistance in-plane distribution of the test unit 2 and further obtain the temperature in-plane distribution of the current wafer 101 on the current wafer 101 after the source and drain annealing process is finished, so that the source and drain annealing process of a wafer product can be timely adjusted, that is, the source and drain annealing process of the wafer product can be adjusted before the next wafer is subjected to the source and drain annealing process, the temperature uniformity distribution uniformity of the source and drain annealing process of the subsequent wafer can be improved, and the resistance and the working current uniformity of the wafer product produced on the subsequent wafer can be further improved, and the product yield can be improved.
The embodiment of the invention can also ensure that the source and drain annealing processes of all wafers except the first wafer are well adjusted by monitoring each wafer, namely, the steps one to six are also circulated when the next wafer is subjected to the source and drain annealing process, and can furthest improve the resistance and the uniformity of working current of the same wafer product, such as the resistance and the uniformity of working current of different wafers in different batches (lot), the uniformity of the working current of different wafers in the same batch and the uniformity of the wafer product in the same wafer.
The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.
Claims (18)
1. The monitoring method of the wafer product source drain annealing process is characterized by comprising the following steps of:
firstly, arranging a plurality of test units on a current wafer, and completing source-drain injection of wafer products on the current wafer, wherein the source-drain injection is also simultaneously injected into the test units;
The test unit is arranged on the dicing tape of the current wafer;
step two, forming a layer of stress silicon nitride on the surface of the current wafer by adopting a stress memory technology;
step three, carrying out a source drain annealing process of the wafer product on the current wafer;
step four, removing the stress silicon nitride layer on the current wafer;
Step five, testing the square resistance of each test unit, forming the distribution in the square resistance surface of the test unit on the current wafer, and distributing the source drain annealing process of the wafer product in the current wafer temperature surface of the current wafer through the distribution in the square resistance surface of the test unit;
And step six, adjusting the source and drain annealing process of the wafer product according to the distribution in the current wafer temperature plane so as to improve the uniformity of the distribution in the next wafer temperature plane.
2. The method for monitoring a source drain annealing process of a wafer product according to claim 1, wherein: and (3) producing the same wafer product on a plurality of wafers, and repeating the steps one to six by taking the next wafer as the current wafer after the step six is completed.
3. The method for monitoring a source drain annealing process of a wafer product according to claim 2, wherein: the current wafer is composed of a semiconductor substrate, and the next wafer is identical to the current wafer.
4. The method for monitoring a source drain annealing process of a wafer product according to claim 3, wherein: the semiconductor substrate includes a silicon substrate.
5. The method for monitoring a source drain annealing process of a wafer product according to claim 4, wherein: the semiconductor device of the wafer product includes a logic device or a memory device.
6. The method for monitoring a source drain annealing process of a wafer product according to claim 5, wherein: the semiconductor device comprises a grid structure, wherein source and drain injection self-aligned to form a source region and a drain region at two sides of the grid structure; a channel region is located between the source region and the drain region and is covered by the gate structure.
7. The method for monitoring a source drain annealing process of a wafer product according to claim 6, wherein: the grid structure comprises a grid dielectric layer and a grid conductive material layer which are sequentially overlapped.
8. The method for monitoring a source drain annealing process of a wafer product according to claim 7, wherein: the gate dielectric layer is a gate oxide layer.
9. The method for monitoring a source drain annealing process of a wafer product according to claim 7, wherein: the gate dielectric layer is a high dielectric constant layer.
10. The method for monitoring a source drain annealing process of a wafer product according to claim 7, wherein: the gate conductive material layer is a polysilicon gate or a metal gate.
11. The method for monitoring a source drain annealing process of a wafer product according to claim 1, wherein: and fifthly, measuring the square resistance of the test unit by adopting a four-probe method.
12. The method for monitoring a source drain annealing process of a wafer product according to claim 1, wherein: the width of the cutting band is 65 μm or more.
13. The method for monitoring a source drain annealing process of a wafer product according to claim 12, wherein: the size of each test unit is more than or equal to 3mm x 65 mu m.
14. The method for monitoring a source drain annealing process of a wafer product according to claim 1, wherein: the test units are uniformly distributed on the current wafer.
15. The method for monitoring a source drain annealing process of a wafer product according to claim 14, wherein: the distribution positions of the test units on the current wafer comprise an upper part, a lower part, a left part, a right part and a middle part.
16. The method for monitoring a source drain annealing process of a wafer product according to claim 14 or 15, wherein: and the number of the test units on the current wafer is more than or equal to 10.
17. The method for monitoring a source drain annealing process of a wafer product according to claim 5, wherein: the technology nodes of the semiconductor device comprise 32nm, 28nm, 22nm and below 20nm.
18. The method for monitoring a source drain annealing process of a wafer product according to claim 1, wherein: in the third step, the temperature of the source and drain annealing process of the wafer product is 900-1060 ℃.
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