CN112420499B - Patterned aluminum oxide dielectric layer and gate, its preparation method and application - Google Patents

Abstract

The invention discloses a patterned alumina dielectric layer and a grid based on screen printing, a preparation method and application thereof, wherein the preparation method comprises the following steps: immersing the alumina dielectric layer with limited growth in isopropanol, ultrasonically treating for 5-10 minutes, drying, silk-screen printing a layer of photoresist as an anti-corrosion layer on the alumina dielectric layer by adopting a silk-screen printing method, and curing for 1-2 minutes; and putting the obtained substrate into etching liquid until the alumina dielectric layer which is not covered by the anti-corrosion layer is etched, and cleaning the anti-corrosion layer to obtain the patterned alumina dielectric layer and the grid electrode. The preparation method provided by the invention is simple to operate, the patterned alumina dielectric layer and the grid electrode can be obtained by only two steps, various patterns can be simply and quickly obtained by adopting a screen printing method to print the anti-corrosion layer, better conditions are provided for subsequent circuit design, and the method can be used for preparing complex circuits without the complex operation and time consumption like the traditional photoetching and etching patterning technology.

Description

Patterned aluminum oxide dielectric layer and gate, its preparation method and application

technical field

The invention belongs to the technical field of semiconductor thin film transistor preparation, and in particular relates to a patterned aluminum oxide dielectric layer and grid based on screen printing and a preparation method and application thereof.

Background technique

In recent years, thin film transistors (TFT) have become the core components of display drive backplanes in the flat panel display industry. With the development of large-scale integrated circuit technology, the device size, including the thickness of the dielectric layer, is getting smaller and smaller, and its reduction trend follows Moore's Law. However, in TFT devices, the dielectric layer is mostly based on silicon oxide material. As the thickness of silicon oxide decreases, the leakage current of the dielectric layer will gradually increase, causing high energy consumption and heat dissipation problems of the device. In order to solve related problems, a dielectric layer with high dielectric constant (high k) will be used instead of silicon oxide to reduce gate leakage current and increase capacitance density, so a new type of high k dielectric that can replace silicon oxide is prepared Layer is the primary task to further improve the performance and integration of integrated circuits. At present, the high-k materials that have become research hotspots include AlO _x , ZrO ₂ , HfO ₂ and so on. The common method for preparing such metal oxides is the sol-gel method or physical vapor deposition method. The organic substances used in this method are generally flammable, toxic and require a high temperature (over 400°C) during preparation. Facilitate the realization of flexible circuits. As an active metal, aluminum can also be electrochemically processed at room temperature to obtain an alumina dielectric layer compared to other materials and methods. The preparation of an alumina dielectric layer by electrochemical anodization is simple and does not require high temperature heating. Low cost, suitable for mass production. However, the existing anodic aluminum oxide growth technology makes aluminum oxide completely cover the surface of aluminum. In order to realize the construction of complex circuits, it is necessary to perform secondary patterned etching on aluminum oxide. Because the chemical properties of alumina and aluminum are similar, etching alumina alone requires a complex protection process, which greatly increases the preparation cost and limits the advantages of the anodic alumina method.

In addition, semiconductor manufacturing is divided into wafer manufacturing and integrated circuit manufacturing. Patterning technology is an essential part of integrated circuit manufacturing. Commonly used patterning technologies include photolithography development and etching processes. The film pattern is complicated to operate and requires a series of operations such as pre-treatment, glue leveling, pre-baking, alignment exposure, development, and post-baking, which brings a series of problems such as high energy consumption, high pollution, and high cost. How to replace the photolithography process with a low-cost method for patterning has become a difficult problem.

Contents of the invention

Aiming at the deficiencies of the prior art, the object of the present invention is to provide a method for preparing a confinement-growth aluminum oxide dielectric layer with a common gate contact site, which realizes the oxidation of patterned confinement growth in the anodic oxidation process Aluminum dielectric layer (aluminum oxide) to create gate connection sites in integrated circuits based on anodized aluminum oxide TFTs without secondary etching of the aluminum oxide.

Another object of the present invention is to provide a confinement-grown alumina dielectric layer obtained by the above preparation method.

Another object of the present invention is to provide an application of the above-mentioned confinement-grown aluminum oxide dielectric layer in a field effect transistor.

Another object of the present invention is to provide a method for preparing a patterned aluminum oxide dielectric layer and a grid based on screen printing.

Another object of the present invention is to provide the patterned aluminum oxide dielectric layer and gate obtained by the above preparation method.

Another object of the present invention is to provide the application of the above-mentioned patterned aluminum oxide dielectric layer and gate in a field effect transistor.

The purpose of the present invention is achieved through the following technical solutions.

A method for preparing a confinement-grown aluminum oxide dielectric layer with a common gate contact site, comprising the following steps:

1) Vacuum deposition grid:

After cleaning the substrate, drying the substrate, vapor-depositing a layer of aluminum film with a thickness of 70-150 nm on the substrate as a grid;

In said step 1), the method of drying the substrate is blowing dry with nitrogen.

In the step 1), the substrate is a rigid substrate or a flexible substrate, the rigid substrate is a quartz plate or a glass slide, and the flexible substrate is polyethylene naphthalate (PEN) or polymethyl Methyl acrylate (PMMA).

In the step 1), the purity of the nitrogen is 99.999%.

2) Print a layer of photoresist material on the aluminum film as a mask by screen printing, and cure for 1-2 minutes;

In the step 2), the screen printing method adopts a screen of 300-500 mesh, and the moving speed of the scraper during screen printing is 5-20 mm/s.

In the step 2), the pattern of the mask is a rectangular photoresist material layer arranged in a rectangular matrix, and the size of the rectangular photoresist material layer is 300 μm×300 μm.

In the step 2), the photoresist material is a positive photoresist material or a negative photoresist material.

In the step 2), the curing temperature is 40-80°C.

3) Electrochemical anodizing:

Using the substrate as an anode, using a conductive material as a cathode, immersing the anode and the cathode in an electrolyte, applying a constant current between the anode and the cathode, so that the aluminum not covered by the mask in step 2) The film is oxidized to form aluminum oxide, and the mask is washed off with an organic solvent to obtain a limited-growth aluminum oxide dielectric layer.

In the step 3), the conductive material is Pt, Au or graphite.

In the step 3), the density of the constant current is 0.007-0.07 mA/cm ² .

In the step 3), the organic solvent is isopropanol, ethanol or dichloromethane.

Application of the above-mentioned confinement-grown aluminum oxide dielectric layer in a field-effect transistor.

In the above technical scheme, a layer of organic film is covered on the aluminum oxide dielectric layer of the confinement-grown alumina dielectric layer, and then a mask plate is pasted on the organic film, and a silver layer is vacuum evaporated. As source and drain electrodes, field effect transistors were obtained.

In the above technical scheme, a mask plate is pasted on the aluminum oxide dielectric layer of confinement growth, organic matter is vacuum evaporated to form an organic film, and a mask plate is pasted, and a silver layer is vacuum evaporated as a source electrode and drain electrode to obtain a field effect transistor.

In the above technical solution, the material of the organic thin film is C8-BTBT or C10-DNTT.

In the above technical solution, the mobility of the field effect transistor is 2.6-3 cm ² /(v*s) ^-1 , and the on-off ratio is 10 ⁵ -10 ⁷ .

The beneficial effect of the preparation method of the aluminum oxide dielectric layer of confined growth of the present invention is as follows:

1. Choosing alumina growth based on anodic oxidation can avoid the high-temperature heating requirements required for thermal growth or solvent-gel method and physical vapor deposition, reduce production costs, and facilitate large-scale production.

2. Based on the preparation method of the present invention, the common gate connection site in the circuit and the aluminum oxide dielectric layer of patterned confinement growth are easy to operate, and there is no need for secondary patterned etching of aluminum oxide, because aluminum oxide and The chemical properties of aluminum are close. If the aluminum oxide is etched alone, a complex protection process is required, which greatly increases the production cost. Compared with the method of using thermally grown alumina and performing secondary etching, the alumina obtained by the preparation method of the present invention The leakage current density is low and the variation range is small, showing that its performance is stable and excellent.

3. The surface roughness of the aluminum oxide dielectric layer obtained by the present invention is lower than 2nm, and the surface is smooth, which provides an excellent contact interface for subsequent transistor preparation and is beneficial to obtain better device properties.

4. The substrate can be either a rigid substrate or a flexible substrate, so that a rigid device or a flexible device can be prepared. When a flexible substrate is used, electronic skin and flexible devices can be fabricated.

5. The steps of the preparation method of the present invention are simple, and the gate connection sites required for the preparation of circuits are obtained, which can form complex logic circuits, such as inverters and flip-flops.

A method for preparing a patterned aluminum oxide dielectric layer and grid based on screen printing, comprising the following steps:

a) Immerse the confined-growth alumina dielectric layer in isopropanol, sonicate for 5-10 minutes, dry, and screen-print a layer of photoresist on the alumina dielectric layer by screen printing The glue is used as a resist layer and cured for 1-2 minutes;

In the step a), the drying is blown dry with nitrogen.

In the step a), the purity of the nitrogen is 99.999%, the screen printing method adopts a screen of 300-500 mesh, and the moving speed of the scraper during screen printing is 5-20mm/s .

In the step a), the photoresist is a positive photoresist material or a negative photoresist material.

In the step a), the curing temperature is 40-80°C.

In the step a), the pattern of the resist layer is a photoresist layer arranged in a rectangular matrix, and the size of the photoresist layer is 700 μm×700 μm.

b) Put the substrate obtained in step a) into an etching solution until the aluminum oxide dielectric layer not covered by the resist layer is etched away, and then clean the resist layer to obtain a patterned aluminum oxide dielectric layer and gate pole.

In the step b), the etching solution is a phosphoric acid aqueous solution, and the concentration of phosphoric acid in the etching solution is 60-90 wt%.

In the step b), the method for cleaning the resist layer is: first rinse off the etching solution with water, and then rinse off the resist layer with an organic cleaning solution. The rinse time is at least 10s, so The organic cleaning solution is isopropanol, ethanol or dichloromethane.

After the step b), a modification step is performed: immersing the patterned aluminum oxide dielectric layer and the grid in the modification solution for at least 2 hours and then cleaning.

In the modification step, the modification solution is octadecyl phosphoric acid solution, and the solvent is isopropanol.

In the above technical solution, the concentration of octadecyl phosphoric acid in the modification solution is 2-4 mM.

In the modifying step, isopropanol is used for the cleaning, and the cleaning time is 5-10 minutes.

Application of the above-mentioned patterned aluminum oxide dielectric layer and gate in a field effect transistor.

In the above technical solution, the preparation method of the field effect transistor is: covering the patterned aluminum oxide dielectric layer and the aluminum oxide dielectric layer of the gate with an organic thin film, and then pasting the organic thin film on the A mask plate is vacuum-evaporated with a silver layer as a source electrode and a drain electrode to obtain a field effect transistor.

In the above technical solution, the preparation method of the field effect transistor is as follows: attaching an upper mask plate on the patterned aluminum oxide dielectric layer and the aluminum oxide dielectric layer of the gate, vacuum evaporating organic matter to form an organic thin film, A mask plate is attached, and a silver layer is vacuum-evaporated as a source electrode and a drain electrode to obtain a field-effect transistor; multiple field-effect transistors are connected to form a Pseudo-D inverter.

In the above technical solution, the material of the organic thin film is C8-BTBT or C10-DNTT.

In the above technical solution, the mobility of the field effect transistor is 3-5 cm ² /(v*s) ^-1 , the average switching ratio is 10 ⁶ , and the gain of the Pseudo-D inverter is 75.

The present invention is based on the beneficial effects of the preparation method of screen printing patterned aluminum oxide dielectric layer and grid as follows:

1. The preparation method of the present invention is simple to operate, and only two steps are needed to obtain the patterned aluminum oxide dielectric layer and grid, and the resist layer can be printed by screen printing method, and various patterns can be obtained simply and quickly, which is for subsequent Circuit design provides better conditions for fabricating complex circuits without the complex and time-consuming operations of traditional photolithography and etching patterning techniques.

2. In the present invention, a single medium-strong-acid phosphoric acid solution is selected instead of a complicated mixed solution, so as to reduce the danger of using a strong acid operation and avoid the complicated steps required for using a strong acid. After the curing is completed, soak in the etching solution. After the etching is completed, use an organic cleaning solution to clean the substrate, and then obtain the patterned dielectric layer and gate, as shown in FIG. 10 .

3. The patterned alumina dielectric layer obtained after a series of operations has low leakage current density and small variation range, and has excellent properties, which is conducive to obtaining better device performance. The prepared TFT device and Pseudo-D inverter It has outstanding properties and can be applied to the manufacture of integrated circuits in the semiconductor industry.

Description of drawings

Fig. 1 is the flow process of the preparation method of the aluminum oxide dielectric layer of confining growth of the present invention;

Fig. 2 is the schematic diagram of electrochemical anodic oxidation setting in the embodiment of the present invention;

Fig. 3 (a) is the cross-sectional schematic diagram after step 2) finishes, and Fig. 3 (b) is the optical picture of the mask obtained after screen printing in embodiment 2 step 2); Fig. 3 (c) is Fig. 3 (b) enlarged view of

Figure 4 (a) is a cross-sectional schematic diagram after step 3) is completed, and Figure 4 (b) is an optical picture of the aluminum oxide dielectric layer and gate site obtained in step 3) of Example 2; Figure 4 (c) is a diagram Enlarged view of 4(b);

5 is a current-voltage diagram between different gate sites in Embodiment 2 of the present invention;

Fig. 6 is the AFM figure of aluminum (left) and aluminum oxide (right) obtained in the embodiment 2 of the present invention;

Fig. 7 is the transfer characteristic curve of the C8-BTBT transistor prepared in Example 1 of the present invention;

Fig. 8 is the transfer characteristic curve of the C10-DNTT transistor prepared in Example 2 of the present invention;

FIG. 9 is a flowchart of a method for preparing a patterned aluminum oxide dielectric layer and a gate in the present invention;

Figure 10(a) is a cross-sectional schematic diagram after step b) is completed, and Figure 10(b) is an optical picture of the patterned alumina and grid obtained in step b) of Example 3; Figure 10c) is Figure 10(b) enlarged view of

Figure 11 is the patterned alumina dielectric layer J-V in Example 3 of the present invention;

Fig. 12 is the transfer curve of a single device in Example 3 of the present invention;

FIG. 13 is a patterned alumina dielectric layer J-V in Embodiment 4 of the present invention;

Figure 14 is the transfer curve of a single device in Example 4 of the present invention;

Fig. 15 (a) Schematic diagram of structural design of the inverter, (b) optical photo of the inverter sample, (c) gain of the inverter prepared based on the present invention.

detailed description

The technical solutions of the present invention will be further described below in conjunction with specific embodiments.

The purity of nitrogen is 99.999%

Example 1

As shown in Figure 1, a method for preparing an aluminum oxide dielectric layer with confinement growth of a common gate contact site comprises the following steps:

1) Vacuum deposition grid:

A substrate is prepared, and the substrate is polyethylene naphthalate (PEN). After cleaning the substrate, dry the substrate with nitrogen gas, and evaporate an aluminum film with a thickness of 100 nm on the substrate as the grid;

2) Use screen printing method to print a layer of photoresist material on the aluminum film as a mask, and confirm that the pattern is printed clearly, as shown in Figure 3 (3(a), 3(b) and 3(c)), 60 Cure for 2 minutes (in order to reduce the erosion of the electrolyte in the electrolytic cell to the pattern in the mask area, the mask needs to be cured); wherein, the photoresist material is photoresist. The silk screen adopted in the screen printing method is 500 meshes, the moving speed of the squeegee during screen printing is 20mm/s, the pattern of mask is the rectangular photoresist material layer arranged along the rectangular matrix, the rectangular photoresist material layer The dimensions are 300 μm × 300 μm.

3) Electrochemical anodizing:

Use the substrate printed with a mask as the anode, prepare graphite as the conductive material, and use the conductive material as the cathode, soak the anode and cathode in the electrolyte, as shown in Figure 2, apply a density of 0.07mA/ cm ² constant current, the anode soaked in the electrolyte will produce an oxidation reaction, the aluminum film that is not covered by the mask in step 2) is oxidized to form aluminum oxide, and the mask is washed away with ethanol to obtain a grid connection site The aluminum oxide dielectric layer grown by confinement of dots is shown in Fig. 4 (4(a), 4(b) and 4(c)).

Preparation of flexible low-voltage C8-BTBT field-effect transistors: the flexible confinement-grown alumina dielectric layer prepared by steps 1) to 3) is scraped and coated with a layer of C8 on the alumina dielectric layer by the solution shearing method -BTBT film with a thickness of 27-30nm, and then attach a mask plate on the surface of the C8-BTBT film (the mask plate is custom-made from Beijing Xinxing Bairui Technology Co., Ltd., with a width-to-length ratio of 3:1), by vacuum evaporation 40nm Thick silver is used as the source and drain electrodes to obtain a C8-BTBT transistor, in which the channel width to length ratio is 3:1. The electrical performance was tested on the electrical performance testing instrument Kerthley4200CSC. The transfer characteristic curve of the C8-BTBT transistor is shown in Figure 7, which reflects the properties of a typical p-type field effect transistor, and the saturation voltage is as low as 5 volts. The prepared flexible low-voltage The mobility of the C8-BTBT transistor can reach 3cm ² /(v*s) ^-1 , and the on/off ratio can reach 10 ⁵ . The structural formula of C8-BTBT is as follows:

Example 2

A method for preparing a confinement-grown aluminum oxide dielectric layer with a common gate contact site, comprising the following steps:

1) Vacuum deposition grid:

A substrate is prepared, which is a glass slide. After cleaning the substrate, dry the substrate with nitrogen gas, and evaporate an aluminum film with a thickness of 100 nm on the substrate as the grid;

2) Use screen printing method to print a layer of photoresist material on the aluminum film as a mask, confirm that the pattern is printed clearly, and cure at 60°C for 2 minutes (in order to reduce the erosion of the electrolyte in the electrolytic cell to the pattern in the mask area, it is necessary to curing the mask); wherein, the photoresist material is photoresist. The silk screen adopted in the screen printing method is 500 meshes, the moving speed of the squeegee during screen printing is 20mm/s, the pattern of mask is the rectangular photoresist material layer arranged along the rectangular matrix, the rectangular photoresist material layer The dimensions are 300 μm × 300 μm. .

3) Electrochemical anodizing:

The substrate printed with a mask is used as the anode, graphite is prepared as the conductive material, the conductive material is used as the cathode, the anode and the cathode are immersed in the electrolyte, and a constant current with a density of 0.07mA/ ^cm2 is applied between the anode and the cathode, The anode soaked in the electrolyte will produce an oxidation reaction, and the aluminum film not covered by the mask in step 2) will be oxidized to form aluminum oxide, and the mask will be washed away with ethanol to obtain a confined growth with a gate connection site. alumina dielectric layer.

Use Keithley 4200CSC to test the conductivity of different gate sites of the prepared confinement-growth alumina dielectric layer, as shown in Figure 5, it can be found that different gate connection sites are connected to each other, as In the future, complex circuits such as inverters will be prepared to provide gates. Using a scanning probe microscope (AFM), the roughness of the prepared confinement-grown aluminum oxide dielectric layer and the surface of the gate site was measured, as shown in Figure 6, the root mean square roughness of aluminum and aluminum oxide were respectively 2.52 and 1.45nm, the surface is smooth, which provides an excellent contact interface for the subsequent preparation of transistors, which is conducive to obtaining better device properties.

Preparation of low-voltage C10-DNTT field-effect thin film transistors: attach an upper mask plate on the confinement-grown alumina dielectric layer prepared through steps 1) to 3) (the mask plate is customized by Beijing Xinxing Bairui Technology Co., Ltd., wide The length ratio is 5:1). A 40nm thick C10-DNTT film was deposited by vacuum evaporation, and then a mask was attached on the surface of the C10-DNTT film (the mask was customized from Beijing Xinxing Bairui Technology Co., Ltd., with a width-to-length ratio of 3:1). Plating silver with a thickness of 40nm as the source-drain electrodes yields a C10-DNTT transistor, wherein the channel width-to-length ratio is 3:1. The electrical performance was tested on the electrical performance testing instrument Keithley 4200CSC. The transfer curve is shown in Figure 8, which reflects the properties of a typical p-type field effect transistor, and the saturation voltage is as low as 5 volts. It can be found that the mobility of the prepared C10-DNTT transistor can be It reaches 2.6cm ² /(v*s) ^-1 , and the on-off ratio reaches 10 ⁷ . The structural formula of C10-DNTT is as follows:

Example 3

As shown in Figure 9, a method for preparing a patterned aluminum oxide dielectric layer and grid based on screen printing includes the following steps:

a) Immerse the alumina dielectric layer of the confinement-grown alumina dielectric layer obtained in Example 2 into isopropanol, ultrasonicate for 5 minutes, blow dry with nitrogen, and print on the alumina dielectric layer by screen printing A layer of photoresist is screen-printed as a resist layer (determining that the pattern is printed clearly), cured at 80° C. for 2 minutes, wherein the photoresist is a positive photoresist, and the screen used in the screen printing method is 500 mesh. The moving speed of the scraper during screen printing is 20 mm/s, the pattern of the resist layer is a photoresist layer arranged along a rectangular matrix, and the size of the photoresist layer is a square of 700 μm×700 μm;

b) Put the substrate obtained in step a) into an etching solution until the aluminum oxide dielectric layer not covered by the resist layer is etched away, and then clean the resist layer to obtain a patterned aluminum oxide dielectric layer and gate ( gate and the patterned alumina dielectric layer thereon), wherein the etchant is a phosphoric acid aqueous solution, and the concentration of phosphoric acid in the etchant is 85wt%, and the method for cleaning the resist layer is: first use water to rinse off Etching solution, and then use isopropanol to rinse off the resist layer, and the rinse time is 10s.

Use Keithley 4200CSC to test the leakage current density of the prepared dielectric layer, as shown in the current-voltage diagram in Figure 11, under low voltage, the leakage current density is lower than 10 ^-8 A/cm ² , and the leakage current density of alumina is low And the variation range is small, showing that its performance is stable and excellent.

Preparation of low-voltage C8-BTBT field-effect transistor: On the patterned alumina dielectric layer prepared by steps a) to b), scrape-coat a layer of C8-BTBT film with a thickness of 27-30nm by solution shearing method , and then attach a mask plate on the surface of the C8-BTBT film (the mask plate is customized by Beijing Xinxing Bairui Technology Co., Ltd., with a width-to-length ratio of 5:1), and vacuum-deposit 40nm thick silver as the source-drain electrode to obtain C8-BTBT transistor, wherein the channel width to length ratio is 5:1. The electrical performance was tested on the electrical performance testing instrument Kerthley4200CSC. The transfer characteristic curve and leakage current of the C8-BTBT transistor are shown in Figure 12. It can be found that the mobility of the prepared flexible C8-BTBT transistor can reach 5cm ² /(v*s) ^{- 1} , the on-off ratio reaches 10 ⁶ . The structural formula of C8-BTBT is as follows:

Example 4

A method for preparing a patterned aluminum oxide dielectric layer and grid based on screen printing, comprising the following steps:

a) Immerse the alumina dielectric layer of the confinement-grown alumina dielectric layer obtained in Example 2 into isopropanol, ultrasonicate for 5 minutes, blow dry with nitrogen, and print on the alumina dielectric layer by screen printing A layer of photoresist is screen-printed as a resist layer (determining that the pattern is printed clearly), cured at 80° C. for 2 minutes, wherein the photoresist is a positive photoresist, and the screen used in the screen printing method is 500 mesh. The moving speed of the scraper during screen printing is 20 mm/s, the pattern of the resist layer is a photoresist layer arranged along a rectangular matrix, and the size of the photoresist layer is a square of 700 μm×700 μm;

b) putting the substrate obtained in step a) into an etching solution until the aluminum oxide dielectric layer not covered by the resist layer is etched away, and cleaning the resist layer to obtain a patterned aluminum oxide dielectric layer and a gate, Wherein, the etching solution is phosphoric acid aqueous solution, and the concentration of phosphoric acid in the etching solution is 85wt%. The time is 10s.

After step b), a modification step is performed: immerse the patterned alumina dielectric layer and the grid in the modification solution for 2 hours, and wash with isopropanol for 5 minutes. The modification solution is octadecyl phosphoric acid solution, and the solvent of the modification solution It is isopropanol, and the concentration of octadecyl phosphate in the modification solution is 2 mM.

Using Keithley 4200CSC to test the leakage current density of the prepared dielectric layer, it can be found that under low voltage, the leakage current density is lower than 10 ^-9 A/cm ² , and the leakage current is stable, as shown in the current-voltage diagram in Figure 13 Show.

Preparing a Pseudo-D inverter: attaching a mask on the patterned alumina dielectric layer prepared through steps a) to b). A 40nm-thick C10-DNTT film is deposited by vacuum evaporation, and then a mask plate is attached on the surface of the C10-DNTT film (the mask plate is customized by Beijing Xinxing Bairui Technology Co., Ltd., and the aspect ratio is customized according to the circuit design). Evaporate 40nm silver as the source and drain electrodes to obtain 4 C10-DNTT field-effect thin film transistors, and the width-to-length ratios of the masks of the 4 C10-DNTT field-effect thin film transistors are 2:1, 6:1, 6:1, 10:1, connect four C10-DNTT field effect thin film transistors to each other as shown in Figure 15(a) Inverter structure design schematic diagram to obtain a Pseudo-D inverter, as shown in Figure 15(a), Pseudo- The channel width-to-length ratio of the D inverter is 2:1, 6:1, 6:1, and 10:1 from top to bottom. The electrical performance was tested on the electrical performance testing instrument Keithley 4200CSC. The transfer curve and gate leakage current are shown in Figure 14. It can be found that the mobility of the prepared C10-DNTT field effect thin film transistor can reach 3cm ² /(v*s) ^-1 , the switching ratio reaches 10 ⁶ , and the gain of the Pseudo-D inverter can reach 75 as shown in Figure 15c.

Statement Regarding Funding Research or Development

This invention has received financial support from the Ministry of Science and Technology of China (approval numbers: 2016YFB0401100 and 2017YFA0204503), the National Natural Science Foundation of China (51702297, 51633006, 51725304, 51733004, 51703159 and 51703160) and strategic key research.

The present invention has been described as an example above, and it should be noted that, without departing from the core of the present invention, any simple deformation, modification or other equivalent replacements that can be made by those skilled in the art without creative labor all fall within the scope of this invention. protection scope of the invention.

Claims (7)

1. A preparation method of a patterned alumina dielectric layer and a grid based on screen printing is characterized by comprising the following steps:

a) Immersing the alumina dielectric layer with limited growth in isopropanol, ultrasonically treating for 5-10 minutes, drying, silk-screen printing a layer of photoresist as an anti-corrosion layer on the alumina dielectric layer by adopting a silk-screen printing method, and curing for 1-2 minutes;

wherein, in the step a), the drying is blow-drying by nitrogen;

in the step a), the purity of the nitrogen is 99.999 percent, a silk screen adopted in the silk screen printing method is 300-500 meshes, and the moving speed of a scraper during silk screen printing is 5-20mm/s;

in the step a), the photoresist is a positive photoresist material or a negative photoresist material;

in the step a), the curing temperature is 40-80 ℃;

in the step a), the pattern of the resist layer is a photoresist layer arranged along a rectangular matrix, and the size of the photoresist layer is 700 μm × 700 μm;

b) Putting the substrate obtained in the step a) into etching liquid until the alumina dielectric layer which is not covered by the anti-corrosion layer is etched, and cleaning the anti-corrosion layer to obtain a patterned alumina dielectric layer and a grid electrode, wherein the preparation method of the alumina dielectric layer with the limited growth comprises the following steps:

1) Vacuum deposition of a grid: cleaning the substrate, drying the substrate, and evaporating an aluminum film with the thickness of 70-150nm on the substrate to be used as a grid;

2) Printing a layer of photoresist material on the aluminum film by adopting a screen printing method as a mask, and curing for 1-2 minutes;

3) Electrochemical anodic oxidation: taking the substrate as an anode, taking a conductive material as a cathode, soaking the anode and the cathode in electrolyte, applying constant current between the anode and the cathode to oxidize the aluminum film which is not covered by the mask in the step 2) to form aluminum oxide, and washing the mask by using an organic solvent to obtain an aluminum oxide dielectric layer with limited growth;

wherein, in the step b), the etching liquid is phosphoric acid aqueous solution, and the concentration of phosphoric acid in the etching liquid is 60-90 wt%;

in the step b), the method for cleaning the resist layer comprises: firstly, washing the etching solution by using water, and then washing the anti-corrosion layer by using an organic cleaning solution, wherein the washing time is at least 10s, and the organic cleaning solution is isopropanol, ethanol or dichloromethane;

after said step b), a modification step is carried out: soaking the patterned aluminum oxide dielectric layer and the grid electrode into a modification liquid for at least 2 hours and then cleaning;

in the step 1), the substrate is dried by blowing with nitrogen;

in the step 1), the substrate is a rigid substrate or a flexible substrate, the rigid substrate is a quartz plate or a glass slide, and the flexible substrate is polyethylene naphthalate or polymethyl methacrylate;

in the step 1), the purity of the nitrogen is 99.999 percent;

in the step 2), the screen adopted in the screen printing method is 300-500 meshes, and the moving speed of the scraper during screen printing is 5-20mm/s;

in the step 2), the pattern of the mask is a rectangular photoresist material layer arranged along a rectangular matrix, and the size of the rectangular photoresist material layer is 300 microns multiplied by 300 microns;

in the step 2), the photoresist material is a positive photoresist material or a negative photoresist material;

in the step 2), the curing temperature is 40-80 ℃;

in the step 3), the conductive material is Pt, au or graphite;

in the step 3), the density of the constant current is 0.007 to 0.07mA/cm < 2 >;

in the step 3), the organic solvent is isopropanol, ethanol or dichloromethane;

in the modification step, the modification liquid is an octadecyl phosphate solution, the solvent is isopropanol, the concentration of the octadecyl phosphate in the modification liquid is 2-4 mM, the isopropanol is adopted for cleaning, and the cleaning time is 5-10 min.

2. The patterned alumina dielectric layer and gate obtained by the method of claim 1.

3. Use of the patterned alumina dielectric layer and gate of claim 2 in field effect transistors and Pseudo-D inverters.

4. The use according to claim 3, wherein the field effect transistor is prepared by a method comprising: and covering a layer of organic film on the patterned alumina dielectric layer and the alumina dielectric layer of the grid, attaching a mask plate on the organic film, and performing vacuum evaporation on a silver layer serving as a source electrode and a drain electrode to obtain the field effect transistor.

5. The use according to claim 3, wherein the field effect transistor is prepared by a method comprising: attaching a mask plate on the patterned alumina dielectric layer and the alumina dielectric layer of the grid, carrying out vacuum evaporation on organic matters to form an organic matter film, attaching a mask plate, and carrying out vacuum evaporation on a silver layer serving as a source electrode and a drain electrode to obtain a field effect transistor; connecting a plurality of field effect transistors into a Pseudo-D inverter.

6. The use according to claim 4 or 5, wherein the organic thin film is C8-BTBT or C10-DNTT.

7. Use according to claim 6, wherein the field effect transistor has a mobility which can be between 3 and 5cm ² /(v*s) ^-1 The average of the switching ratios is 106 and the pseudo-D inverter gain is 75.

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