CN112416848B - Source chip, destination chip, data transmission method and processor system - Google Patents

Abstract

The application provides a source chip, a destination chip, a data transmission method and a processor system, which comprise a data coding module and a driver, wherein the data coding module is connected with the driver; the data coding module is used for receiving serial data, coding the serial data to obtain coded data and transmitting the coded data to the driver, wherein jump delay exists between any two adjacent data of the coded data; the driver is used for receiving the coded data and transmitting the coded data to a target chip of the opposite terminal, so that the target chip of the opposite terminal recovers the coded data into serial data according to the coded data with jump delay between any two adjacent data. By encoding the serial data, the encoded data carries a clock signal through the change of the jump delay, and compared with the chip self-adaptive clock which does not carry the clock signal in the prior art and needs an opposite terminal, the difficulty of clock recovery is reduced, and the delay of data transmission is reduced.

Description

Source chip, destination chip, data transmission method and processor system

Technical field

The present application relates to the field of computers, specifically, to a source chip, a destination chip, a data transmission method and a processor system.

Background technique

In the existing technology, when data is transmitted between two chip dies, the source chip often transmits both the data and the clock signal corresponding to the data to the destination chip. The destination chip can receive the data according to the received clock signal. The data is collected. However, since data and clock signals need to be transmitted simultaneously during transmission, the amount of data that needs to be transmitted is large.

In another method of the prior art, the source chip can only transmit data to the destination chip. The destination chip can adjust the frequency of its own clock signal through the feedback circuit so that the frequency of the clock can adapt to the data transmitted from the source chip. The destination chip can adjust the frequency of the clock signal according to the feedback circuit. The frequency of the adjusted clock is used to collect the received data. However, since the above method requires a feedback circuit to adjust its own clock, the clock recovery circuit is more complex and the data transmission delay is large.

Contents of the invention

The purpose of the embodiments of the present application is to provide a source chip, a destination chip, a data transmission method and a processor system to improve the problem of large data transmission delay between chip dies in the prior art.

In a first aspect, embodiments of the present application provide a source chip, which includes a data encoding module and a driver. The data encoding module is connected to the driver; the data encoding module is used to receive serial data and perform processing on the serial data. The data is encoded to obtain encoded data, and the encoded data is transmitted to the driver, wherein there is a jump delay between any two adjacent data of the encoded data; the driver is used to receive the encoded data , and sends the encoded data to the destination chip of the opposite end, so that the destination chip of the opposite end restores the encoded data to the encoded data according to the encoded data that has a jump delay between any two adjacent data. Described serial data.

In the above embodiment, the data encoding module can encode the serial data to obtain encoded data, so as to achieve a jump delay between any two adjacent data of the encoded data. Since there is a transition delay between any two adjacent pieces of data, each time the chip at the opposite end receives a piece of data, it can be informed by the change in the transition delay. That is, each change in transition delay corresponds to a receiving data. The received data is equivalent to using encoded data to realize the transmission of clock signals. By encoding the serial data, the encoded data carries the clock signal through the change of transition delay. Compared with the existing technology that does not carry the clock signal and requires an adaptive clock on the opposite end chip, the difficulty of recovering the clock is reduced and the time is reduced. Reduces data transmission delay.

In a possible design, the data encoding module is used to receive serial data and encode the serial data to obtain encoded data, which specifically includes: receiving current data; determining whether the level state corresponding to the current data is consistent with the required level. Whether the level state corresponding to the previous data of the current data is consistent; if so, encode the current data to an intermediate level; if not, encode the current data to a level state consistent with the current data.

In the above embodiment, the level state of the current data can be compared with the level state of the previous data to determine whether the level states of the two are consistent. If they are consistent, the level of the current data is represented by the intermediate level. status, if inconsistent, the original level status of the current data is retained. Through the introduction of intermediate levels, when two adjacent data are at the same level, the level state of the latter data in the two adjacent data can be changed, so that the same level will not appear in the two adjacent data. Condition.

In a possible design, the data encoding module includes a first digital flip-flop, a second digital flip-flop, an exclusive OR operator and a selector; the CLK terminal of the first digital flip-flop is connected to a clock signal that transmits a clock signal The input terminal of the first digital flip-flop is connected to the serial data line for transmitting serial data, and the output terminal of the first digital flip-flop is connected to the first input terminal of the exclusive OR operator; The second input end of the OR operator is connected to the serial data line, the output end of the XOR operator is connected to the first input end of the selector; the output end of the selector is connected to the second The input end of the digital flip-flop is connected; the output end of the second digital flip-flop is connected to the second input end of the selector, and the CLK end of the second digital flip-flop is connected to the clock signal line.

In the above embodiment, the first digital flip-flop can delay the serial data by one clock cycle, and perform an exclusive OR operation on the serial data and the serial data delayed by one clock cycle to obtain the operation result. According to the specific operation result and the level state of the previous bit of data, the level state of the bit of data can be determined.

In a possible design, the data encoding module is used to receive the serial data and encode the serial data to obtain encoded data, which specifically includes: using the exclusive OR operator to combine the serial data with The serial data delayed by one clock cycle through the first digital flip-flop performs an exclusive OR operation between bits to obtain an operation result; if the operation result is 0, the selected device is used to determine the serial data The level of the corresponding bit of the row data corresponding to the operation result and the corresponding bit of the encoded data is the original level; if the operation result is 1, the judgment is made based on the output result of the second digital flip-flop. Whether the level state of the encoded data corresponding to the previous bit of serial data is an intermediate level; if the level state of the encoded data corresponding to the previous bit of data is an intermediate level, determine the level of the serial data The level of the bit corresponding to the operation result in the corresponding bit of the encoded data is the original level; if the level state of the encoded data corresponding to the previous bit of data is not an intermediate level, then it is determined that the serial The level of the bit of the data corresponding to the operation result and the corresponding bit of the encoded data is an intermediate level.

In the above embodiment, if the operation result is 0, it means that the level state of the current bit data is different from the level state of the previous bit data, and the original level of the bit data can be directly output. If the operation result is 1, it means that the level state of the current bit data is the same as the actual level state of the previous bit data. It needs to be further determined: whether the level state of the previous bit data has been changed to an intermediate level. If the level state of the previous bit of data is changed to the middle level, the level state of the current bit of data does not need to be modified, and the original level can be output directly to distinguish it from the level state of the previous bit of data; If the level state of the previous bit of data has not been changed to the middle level, the level state of the current bit of data needs to be modified to the middle level to distinguish it from the level state of the previous bit of data.

In the second aspect, embodiments of the present application provide a destination chip that cooperates with the source chip of the first aspect or any possible design of the first aspect, including a first comparator, a second comparator, and a clock recovery circuit. And a data recovery circuit; the first comparator is used to receive the encoded data sent by the source chip of the opposite end, and compare the encoded data with the first reference level, and compare the encoded data with the higher than the first reference level. The output that is flat is high level, and the output that is lower than the first reference level is low level, and the first waveform is obtained, wherein the first reference level is between the middle level and the high level; so The second comparator is used to receive the encoded data and compare the encoded data with a second reference level, and output the encoded data higher than the second reference level as a high level, and the encoded data lower than the second reference level. The output of the second reference level is low level to obtain a second waveform, wherein the second reference level is between the intermediate level and the low level; the clock recovery circuit is used to obtain the first waveform. The waveform inversion pulse of one waveform and the waveform inversion pulse of the second waveform are combined and processed to obtain a clock recovery signal; the data recovery circuit is used to collect the encoded data according to the clock recovery signal , and restore the encoded data into serial data.

In the above embodiment, the first comparator can restore the middle level to a low level through its own reference level to obtain the first waveform; the second comparator can restore the middle level to a low level through its own reference level. High level, get the second waveform. Then the clock recovery circuit can respectively obtain the pulse corresponding to the waveform flip position of the first waveform and the pulse corresponding to the waveform flip position of the second waveform, and then process the two pulses together to obtain the clock recovery signal. The data recovery circuit can collect the encoded data based on the above-mentioned clock recovery signal and restore the encoded data to serial data. Through the cooperation of the first comparator, the second comparator and the clock recovery circuit, the clock signal can be recovered from the encoded data. Compared with the existing technology, the circuit structure of the clock signal recovery is simple, which reduces the difficulty of recovering the clock. Reduces data transmission delay.

In a possible design, the clock recovery circuit includes at least a first delayer, a first XOR operator, at least a second delayer, a second XOR operator and an OR operator; the at least A first delayer is used to delay the first waveform; the first XOR operator is used to XOR the first waveform and the first waveform delayed by the at least one first delayer. operation to obtain the first pulse waveform; the at least one second delayer is used to delay the second waveform; the second XOR operator is used to delay the second waveform through the at least one second The second waveform delayed by the delay device is subjected to an XOR operation to obtain a second pulse waveform; the OR operator is used to perform OR processing on the first pulse waveform and the second pulse waveform to obtain a pulse fusion waveform. The pulse fusion The waveform is the clock recovery signal.

In the above embodiment, the clock recovery circuit includes a first delayer, a first XOR operator, a second delayer, a second XOR operator and an OR operator. The first delayer is used to delay the first waveform, and the first XOR operator performs XOR processing on the delayed first waveform and the first waveform to obtain a pulse signal composed of the first waveform at the flip position. waveform, which can be recorded as the first pulse waveform. The second XOR operator performs XOR processing on the delayed second waveform and the second waveform, and can obtain a waveform composed of the pulse signal of the second waveform at the flip position, and this waveform is recorded as the second pulse waveform. Take the OR set of the first pulse waveform and the second pulse waveform to obtain the pulse fusion waveform. The time interval between two adjacent pulses of the pulse fusion waveform is the same as the time interval between two adjacent data in the encoded data. Therefore, this pulse fusion waveform is the clock recovery signal.

In a possible design, the clock recovery circuit further includes a frequency divider, the CLK terminal of the frequency divider is connected to the output terminal of the OR operator; the frequency divider is used to convert the clock The recovered signal is divided by two to obtain a clock recovery signal with a duty cycle of 50%.

In the above embodiment, after obtaining the clock recovery signal, the clock recovery signal can also be divided by two using a frequency divider to obtain a clock recovery signal with a duty cycle of 50%. The clock recovery signal processed by dividing by two is more stable.

In a possible design, the data recovery circuit is used to collect the encoded data according to the clock recovery signal and restore the encoded data into serial data, specifically including: determining that the current data received is an intermediate level. Status; obtain the level status of the previous data of the current data, and use the level status of the previous data as the level status of the current data.

In the above embodiment, when the data recovery circuit recovers the encoded data into serial data, it can collect the encoded data according to the frequency of the clock recovery signal, and determine the received data based on the comparison results of the first comparator and the second comparator. Whether the current data is in the intermediate level state, if not, the high level will return to 1 corresponding to the high level, and the low level will return to 0 corresponding to the low level. If the current data is in an intermediate level state, the level state of the previous data is obtained, and the value corresponding to the current data is determined based on the level state of the previous data. This recovery process is simple and requires little calculation.

In a third aspect, the present application provides a data transmission method, applied to a source chip. The method includes: the data encoding module of the source chip receives serial data, encodes the serial data to obtain encoded data, and The encoded data is transmitted to the driver of the source chip, where there is a jump delay between any two adjacent data of the encoded data; the driver receives the encoded data and sends the encoded data to the destination chip at the opposite end, so that the destination chip at the opposite end processes the encoded data.

In the above embodiment, the data encoding module can encode the serial data to obtain encoded data, so as to achieve a jump delay between any two adjacent data of the encoded data. Since there is a transition delay between any two adjacent pieces of data, each time the chip at the opposite end receives a piece of data, it can be informed by the change in the transition delay. That is, each change in transition delay corresponds to a receiving data. The received data is equivalent to using encoded data to realize the transmission of clock signals. By encoding the serial data, the encoded data carries the clock signal through the change of transition delay. Compared with the existing technology that does not carry the clock signal and requires an adaptive clock on the opposite end chip, the difficulty of recovering the clock is reduced and the time is reduced. Reduces data transmission delay.

In a possible design, the data encoding module receives serial data, encodes the serial data to obtain encoded data, including: receiving current data; judging the level state corresponding to the current data and the current data Whether the level state corresponding to the previous data is consistent; if so, the current data is encoded as an intermediate level; if not, the level state corresponding to the current data is retained.

In the above embodiment, the level state of the current data can be compared with the level state of the previous data to determine whether the level states of the two are consistent. If they are consistent, the level of the current data is represented by the intermediate level. status, if inconsistent, the original level status of the current data is retained. Through the introduction of intermediate levels, when two adjacent data are at the same level, the level state of the latter data in the two adjacent data can be changed, so that the same level will not appear in the two adjacent data. Condition.

In a possible design, the data encoding module includes a first digital flip-flop, a second digital flip-flop, an exclusive OR operator and a selector; the CLK terminal of the first digital flip-flop receives a clock signal, and the first digital flip-flop The input end of the flip-flop is used to receive the serial data, the output end of the first digital flip-flop is connected to the first input end of the XOR operator; the second input end of the XOR operator is When receiving the serial data, the output terminal of the XOR operator is connected to the first input terminal of the selector; the output terminal of the selector is connected to the input terminal of the second digital flip-flop; the The output end of the second digital flip-flop is connected to the second input end of the selector, and the CLK end of the second digital flip-flop is used to receive the clock signal; the data encoding module receives the serial data , encoding the serial data to obtain encoded data, including: performing an exclusive OR operation between bits on the serial data and the serial data that has been delayed by one clock cycle to obtain the operation result; if the operation If the result is 0, it is determined that the data level of the corresponding bit of the serial data is the original level; if the operation result is 1, it is determined whether the level state of the previous bit of data is the middle level; if the previous If the level state of the bit data is an intermediate level, it is determined that the level of the corresponding bit data of the serial data is the original level; if the level state of the previous bit data is not an intermediate level, it is determined that the serial data level is not an intermediate level. The data level of the corresponding bit of the row data is the middle level.

In the above embodiment, the first digital flip-flop can delay the serial data by one clock cycle, and perform an exclusive OR operation on the serial data and the serial data delayed by one clock cycle to obtain the operation result. According to the specific operation result and the level state of the previous bit of data, the level state of the bit of data can be determined. If the operation result is 0, it means that the level state of the current bit data is different from the level state of the previous bit data, and the original level of the bit data can be directly output. If the operation result is 1, it means that the level state of the current bit data is the same as the actual level state of the previous bit data. It needs to be further determined: whether the level state of the previous bit data has been changed to an intermediate level. If the level state of the previous bit of data is changed to the middle level, the level state of the current bit of data does not need to be modified, and the original level can be output directly to distinguish it from the level state of the previous bit of data; If the level state of the previous bit of data has not been changed to the middle level, the level state of the current bit of data needs to be modified to the middle level to distinguish it from the level state of the previous bit of data.

In a fourth aspect, the present application provides a data transmission method, applied to a destination chip. The method includes: the first comparator of the destination chip receives the encoded data sent by the source chip of the opposite end, and compares the encoded data with the first comparator of the destination chip. A reference level is compared, the output of the encoded data higher than the first reference level is high level, and the output lower than the first reference level is low level to obtain the first waveform, and The first waveform is transmitted to the clock recovery circuit of the destination chip, wherein the first reference level is between the intermediate level and the high level; the second comparator of the destination chip receives the code data, and compare the encoded data with the second reference level, output the encoded data higher than the second reference level as high level, and output the encoded data lower than the second reference level as low level, obtain a second waveform, and transmit the second waveform to the clock recovery circuit of the destination chip, wherein the second reference level is between the intermediate level and the low level; The clock recovery circuit acquires the waveform inversion pulse of the first waveform and the waveform inversion pulse of the second waveform, and processes the acquired pulses to obtain a clock recovery signal, and transmits the clock recovery signal To the data recovery circuit of the destination chip; the data recovery circuit collects the encoded data according to the clock recovery signal and restores the encoded data into serial data.

In the above embodiment, the first comparator can restore the middle level to a low level through its own reference level to obtain the first waveform; the second comparator can restore the middle level to a low level through its own reference level. High level, get the second waveform. Then the clock recovery circuit can respectively obtain the pulse corresponding to the waveform flip position of the first waveform and the pulse corresponding to the waveform flip position of the second waveform, and then process the two pulses together to obtain the clock recovery signal. The data recovery circuit can collect the encoded data based on the above-mentioned clock recovery signal and restore the encoded data to serial data. Through the cooperation of the first comparator, the second comparator and the clock recovery circuit, the clock signal can be recovered from the encoded data. Compared with the existing technology, the circuit structure of the clock signal recovery is simple, which reduces the difficulty of recovering the clock. Reduces data transmission delay.

In a possible design, the clock recovery circuit includes at least a first delayer, a first XOR operator, at least a second delayer, a second XOR operator and an OR operator; the clock The recovery circuit acquires the waveform inversion pulse of the first waveform and the waveform inversion pulse of the second waveform, and processes the acquired pulses to obtain a clock recovery signal, including: the at least one first delayer The first waveform is delayed; the first XOR operator performs an XOR operation on the first waveform and the delayed first waveform to obtain a first pulse waveform, wherein the first pulse waveform is the The waveform of a waveform inverts the waveform of the corresponding pulse signal; the at least one second delayer delays the second waveform; the second XOR operator delays the second waveform and the delayed third waveform. Exclusive OR operation is performed on the two waveforms to obtain a second pulse waveform, wherein the second pulse waveform is the waveform in which the pulse signal corresponding to the waveform inversion of the second waveform is located; the OR operator performs the operation on the first pulse waveform Perform OR processing with the second pulse waveform to obtain a pulse fusion waveform, and the pulse fusion waveform is the clock recovery signal.

In the above embodiment, the clock recovery circuit includes a first delayer, a first XOR operator, a second delayer, a second XOR operator and an OR operator. The first delayer is used to delay the first waveform, and the first XOR operator performs XOR processing on the delayed first waveform and the first waveform to obtain a pulse signal composed of the first waveform at the flip position. waveform, which can be recorded as the first pulse waveform. The second XOR operator performs XOR processing on the delayed second waveform and the second waveform, and can obtain a waveform composed of the pulse signal of the second waveform at the flip position, and this waveform is recorded as the second pulse waveform. Take the OR set of the first pulse waveform and the second pulse waveform to obtain the pulse fusion waveform. The time interval between two adjacent pulses of the pulse fusion waveform is the same as the time interval between two adjacent data in the encoded data. Therefore, this pulse fusion waveform is the clock recovery signal.

In a possible design, the clock recovery circuit further includes a two-frequency divider, the CLK terminal of the two-frequency divider is connected to the output terminal of the OR operator; in the OR operator, the first After performing OR processing on the pulse waveform and the second pulse waveform to obtain the pulse fusion waveform, the method further includes: the frequency divider performs frequency division processing on the clock recovery signal to obtain a clock with a duty cycle of 50%. Restore signal.

In the above embodiment, after obtaining the clock recovery signal, the clock recovery signal can also be divided by two using a frequency divider to obtain a clock recovery signal with a duty cycle of 50%. The clock recovery signal processed by dividing by two is more stable.

In a possible design, the data recovery circuit collects the encoded data according to the clock recovery signal, and restores the encoded data into serial data, including: determining that the current data received is an intermediate level state; obtaining The level state of the previous data of the current data is taken as the level state of the current data.

In the above embodiment, when the data recovery circuit recovers the encoded data into serial data, it can collect the encoded data according to the frequency of the clock recovery signal, and determine the received data based on the comparison results of the first comparator and the second comparator. Whether the current data is in the intermediate level state, if not, the high level will return to 1 corresponding to the high level, and the low level will return to 0 corresponding to the low level. If the current data is in an intermediate level state, the level state of the previous data is obtained, and the value corresponding to the current data is determined based on the level state of the previous data. This recovery process is simple and requires little calculation.

In a fifth aspect, this application provides a processor system, including a chip of the first aspect or any possible design of the first aspect, and a chip of the second aspect or any possible design of the second aspect.

In order to make the above objects, features and advantages achieved by the embodiments of the present application more obvious and easy to understand, preferred embodiments are cited below and described in detail with reference to the attached drawings.

Description of the drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required to be used in the embodiments of the present application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present application, therefore This should not be regarded as limiting the scope. For those of ordinary skill in the art, other relevant drawings can be obtained based on these drawings without exerting creative efforts.

Figure 1 shows an application scenario diagram for data transmission between chip dies in the prior art;

Figure 2 shows a schematic structural diagram of a processor system provided by an embodiment of the present application;

Figure 3 shows a schematic structural diagram of the data encoding module;

Figure 4 shows the corresponding waveform diagram during the working process of the data encoding module;

Figure 5a shows a schematic structural diagram of the driver outputting a high level state;

Figure 5b shows a schematic structural diagram of the driver output intermediate level state;

Figure 5c shows a schematic structural diagram of the driver outputting a low level state;

Figure 6 shows a waveform diagram of a specific implementation of encoding serial data into encoded data;

Figure 7 shows the waveform diagram generated when the clock recovery circuit is working;

Figure 8 shows a schematic structural diagram of the clock recovery circuit;

Figure 9 shows a schematic flow chart of the data transmission method provided by the embodiment of the present application;

Figure 10 shows a schematic flowchart of a data transmission method provided by another embodiment of the present application;

FIG. 11 shows a schematic flowchart of the specific steps of step S230 in FIG. 10 .

Detailed ways

Please refer to FIG. 1 . FIG. 1 shows the method of data transmission between chip dies in the comparative embodiment. The following description will be based on data transmission from the source chip 100 to the destination chip 200 . In the embodiments of this application, the chips mentioned in the text are all die unless otherwise specified.

The transmitted data can be a Non Return Zero (NRZ) code or a Pulse Amplitude Modulation (PAM) code. Among them, NRZ transmits data 0 and 1 respectively through low level and high level, and PAM code uses multiple levels to encode and transmit multiple data.

In the source chip 100, the parallel-to-serial conversion module 101 converts four channels of parallel data into one channel of serial data, and sends the serial data through the driver 102.

In the destination chip 200, data is collected at different clock transition delays through the first receiver 201 and the second receiver 202 respectively. For example, it may be assumed that the first receiver 201 collects data on the rising edge of the clock, and the second receiver 202 collects data on the falling edge of the clock. The above clock may be a preset clock.

The first receiver 201 and the second receiver 202 collect data according to the preset clock, and transmit the collected data to the serial-to-parallel conversion module 203 for serial-to-parallel conversion. The serial-to-parallel conversion module 203 converts the two collected data Re-convert the four-channel parallel data into four-channel parallel data, and transmit the four-channel parallel data to the logic module 204.

The logic module 204 can determine whether the data is ahead of the clock or behind the clock based on the received four-channel parallel data. If the data is ahead of the clock, the logic module 204 can adjust the phase interpolator (PI) module 205 to advance the clock; if the data lags behind the clock, the logic module 204 can adjust the PI module 205 to delay the clock.

Among them, the PI module 205 can obtain the clock signal from the phase locked loop (Phase Locked Loop, PLL for short) 206, and adjust the clock signal according to the instructions of the logic module 204.

In the above-mentioned method of data transmission, the logic module 204 is required to adjust the clock according to the phase relationship between the clock and the data, resulting in a large data transmission delay.

In order to solve this problem, this application obtains encoded data by encoding the serial data, so that there is a jump delay between any two adjacent data of the encoded data, and the encoded data carries the clock signal through the change of the jump delay, so that Reduce the difficulty of recovering the clock.

Please refer to Figure 2. Figure 2 shows a processor system provided by an embodiment of the present application. The processor system includes a source chip 100 and a destination chip 200. The source chip 100 and the destination chip 200 communicate with each other.

The source chip 100 includes a parallel-to-serial conversion module 101, a data encoding module 110, and a driver 102. The parallel-to-serial conversion module 101, the data encoding module 110, and the driver 102 are connected in sequence.

The parallel-to-serial conversion module 101 is used to convert four channels of parallel data into one channel of serial data, and transmit the serial data to the data encoding module 110 .

The data encoding module 110 is used to receive serial data, encode the serial data to obtain encoded data, and transmit the encoded data to the driver 102, where there is a transition delay between any two adjacent data of the encoded data.

Optionally, the data encoding module 110 is specifically configured to: receive the current data; determine whether the level state corresponding to the current data is consistent with the level state corresponding to the previous data of the current data; if so, encode the current data into an intermediate level state. If not, retain the level state corresponding to the current data.

Please refer to Figure 6. Figure 6 shows a specific implementation manner of encoding serial data into encoded data. For serial data: 010 011 000 111, the parallel-to-serial conversion module 101 can transmit data according to the clock signal CLK: Each time CLK transitions, one piece of data can be transmitted to the data encoding module 110, that is, one piece of data can be transmitted to the data encoding module 110 on both the rising edge and the falling edge of CLK.

The data encoding module 110 can convert data 0 to a low-level state L, convert data 1 to a high-level state H, and when the level state of the current data is consistent with the level state of the previous data, convert the current data to the low-level state L. The level state is determined to be the intermediate level state M.

The process of converting three consecutive identical data in serial data into encoded data can be carried out as follows:

Let's take the three consecutive 0s in serial data: 010 011 000 111 as an example. The level state of the first 0 is different from the previous data 1, so the level state corresponding to the first 0 is L.

The level state corresponding to the second 0 is originally L, but since the level state corresponding to the second 0 is the same as the level state corresponding to the first 0, both are L, so the second 0 can be corresponding to The level state of is determined as the intermediate level state M.

The level state originally corresponding to the third 0 is L. Since the level state corresponding to the second 0 is determined to be the intermediate level state M, it is inconsistent with the level state originally corresponding to the third 0. Therefore, for the third 0 0, the original corresponding level state L can be output.

In summary, the encoded data corresponding to serial data 000 is LML.

Through the above processing method, the encoded data corresponding to the serial data: 010 011 000 111 can be obtained: LHLMHM LML HMH. Obviously, there is a jump delay between two adjacent data of the encoded encoded data.

Optionally, in a specific implementation, the data encoding module 110 can also convert data 0 to a high level state H, convert data 1 to a low level state L, and compare the level state of the current data with the previous one. When the level states of one data are consistent, the level state of the current data is determined as the intermediate level state M. The correspondence between data values and level states should not be understood as a limitation of the present application.

Referring to FIG. 3 , in a specific implementation, the data encoding module 110 includes a first digital flip-flop 111 , a second digital flip-flop 112 , an exclusive OR operator 113 and a selector 114 .

The CLK terminal of the first digital flip-flop 111 is used to receive a clock signal, the input terminal of the first digital flip-flop 111 is used to receive serial data, and the output terminal of the first digital flip-flop 111 is connected to the first input of the XOR operator 113 end connection.

The second input terminal of the exclusive NOR operator 113 is used to receive serial data, and the output terminal of the exclusive NOR operator 113 is connected to the first input terminal of the selector 114 .

The output terminal of the selector 114 is connected to the input terminal of the second digital flip-flop 112; the output terminal of the second digital flip-flop 112 is connected to the second input terminal of the selector 114, and the CLK terminal of the second digital flip-flop 112 is used to receive the clock signal.

The first digital flip-flop 111 is used to delay the serial data TxDat by one clock cycle, and the exclusive-OR operator 113 is used to perform an exclusive-OR operation between the serial data TxDat and the serial data TxDat_d that has been delayed by one clock cycle to obtain the operation result.

The selector 114 is used to determine the selection result Txweak output by the current clock cycle selector 114 based on the above operation result and the selection result Txweak_d output by the previous clock cycle selector 114.

Optionally, please refer to Figure 4. When TxDat and TxDat_d are the same or the processing result is 0, it is determined that the selection result Txweak output by the selector 114 of this clock cycle is 0.

When the OR processing result of TxDat and TxDat_d is 1, and the selection result Txweak_d output by the previous clock cycle selector 114 is 0, it is determined that the selection result Txweak output by the clock cycle selector 114 this time is 1.

When the OR processing result of TxDat and TxDat_d is 1, and the selection result Txweak_d output by the previous clock cycle selector 114 is 1, it is determined that the selection result Txweak output by the clock cycle selector 114 this time is 0.

Among them, Txweak is 1, and the driver 102 outputs an intermediate level; Txweak is 0, and the driver 102 outputs a level signal originally corresponding to the serial data.

If the operation result is 0, it means that the level state of the current bit data is different from the level state of the previous bit data, and the original level of the bit data can be directly output. If the operation result is 1, it means that the level state of the current bit data is the same as the actual level state of the previous bit data. It needs to be further determined: whether the level state of the previous bit data has been changed to an intermediate level.

If the level state of the previous bit of data is changed to the middle level, that is, the selection result Txweak_d output by the selector 114 of the previous clock cycle corresponding to the level state of the previous bit of data is 1, then the level state of the current bit of data No further modification is needed, and the original level can be directly output (that is, the selection result Txweak output by the clock cycle selector 114 this time is 0) to distinguish it from the level state of the previous bit of data; if the level of the previous bit of data is The flat state has not been changed to the intermediate level, that is, the selection result Txweak_d output by the selector 114 of the previous clock cycle corresponding to the level state of the previous bit data is 0, then the level state of the current bit data needs to be modified to the intermediate level. flat (that is, the selection result Txweak output by the selector 114 of this clock cycle is 1), to distinguish it from the level state of the previous bit of data.

The driver 102 is used to receive the encoded data and send the encoded data to the opposite end chip, so that the opposite end chip processes the encoded data.

Please refer to Figure 5a to Figure 5c. Figure 5a, Figure 5b, and Figure 5c together show a circuit diagram of a specific implementation of the driver 102. The driver 102 includes a first resistor R1, a second resistor R2, a first switch k1, The second switch k2, in which the power supply is connected to the ground through the first resistor R1, the first switch k1, the second switch k2, and the second resistor R2 in sequence. One end of the transmission line is connected between the first switch k1 and the second switch k2, and the other end of the transmission line is connected to the ground resistor R3 of the opposite end chip.

If the first switch k1 is closed and the second switch k2 is open, the transmission line transmits high level VDD/2. Please see Figure 5a for details; if the first switch k1 and the second switch k2 are both closed, the transmission line transmits Intermediate level VDD/4, please see Figure 5b for details; if the first switch k1 is open and the second switch k2 is closed, the transmission line transmits a low level 0, please see Figure 5c for details. Among them, the high level VDD/2 can correspond to data 1, and the low level 0 can correspond to data 0.

The source chip 100 can control the level state of the output of the driver 102 by controlling the closing or closing of the first switch k1 or the second switch k2.

For the source chip 100 provided in the embodiment of the present application, the data encoding module 110 can encode the serial data to obtain encoded data, so as to achieve a jump delay between any two adjacent data of the encoded data. Since there is a transition delay between any two adjacent pieces of data, each time the chip at the opposite end receives a piece of data, it can be informed by the change in the transition delay. That is, each change in transition delay corresponds to a receiving data. The received data is equivalent to using encoded data to realize the transmission of clock signals. By encoding the serial data, the encoded data carries the clock signal through the change of transition delay. Compared with the existing technology that does not carry the clock signal and requires an adaptive clock on the opposite end chip, the difficulty of recovering the clock is reduced and the time is reduced. Reduces data transmission delay.

The destination chip 200 may cooperate with the above-mentioned source chip 100. The target chip 200 includes a first comparator 210 , a second comparator 220 , a clock recovery circuit 230 , a data recovery circuit 240 and a serial-to-parallel conversion module 203 .

The first comparator 210 is used to receive the encoded data sent by the chip of the opposite end, compare the encoded data with the first reference level, and output the encoded data higher than the first reference level as a high level, and output the encoded data lower than the first reference level as a high level. The output of the reference level is low level, and the first waveform is obtained. Wherein, the first reference level is between the middle level and the high level.

The second comparator 220 is used to receive the encoded data, compare the encoded data with the second reference level, and output the encoded data higher than the second reference level as a high level, and output the encoded data lower than the second reference level. is low level, the second waveform is obtained. Wherein, the second reference level is between the middle level and the low level.

Referring to FIG. 6 , the first reference level may be a dotted line represented by D1 of the encoded data position in FIG. 6 , and the second reference level may be a dotted line represented by D2 of the encoded data position in FIG. 6 . FIG. 7 shows the first waveform amp_h obtained by processing the encoded data by the first comparator 210, and the second waveform amp_l obtained by processing the encoded data by the second comparator 220.

Next, the method in which the first comparator 210 obtains the first waveform according to the encoded data is described in detail:

Let’s take the first four digits of the LHLM encoded data as an example, see Figure 6:

The first digit L is lower than the first reference level D1 of the first comparator 210, then the output is 0;

The second digit H is higher than the first reference level D1 of the first comparator 210, then the output is 1;

The third digit L is lower than the first reference level D1 of the first comparator 210, then the output is 0;

If the fourth digit M is lower than the first reference level D1 of the first comparator 210, the output is 0;

Therefore, the first waveform corresponding to the first four digits of LHLM of the encoded data is 0100.

Each number of the encoded data can be judged to obtain the complete first waveform amp_h corresponding to the complete encoded data.

Next, the method in which the second comparator 220 obtains the second waveform according to the encoded data is described in detail:

Let’s also take the first four digits of the encoded data LHLM as an example, see Figure 6:

The first digit L is lower than the second reference level D2 of the second comparator 220, then the output is 0;

The second digit H is higher than the second reference level D2 of the second comparator 220, then the output is 1;

The third digit L is lower than the second reference level D2 of the second comparator 220, then the output is 0;

If the fourth digit M is higher than the second reference level D2 of the second comparator 220, the output is 1;

Therefore, the second waveform corresponding to the first four digits of LHLM of the encoded data is 0101.

The complete second waveform amp_l corresponding to the complete coded data can be obtained by judging each number of the coded data.

The clock recovery circuit 230 is configured to acquire the waveform inversion pulse of the first waveform and the waveform inversion pulse of the second waveform, and perform a combined processing on the acquired pulses to obtain the clock recovery signal RXCLK.

Referring to FIG. 7 , the clock recovery circuit 230 includes at least a first delayer 231 , a first XOR operator 232 , at least a second delayer 233 , a second XOR operator 234 , an OR operator 235 and two Divider 236.

At least one first delayer 231 is connected in sequence for delaying the first waveform amp_h and transmitting the delayed first waveform to the first XOR operator 232 . Wherein, the delay time of the at least one first delayer 231 for the first waveform is greater than the sum of the change time of the rising edge of the first waveform and the change time of the falling edge of the first waveform.

The first XOR operator 232 is used to perform an XOR operation on the first waveform and the delayed first waveform to obtain the first pulse waveform edge_h. The first delayer 231 is used to delay the first waveform, and the first XOR operator 232 performs XOR processing on the delayed first waveform and the first waveform to obtain a pulse signal of the first waveform at the flip position. The resulting waveform can be recorded as the first pulse waveform.

At least one second delayer 233 is connected in sequence for delaying the second waveform amp_1, and transmitting the delayed second waveform to the second XOR operator 234. Wherein, the delay time of at least one second delayer 233 for the second waveform is greater than the sum of the change time of the rising edge of the second waveform and the change time of the falling edge of the second waveform.

The second XOR operator 234 is used to perform an XOR operation on the second waveform and the delayed second waveform to obtain the second pulse waveform edge_l. The second XOR operator 234 performs XOR processing on the delayed second waveform and the second waveform to obtain a waveform composed of the pulse signal of the second waveform at the flip position, and this waveform is recorded as the second pulse waveform.

The OR operator 235 is used to perform OR processing on the first pulse waveform and the second pulse waveform to obtain a pulse fusion waveform, where the pulse fusion waveform is the clock recovery signal edge_h|edge_l.

Take the OR set of the first pulse waveform and the second pulse waveform to obtain the pulse fusion waveform edge_h|edge_l. The time interval between two adjacent pulses of the pulse fusion waveform edge_h|edge_l is equal to the time interval between two adjacent data in the encoded data. The time interval between them is the same, so the pulse fusion waveform is the clock recovery signal.

The frequency divider 236 is used to divide the clock recovery signal by two to obtain the clock recovery signal RXCLK with a duty cycle of 50%.

Both the rising and falling edges of the clock recovery signal RXCLK can trigger signal acquisition. Since the clock is recovered from the encoded data, the jitter characteristics of the clock are consistent with the encoded data, and the difficulty of data recovery is also reduced.

After obtaining the clock recovery signal, the clock recovery signal can also be divided by two through the frequency divider 236 to obtain a clock recovery signal with a duty cycle of 50%. The clock recovery signal processed by dividing by two is more stable.

The data recovery circuit 240 is used to collect encoded data according to the clock recovery signal and restore the encoded data into serial data.

The data recovery circuit 240 is specifically used to: determine that the current data received is an intermediate level state; obtain the level state of the previous data of the current data, and use the level state of the previous data as the level state of the current data. flat state.

When the data recovery circuit 240 recovers the encoded data into serial data, it can collect the encoded data according to the frequency of the clock recovery signal, and determine whether the current data received is based on the comparison results of the first comparator 210 and the second comparator 220. In the intermediate level state, if not, the high level will return to 1 corresponding to the high level, and the low level will return to 0 corresponding to the low level. If the current data is in an intermediate level state, the level state of the previous data is obtained, and the value corresponding to the current data is determined based on the level state of the previous data. This recovery process is simple and requires little calculation.

The serial-to-parallel conversion module 203 is used to convert the serial data recovered by the data recovery circuit 240 into four channels of parallel data.

Through the cooperation of the first comparator 210, the second comparator 220 and the clock recovery circuit 230, the clock signal can be recovered from the encoded data. Compared with the existing technology, the circuit structure of the recovered clock signal is simple and reduces the cost of recovering the clock signal. The difficulty reduces the delay of data transmission.

Please refer to Figure 9. Figure 9 shows a data transmission method provided by an embodiment of the present application. The method is applied to the above-mentioned source chip 100, and specifically includes the following steps S110 to step S120:

Step S110: The data encoding module of the source chip receives serial data, encodes the serial data to obtain encoded data, and transmits the encoded data to the driver of the source chip, wherein any phase of the encoded data There is a transition delay between two adjacent data.

In step S120, the driver receives the encoded data and sends the encoded data to the destination chip of the opposite end, so that the destination chip of the opposite end processes the encoded data.

The data encoding module 110 can encode the serial data to obtain encoded data, so as to achieve a jump delay between any two adjacent data of the encoded data. Since there is a transition delay between any two adjacent pieces of data, each time the chip at the opposite end receives a piece of data, it can be informed by the change in the transition delay. That is, each change in transition delay corresponds to a receiving data. The received data is equivalent to using encoded data to realize the transmission of clock signals. By encoding the serial data, the encoded data carries the clock signal through the change of transition delay. Compared with the existing technology that does not carry the clock signal and requires an adaptive clock on the opposite end chip, the difficulty of recovering the clock is reduced and the time is reduced. Reduces data transmission delay.

Optionally, in a specific implementation, step S110 specifically includes the following steps: receiving current data; determining whether the level state corresponding to the current data is consistent with the level state corresponding to the previous data of the current data; If yes, encode the current data to an intermediate level; if not, retain the level state corresponding to the current data.

The level state of the current data can be compared with the level state of the previous data to determine whether the level states of the two are consistent. If they are consistent, the level state of the current data will be represented by the middle level. If they are inconsistent, the current level state will be retained. The original level state of the data. Through the introduction of intermediate levels, when two adjacent data are at the same level, the level state of the latter data in the two adjacent data can be changed, so that the same level will not appear in the two adjacent data. Condition.

Optionally, in another specific implementation, step S110 specifically includes the following steps: performing a bit-to-bit exclusive OR operation on the serial data and the serial data that has been delayed by one clock cycle to obtain the operation result. ; If the operation result is 0, it is determined that the level of the data of the corresponding bit of the serial data is the original level; if the operation result is 1, it is determined whether the level state of the previous bit of data is the intermediate level. If the level state of the previous bit of data is the middle level, then it is determined that the level of the data of the corresponding bit of the serial data is the original level; if the level state of the previous bit of data is not the middle level, Then it is determined that the data level of the corresponding bit of the serial data is the middle level.

The first digital flip-flop 111 can delay the serial data by one clock cycle, perform an exclusive OR operation on the serial data and the serial data delayed by one clock cycle, and obtain the operation result. According to the specific operation result and the level state of the previous bit of data, the level state of the bit of data can be determined. If the operation result is 0, it means that the level state of the current bit data is different from the level state of the previous bit data, and the original level of the bit data can be directly output. If the operation result is 1, it means that the level state of the current bit data is the same as the actual level state of the previous bit data. It needs to be further determined: whether the level state of the previous bit data has been changed to an intermediate level. If the level state of the previous bit of data is changed to the middle level, the level state of the current bit of data does not need to be modified, and the original level can be output directly to distinguish it from the level state of the previous bit of data; If the level state of the previous bit of data has not been changed to the middle level, the level state of the current bit of data needs to be modified to the middle level to distinguish it from the level state of the previous bit of data.

Please refer to Figure 10. Figure 10 shows a data transmission method provided by an embodiment of the present application. The method is applied to the above-mentioned destination chip 200, and specifically includes the following steps S210 to step S240:

Step S210: The first comparator of the destination chip receives the encoded data sent by the source chip of the opposite end, compares the encoded data with the first reference level, and compares the encoded data that is higher than the first reference level. The output is high level, and the output lower than the first reference level is low level, a first waveform is obtained, and the first waveform is transmitted to the clock recovery circuit of the target chip.

Wherein, the first reference level is between an intermediate level and a high level.

Step S220: The second comparator of the destination chip receives the encoded data, compares the encoded data with the second reference level, and outputs the encoded data that is higher than the second reference level as a high level. level, the output lower than the second reference level is low level, a second waveform is obtained, and the second waveform is transmitted to the clock recovery circuit of the destination chip.

Wherein, the second reference level is between the intermediate level and the low level.

Step S230: The clock recovery circuit obtains the waveform inversion pulse of the first waveform and the waveform inversion pulse of the second waveform, performs a union process on the obtained pulses, obtains a clock recovery signal, and restores the clock. The signal is transmitted to the data recovery circuit of the destination chip.

Optionally, please refer to Figure 11. In a specific implementation, step S230 may include the following steps S231 to step S236:

Step S231: At least one first delayer 231 delays the first waveform.

Step S232, the first XOR operator 232 performs an XOR operation on the first waveform and the delayed first waveform to obtain a first pulse waveform, wherein the first pulse waveform is the waveform of the first waveform. Flip the waveform of the corresponding pulse signal.

Step S233, at least one second delayer 233 delays the second waveform.

Step S234, the second XOR operator 234 performs an XOR operation on the second waveform and the delayed second waveform to obtain a second pulse waveform, wherein the second pulse waveform is the waveform of the second waveform. Flip the waveform of the corresponding pulse signal.

In step S235, the OR operator 235 performs OR processing on the first pulse waveform and the second pulse waveform to obtain a pulse fusion waveform, and the pulse fusion waveform is the clock recovery signal.

The first XOR operator 232 performs XOR processing on the delayed first waveform and the first waveform, and can obtain a waveform composed of the pulse signal of the first waveform at the flip position, which waveform can be recorded as the first pulse waveform. The second XOR operator 234 performs XOR processing on the delayed second waveform and the second waveform to obtain a waveform composed of the pulse signal of the second waveform at the flip position, and this waveform is recorded as the second pulse waveform. Take the OR set of the first pulse waveform and the second pulse waveform to obtain the pulse fusion waveform. The time interval between two adjacent pulses of the pulse fusion waveform is the same as the time interval between two adjacent data in the encoded data. Therefore, this pulse fusion waveform is the clock recovery signal.

In step S236, the frequency divider 236 divides the clock recovery signal by two to obtain a clock recovery signal with a duty cycle of 50%.

The clock recovery signal is divided by two through the frequency divider 236 to obtain a clock recovery signal with a duty cycle of 50%. The clock recovery signal processed by dividing by two is more stable.

Step S240: The data recovery circuit collects the encoded data according to the clock recovery signal and recovers the encoded data into serial data.

Optionally, step S240 specifically includes the following steps: determining that the current data received is an intermediate level state; obtaining the level state of the previous data of the current data, and using the level state of the previous data as the current level state. The level status of the data.

When recovering the encoded data into serial data, the data recovery circuit 240 can collect the encoded data according to the frequency of the clock recovery signal, and determine whether the current data received is an intermediate circuit based on the comparison results of the first comparator and the second comparator. If not, the high level will return to 1 corresponding to the high level, and the low level will return to 0 corresponding to the low level. If the current data is in an intermediate level state, the level state of the previous data is obtained, and the value corresponding to the current data is determined based on the level state of the previous data. This recovery process is simple and requires little calculation.

In the embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components may be combined or can be integrated into another system, or some features can be ignored, or not implemented. On the other hand, the coupling or direct coupling or communication connection between each other shown or discussed may be through some communication interfaces, and the indirect coupling or communication connection of the devices or units may be in electrical, mechanical or other forms.

In addition, units described as separate components may or may not be physically separated, and components shown as units may or may not be physical units, that is, they may be located in one place, or they may be distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

Furthermore, each functional module in each embodiment of the present application can be integrated together to form an independent part, each module can exist alone, or two or more modules can be integrated to form an independent part.

In this document, relational terms such as first, second, etc. are used merely to distinguish one entity or operation from another entity or operation and do not necessarily require or imply the existence of any such entity or operation between these entities or operations. Actual relationship or sequence.

The above descriptions are only examples of the present application and are not intended to limit the scope of protection of the present application. For those skilled in the art, the present application may have various modifications and changes. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this application shall be included in the protection scope of this application.

Claims (11)

1. A source chip, characterized in that it includes a data encoding module and a driver, and the data encoding module is connected to the driver; The data encoding module is used to receive serial data, encode the serial data to obtain encoded data, and transmit the encoded data to the driver, wherein any two adjacent data of the encoded data There is a jump delay between them; The driver is used to receive the encoded data and send the encoded data to the destination chip of the opposite end, so that the destination chip of the opposite end can adjust the encoding according to the jump delay between any two adjacent data. data, restoring the encoded data to the serial data; Wherein, the serial data is encoded to obtain encoded data, including: Perform a bit-to-bit exclusive OR operation on the serial data and the serial data that has been delayed by one clock cycle to obtain the operation result; If the operation result is 0, then it is determined that the data level of the corresponding bit of the serial data is the original level; If the operation result is 1, determine whether the level state of the previous bit of data in the serial data is an intermediate level; If the level state of the previous bit of data is an intermediate level, then it is determined that the level of the data of the corresponding bit of the serial data is the original level; If the level state of the previous bit of data is not an intermediate level, it is determined that the level of the data of the corresponding bit of the serial data is an intermediate level. 2. The source chip according to claim 1, characterized in that the data encoding module is used to receive serial data and encode the serial data to obtain encoded data, specifically including: Receive current data; Determine whether the level state corresponding to the current data is consistent with the level state corresponding to the previous data of the current data; If so, encode the current data into an intermediate level; If not, the current data is encoded into a level state consistent with the current data. 3. The source chip according to claim 1, characterized in that the data encoding module includes a first digital flip-flop, a second digital flip-flop, an exclusive OR operator and a selector; The CLK end of the first digital flip-flop is connected to a clock signal line that transmits a clock signal, the input end of the first digital flip-flop is connected to a serial data line that transmits serial data, and the output end of the first digital flip-flop is Connected to the first input end of the XOR operator; The second input end of the XOR operator is connected to the serial data line, and the output end of the XOR operator is connected to the first input end of the selector; The output end of the selector is connected to the input end of the second digital flip-flop; The output terminal of the second digital flip-flop is connected to the second input terminal of the selector, and the CLK terminal of the second digital flip-flop is connected to the clock signal line. 4. The source chip according to claim 3, characterized in that the XOR operator is used to perform bit-AND operation on the serial data and the serial data delayed by one clock cycle through the first digital flip-flop. The same-or operation between them obtains the operation result; If the operation result is 0, use the selector to determine that the level of the bit in the serial data corresponding to the operation result in the corresponding bit in the encoded data is the original level; If the operation result is 1, based on the output result of the second digital flip-flop, it is determined whether the level state of the encoded data corresponding to the previous bit of the serial data is an intermediate level. 5. A destination chip, characterized in that, in cooperation with the source chip according to any one of claims 1-4, it includes a first comparator, a second comparator, a clock recovery circuit and a data recovery circuit; The first comparator is used to receive the encoded data sent by the source chip of the opposite end, compare the encoded data with the first reference level, and output the encoded data higher than the first reference level as high level, the output lower than the first reference level is low level, and the first waveform is obtained, wherein the first reference level is between the middle level and the high level; The second comparator is used to receive the encoded data, compare the encoded data with a second reference level, and output the encoded data that is higher than the second reference level as high level and low level. When the output of the second reference level is low level, a second waveform is obtained, wherein the second reference level is between the intermediate level and the low level; The clock recovery circuit is used to obtain the waveform inversion pulse of the first waveform and the waveform inversion pulse of the second waveform, and perform a combined processing on the obtained pulses to obtain a clock recovery signal; The data recovery circuit is used to collect the encoded data according to the clock recovery signal and restore the encoded data into serial data. 6. The target chip according to claim 5, characterized in that the clock recovery circuit includes at least a first delayer, a first XOR operator, at least a second delayer, a second XOR operator operator and OR operator; The at least one first delayer is used to delay the first waveform; The first XOR operator is used to perform an XOR operation on the first waveform and the first waveform delayed by the at least one first delayer to obtain a first pulse waveform; The at least one second delayer is used to delay the second waveform; The second XOR operator is used to perform an XOR operation on the second waveform and the second waveform delayed by the at least one second delayer to obtain a second pulse waveform; The OR operator is used to perform OR processing on the first pulse waveform and the second pulse waveform to obtain a pulse fusion waveform, and the pulse fusion waveform is the clock recovery signal. 7. The target chip according to claim 6, characterized in that the clock recovery circuit further includes a two-frequency divider, and the CLK terminal of the two-frequency divider is connected to the output terminal of the OR operator; The frequency divider is used to divide the clock recovery signal by two to obtain a clock recovery signal with a duty cycle of 50%. 8. The target chip according to claim 5, characterized in that the data recovery circuit is used to collect the encoded data according to the clock recovery signal and restore the encoded data into serial data, specifically including: Determine that the current data received is in the intermediate level state; Obtain the level state of the previous data of the current data, and use the level state of the previous data as the level state of the current data. 9. A data transmission method, characterized in that it is applied to the source chip, and the method includes: The data encoding module of the source chip receives serial data, encodes the serial data to obtain encoded data, and transmits the encoded data to the driver of the source chip, wherein any adjacent part of the encoded data There is a transition delay between the two data; The driver receives the encoded data and sends the encoded data to the destination chip of the opposite end, so that the destination chip of the opposite end processes the encoded data; Wherein, the serial data is encoded to obtain encoded data, including: Perform a bit-to-bit exclusive OR operation on the serial data and the serial data that has been delayed by one clock cycle to obtain the operation result; If the operation result is 0, then it is determined that the data level of the corresponding bit of the serial data is the original level; If the operation result is 1, determine whether the level state of the previous bit of data in the serial data is an intermediate level; If the level state of the previous bit of data is an intermediate level, then it is determined that the level of the data of the corresponding bit of the serial data is the original level; If the level state of the previous bit of data is not an intermediate level, it is determined that the level of the data of the corresponding bit of the serial data is an intermediate level. 10. A data transmission method, characterized in that it is applied to a destination chip, and the method includes: The first comparator of the destination chip receives the encoded data sent by the source chip of the opposite end, compares the encoded data with the first reference level, and outputs the encoded data that is higher than the first reference level. is a high level, and the output lower than the first reference level is a low level, a first waveform is obtained, and the first waveform is transmitted to the clock recovery circuit of the target chip, wherein the first The reference level is between mid-level and high level; The second comparator of the destination chip receives the encoded data, compares the encoded data with a second reference level, and outputs the encoded data that is higher than the second reference level as a high level. , the output lower than the second reference level is low level, a second waveform is obtained, and the second waveform is transmitted to the clock recovery circuit of the destination chip, wherein the second reference level is Between the middle level and the low level; The clock recovery circuit acquires the waveform inversion pulse of the first waveform and the waveform inversion pulse of the second waveform, and processes the acquired pulses to obtain a clock recovery signal, and converts the clock recovery signal Transmitted to the data recovery circuit of the destination chip; The data recovery circuit collects the encoded data according to the clock recovery signal and recovers the encoded data into serial data. 11. A processor system, characterized by comprising the source chip according to any one of claims 1-4 and the destination chip according to any one of claims 5-8.