CN112416723A - CPU fault detection-based result type number display method and board card - Google Patents
CPU fault detection-based result type number display method and board card Download PDFInfo
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Abstract
The present specification provides a CPU fault detection-based result type number display method and a board card, where the method includes: the method comprises the steps that a plurality of CPUs are connected with the same programmable logic device, the CPUs send detection result type numbers of fault detection to the programmable logic device, the programmable logic device drives a group of nixie tube display devices connected with the programmable logic device to display the result type numbers sent by at least two different CPUs in a grading mode, and the result type numbers sent by different CPUs are represented in different modes during display each time. Through the board card, the technical effect that the detection result is output and displayed to technicians in a numbering form is achieved.
Description
Technical Field
The specification relates to the technical field of computer application, in particular to a CPU fault detection-based result type number display method and a board card.
Background
A large data Processing device (such as a switch, a firewall, a storage device, etc.) often has multiple Central Processing Units (CPUs) on a board. And the CPU can detect faults in the starting process, output the detection result and display the detection result to a technician in a numbering form.
Disclosure of Invention
In order to solve the problem that detection results need to be displayed to technicians in a serial number mode in the related art, the specification provides a result type serial number display method and a board card based on CPU fault detection.
According to a first aspect of the embodiments of the present specification, there is provided a board card applied to a data processing device, the board card including: programmable logic device, digital tube display device and N CPUs, N is greater than 1; the N CPUs are respectively connected with the programmable logic device, and the nixie tube display device is connected with the programmable logic device;
each CPU executes fault detection in the starting process and sends a result type number corresponding to a detection result to the programmable logic device;
the programmable logic device controls the nixie tube display device to display result type numbers sent by at least two CPUs based on control logic written in advance, and the method comprises the following steps: and controlling the nixie tube display device to display the result type numbers sent by different CPUs in different modes.
According to a second aspect of the embodiments of the present specification, there is provided a method for displaying a result type number based on CPU fault detection, where the board includes: programmable logic device, digital tube display device and N CPUs, N is greater than 1; the N CPUs are respectively connected with the programmable logic device, and the nixie tube display device is connected with the programmable logic device;
each CPU executes fault detection in the starting process and sends a result type number corresponding to a detection result to the programmable logic device;
the programmable logic device controls the nixie tube display device to display result type numbers sent by at least two CPUs based on control logic written in advance, and the method comprises the following steps: and controlling the nixie tube display device to display the result type numbers sent by different CPUs in different modes.
According to a third aspect of the embodiments of the present specification, there is provided a processing apparatus having the board card according to any one of the embodiments of the first aspect of the embodiments of the present specification.
In the embodiment of the specification, a plurality of CPUs are connected with the same programmable logic device, the CPUs transmit the detection result type numbers of the fault detection to the programmable logic device, the programmable logic device drives a group of nixie tube display devices connected with the programmable logic device to display the result type numbers transmitted by at least two different CPUs in a time division manner, and the result type numbers transmitted by different CPUs are represented in different forms during each display. Through the board card, the technical effect that the detection result is output and displayed to technicians in a numbering form is achieved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the specification.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present specification and together with the description, serve to explain the principles of the specification.
Fig. 1 is a schematic connection diagram of a board card shown in this specification according to an exemplary embodiment.
Fig. 2 is a schematic connection diagram of another board card shown in this specification according to an exemplary embodiment.
Fig. 3A is a schematic diagram of a seven-segment digital tube in an embodiment of the present disclosure.
Fig. 3B is a schematic diagram of an eight-segment nixie tube in an embodiment of the present disclosure.
Fig. 3C is a schematic diagram of a nine-segment nixie tube in the embodiment of the present disclosure.
Fig. 4 is a schematic diagram of a digital tube display device on a board card according to an embodiment of the present disclosure.
Fig. 5 is a flowchart illustrating a method for displaying a result type number based on CPU failure detection according to an exemplary embodiment of the present specification.
Detailed Description
Generally, a large-scale data processing device (such as a switch, a firewall, a storage device, and the like) is provided with boards, and in order to improve system performance, some boards are provided with a plurality of CPUs. And in the starting process of the CPU, fault detection is carried out, and the detection result is output and displayed to a technician in a numbering form.
In the implementation process, as shown in a connection diagram of the CPU, the driving chip and the nixie tube display device on the board card shown in fig. one, taking four CPUs on the board card as an example, for each CPU, the result type number of the detection result may be output to the driving chip corresponding to the CPU, and then the driving chip drives the nixie tube display device to display the result type number. Wherein, drive chip and digital tube display device are all fixed on the mainboard. In the implementation scheme, because a drive chip and a nixie tube display device are required to be configured for each CPU, four drive chips and four nixie tube display devices are required for four CPUs, so that the complexity of layout and wiring on the board card is greatly increased, and the design difficulty is increased; the more complex devices on the board card, the more unstable the system carried on the board card, and this way, a large number of devices are added and a large amount of layout and wiring space is occupied, thus reducing the stability of the system; in addition, the added devices for displaying the test results increase the material cost of production.
Based on this, in the embodiments of this specification, a plurality of CPUs are connected to the same programmable logic device, the CPUs transmit the detection result type numbers of their fault detections to the programmable logic device, a control logic written in advance on the programmable logic device drives a nixie tube display device connected thereto to display the result type numbers transmitted by at least two different CPUs in a separate manner, and in each display, the result type numbers transmitted by different CPUs are represented in different patterns. Through the board card, devices for displaying detection results are reduced, the design difficulty is reduced, the system stability is improved, and the material cost is reduced.
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present specification. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the specification, as detailed in the appended claims.
The terminology used in the description herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the description. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, these information should not be limited to these terms. These terms are only used to distinguish one type of information from another. For example, the first information may also be referred to as second information, and similarly, the second information may also be referred to as first information, without departing from the scope of the present specification. The word "if" as used herein may be interpreted as "at … …" or "when … …" or "in response to a determination", depending on the context.
The following provides a detailed description of examples of the present specification.
As shown in fig. 2, fig. 2 is a schematic connection diagram of a board shown in this specification according to an exemplary embodiment, where the board is applied to a data processing device, and the board includes: programmable logic device, digital tube display device and N CPUs, N is greater than 1; the N CPUs are respectively connected with the programmable logic device, and the nixie tube display device is connected with the programmable logic device.
Compared with the board card shown in fig. 1, the driving chip can only drive a certain nixie tube display device to display a fixed numerical value, and the programmable logic device can flexibly write different control logics into the nixie tube display device, so that the nixie tube display device can realize more complex functions. In one or more embodiments of the present description, the programmable logic device may drive the nixie tube display device to display result type numbers sent by different CPUs in a time-sharing manner according to control logic written in advance to the drive chip. The Programmable logic device may be a Complex Programmable Logic Device (CPLD) or a Field Programmable Gate Array (FPGA).
Wherein, a nixie tube display device includes at least one data tube composed of a group of Light Emitting Diodes (LEDs), which is commonly called as LED nixie tubes (hereinafter, nixie tubes), each nixie tube may be seven-segment nixie tubes (including seven LEDs, which can display a number or letter, as shown in fig. 3A), eight-segment nixie tubes (including eight LEDs, which can display a number or letter, and a decimal point, as shown in fig. 3B), or nine-segment nixie tubes (including nine LEDs, which can display a number or letter, and a colon, as shown in fig. 3C). A seven-segment nixie tube may typically display ten numbers from 0 to 9, and a-Z26 letters.
Each CPU may be connected to the programmable logic device through an LPC Bus (Low pin count Bus), which means that each CPU transmits data to the programmable logic device through the LPC Bus.
And each CPU executes fault detection in the starting process and sends a result type number corresponding to the detection result to the programmable logic device.
During the starting process of the CPU, fault detection is required, and whether a register, a port, or the like is normally started or not is determined, which is also called debug (debug). When the fault detection is carried out, the detection can be carried out in sequence according to a preset fault checking sequence. If the fault exists, the result type number (also called debug signal) corresponding to the fault can be transmitted to the programmable logic device through the debug interface, and if the fault does not exist, the result type number corresponding to the normal starting is sent to the programmable logic device. The result type number is a general number and can be displayed by a nixie tube. The result type number may be two hexadecimal data, and in this case, 00 or FF may be used to represent the current normal start; the result type number may also be one or more decimal, binary data.
The programmable logic device controls the nixie tube display device to display result type numbers sent by at least two CPUs based on control logic written in advance, and the method comprises the following steps: and controlling the nixie tube display device to display the result type numbers sent by different CPUs in different modes.
Before starting the CPU, a preset control logic needs to be written in the programmable logic device. According to the display requirement, the control logic is written into the programmable logic device in advance, so that the programmable logic device drives the digital tube display device to display the result type numbers sent by all CPUs. The programmable logic device can also be enabled to display only part of the result type numbers sent by the CPU. For example, a technician may replace two CPUs on a board card, and may write control logic to a programmable logic device to drive a nixie tube display device to display result type numbers sent by the two CPUs to be tested, if the replaced CPUs need to be tested and can be started normally. Or, in order to facilitate quick errors of technicians, when the CPLD judges that the result type numbers sent by all the CPUs are normal starting numbers, the digital tube display device can be driven to always display the numbers representing that all the CPUs are normally started. In addition, when the CPLD receives the result type numbers and determines that the result type numbers sent by some CPUs are normal starting numbers and the result type numbers sent by other CPUs are failure numbers, only the result type numbers sent by the failed CPUs can be displayed.
After the programmable logic device receives the data sent by each CPU, if the data transmitted through the bus needs a specific data form, the CPLD needs to analyze the result type number from the received data according to the bus protocol. After the result type number sent by each CPU is obtained through analysis, the result type number sent by each CPU may be stored in a cache space of the programmable logic device, so that the CPLD may invoke the result type number to be displayed from the cache in the subsequent process of driving the nixie tube display device to display the result type number.
According to the control logic written into the programmable logic device, in one or more embodiments of the present specification, it is necessary to implement displaying result type numbers sent by different CPUs in a time division manner, and in each time of displaying, according to a different pattern displayed in each time, it is possible to distinguish which CPU result type number is displayed under the pattern display.
The controlling of the nixie tube display device to display the result type numbers sent by the different CPUs in a grading manner may be controlling of the nixie tube display device to display the result type numbers sent by the different CPUs in a grading manner based on a fixed time interval, for example, the time interval of each display may be set to be 1 s. The display device of the nixie tube can also be controlled to display the result type numbers sent by different CPUs in sequence, for example, the display device of the nixie tube can be driven to display according to the sequence of the CPU numbers from small to large, and can also display according to the sequence of the CPU numbers from large to small.
When the result type numbers are displayed, if the result type numbers sent by different CPUs are sequentially displayed in sequence, the result type numbers of the CPUs can be circularly displayed according to the result type number of each CPU stored in the CPLD.
Wherein, controlling the nixie tube display device to display result type numbers sent by different CPUs in different modes can be: the nixie tube display device also comprises at least one nixie tube for displaying the serial number of the CPU; and the programmable logic device controls the nixie tube to display the CPU number of the CPU when controlling the nixie tube display device to display the result type number sent by the CPU aiming at each CPU in the at least two CPUs. The nixie tube display device also comprises at least one light-emitting diode which represents the number of the CPU through the on/off state; and the programmable logic device controls the at least one light-emitting diode to represent the CPU number of the CPU when controlling the nixie tube display device to display the result type number sent by the CPU aiming at each CPU in the at least two CPUs. The method can also be as follows: and the programmable logic device controls at least one light-emitting diode to flash at a certain frequency to represent the CPU number of the CPU when controlling the nixie tube display device to display the result type number sent by the CPU aiming at each CPU in at least two CPUs, and the flashing frequencies are different when displaying the result type numbers sent by different CPUs.
Specifically, for example, 4 CPUs are installed on a board card, in the first method, all nixies in a nixie tube display device may be seven-segment nixies, and the nixie tube display device further includes 1 nixie tube for displaying a CPU number, and for a result type number sent by a certain CPU, when other nixie tubes display the result type number, the nixie tube displays a CPU number corresponding to the CPU, so that a technician can know which nixie tube the current result type number is sent by according to the number displayed by the nixie tube. In the second method, as shown in fig. 4, the nixie tube display device for displaying the result type number may include two eight nixie tubes, where both the two eight nixie tubes include a light emitting diode capable of displaying a decimal point, and when the two eight nixie tubes display the result type number sent by a certain CPU, the nixie tube for displaying the decimal point may indicate which specific CPU the currently displayed result type number belongs to through the display state shown in table 1, and a technician may know which CPU the current decimal point display state represents according to a preset corresponding relationship between the decimal point display state and the CPU number. In the third method, the nixie tube display device for displaying the result type number may include two seven-segment nixie tubes, and when the two seven-segment nixie tubes display the result type number sent by a certain CPU, at least one of the nixie tubes may indicate which specific CPU the currently displayed result type number belongs to according to the blinking frequency shown in table 2, and a technician may know which CPU the currently displayed frequency indicates according to the pre-configured correspondence relationship between the blinking frequency and the CPU number.
| Decimal point display state | CPU numbering |
| Quan Liang | 1 |
| First on and second off | 2 |
| First off and second on | 3 |
| All-round extinguishing | 4 |
TABLE 1
| Digital tube flicker frequency/Hz | CPU numbering |
| 1 | 1 |
| 2 | 2 |
| 3 | 3 |
| 4 | 4 |
TABLE 2
For example, a board card is provided with 4 CPUs, a CPLD and a nixie tube display device, wherein the nixie tube display device comprises 3 seven-segment nixie tubes; the 4 CPUs are respectively connected with the CPLD through LPC buses, and the CPLD is connected with a nixie tube display device through a lead on the board card.
And the CPU detects the fault in the starting process and sends a result type number corresponding to the fault detection result to the CPLD through the LPC bus. Wherein the result type number is represented by a two-digit 16-ary number, wherein 00 or FF indicates no fault. Before the CPU is started, the correspondence between the detection result and the result type number needs to be stored in advance, so that a technician can search for a corresponding fault from the correspondence according to the displayed result type number.
After receiving the fault detection results sent by all CPUs, the CPLD controls the nixie tube display device to display the result type numbers sent by all CPUs based on the control logic written in advance, and the method comprises the following steps: and controlling two nixie tubes close to the left in the nixie tube display device, sequentially displaying the result type number sent by each CPU according to the positive sequence of the CPU number, and simultaneously displaying the CPU number through the other nixie tube, wherein the time displayed by the three nixie tubes each time is 1 s.
In one or more embodiments of the present description, a plurality of CPUs are connected to the same programmable logic device, the CPUs transmit detection result type numbers of their failure detections to the programmable logic device, the programmable logic device drives a nixie tube display device connected thereto to display the result type numbers transmitted by at least two different CPUs in a time division manner, and in each display, the result type numbers transmitted by different CPUs are represented in different forms. Through the board card, devices for displaying detection results are reduced, the design difficulty is reduced, the system stability is improved, and the material cost is reduced.
The embodiment of the present specification further shows a data processing device, which has the board card in one or more embodiments described above.
As shown in fig. 5, fig. 5 is a flowchart of a method for displaying a result type number based on CPU fault detection according to an exemplary embodiment, where the method is applied to a board, and the board includes: programmable logic device, digital tube display device and N CPUs, N is greater than 1; the N CPUs are respectively connected with the programmable logic device, and the nixie tube display device is connected with the programmable logic device;
the method comprises the following steps:
Further, controlling the nixie tube display device to display result type numbers sent by different CPUs in a time-sharing manner specifically comprises: and controlling the nixie tube display device to sequentially display the result type numbers sent by different CPUs.
Further, the nixie tube display device also comprises at least one nixie tube for displaying the serial number of the CPU; controlling the nixie tube display device to display result type numbers sent by different CPUs in different modes, specifically comprising: and for each CPU in the at least two CPUs, controlling the nixie tube to display the CPU number of the CPU when controlling the nixie tube display device to display the result type number sent by the CPU.
Embodiments of the present specification further provide a storage medium readable by a programmable logic device, on which a program of the programmable logic device is stored, and when the program is executed by a processor, the method for displaying the result type number based on the CPU fault detection is implemented. The method at least comprises the following steps:
the programmable logic device receives a result type number sent by the CPU; and controlling the nixie tube display device to display the result type numbers sent by different CPUs in different modes.
Computer-readable media, including both non-transitory and non-transitory, removable and non-removable media, may implement information storage by any method or technology. The information may be computer readable instructions, data structures, modules of a program, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), other types of Random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), Digital Versatile Discs (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. As defined herein, a computer readable medium does not include a transitory computer readable medium such as a modulated data signal and a carrier wave.
The foregoing description has been directed to specific embodiments of this disclosure. Other embodiments are within the scope of the following claims. In some cases, the actions or steps recited in the claims may be performed in a different order than in the embodiments and still achieve desirable results. In addition, the processes depicted in the accompanying figures do not necessarily require the particular order shown, or sequential order, to achieve desirable results. In some embodiments, multitasking and parallel processing may also be possible or may be advantageous.
Other embodiments of the present description will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This specification is intended to cover any variations, uses, or adaptations of the specification following, in general, the principles of the specification and including such departures from the present disclosure as come within known or customary practice within the art to which the specification pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the specification being indicated by the following claims.
It will be understood that the present description is not limited to the precise arrangements described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present description is limited only by the appended claims.
The above description is only a preferred embodiment of the present disclosure, and should not be taken as limiting the present disclosure, and any modifications, equivalents, improvements, etc. made within the spirit and principle of the present disclosure should be included in the scope of the present disclosure.
Claims (10)
1. The utility model provides a board card which characterized in that is applied to data processing equipment, the board card includes: programmable logic device, digital tube display device and N central processing units CPU, N is greater than 1; the N CPUs are respectively connected with the programmable logic device, and the nixie tube display device is connected with the programmable logic device;
each CPU executes fault detection in the starting process and sends a result type number corresponding to a detection result to the programmable logic device;
the programmable logic device controls the nixie tube display device to display result type numbers sent by at least two CPUs based on control logic written in advance, and the method comprises the following steps: and controlling the nixie tube display device to display the result type numbers sent by different CPUs in different modes.
2. The board of claim 1, wherein the programmable logic device is a Complex Programmable Logic Device (CPLD).
3. The board of claim 1, wherein the programmable logic device controls the nixie tube display device to sequentially display the result type numbers sent by different CPUs in sequence.
4. The board of claim 1, wherein the programmable logic device controls the nixie tube display device to display the result type numbers sent by different CPUs in a time-division manner based on a fixed time interval.
5. The board of claim 1, wherein the nixie tube display device further comprises at least one nixie tube for displaying a CPU number;
and the programmable logic device controls the nixie tube to display the CPU number of the CPU when controlling the nixie tube display device to display the result type number sent by the CPU aiming at each CPU in the at least two CPUs.
6. The board of claim 1, wherein the nixie tube display device further comprises at least one light emitting diode that indicates a CPU number by an on/off state;
and the programmable logic device controls the at least one light-emitting diode to represent the CPU number of the CPU when controlling the nixie tube display device to display the result type number sent by the CPU aiming at each CPU in the at least two CPUs.
7. A CPU fault detection-based result type number display method is characterized in that a board card comprises: programmable logic device, digital tube display device and N CPUs, N is greater than 1; the N CPUs are respectively connected with the programmable logic device, and the nixie tube display device is connected with the programmable logic device;
each CPU executes fault detection in the starting process and sends a result type number corresponding to a detection result to the programmable logic device;
the programmable logic device controls the nixie tube display device to display result type numbers sent by at least two CPUs based on control logic written in advance, and the method comprises the following steps: and controlling the nixie tube display device to display the result type numbers sent by different CPUs in different modes.
8. The method as claimed in claim 7, wherein controlling the nixie tube display device to display the result type numbers sent by different CPUs in a plurality of times specifically comprises:
and controlling the nixie tube display device to sequentially display the result type numbers sent by different CPUs.
9. The method of claim 7, wherein said nixie tube display device further comprises at least one nixie tube for displaying a CPU number;
controlling the nixie tube display device to display result type numbers sent by different CPUs in different modes, specifically comprising:
and for each CPU in the at least two CPUs, controlling the nixie tube to display the CPU number of the CPU when controlling the nixie tube display device to display the result type number sent by the CPU.
10. A data processing device having a board as claimed in any one of claims 1 to 6.
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| CN117274720A (en) * | 2023-11-16 | 2023-12-22 | 深圳市七彩虹禹贡科技发展有限公司 | Computer hardware anomaly detection method and system |
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| CN202217034U (en) * | 2011-06-03 | 2012-05-09 | 中兴通讯股份有限公司 | Single plate fault detector |
| CN104182314A (en) * | 2014-08-25 | 2014-12-03 | 浪潮集团有限公司 | Dragon core processor server motherboard maintaining method |
| CN105158684A (en) * | 2015-06-04 | 2015-12-16 | 常熟开关制造有限公司(原常熟开关厂） | Intelligent circuit breaker fault display method, intelligent circuit breaker and fault recognition terminal |
| CN106547657A (en) * | 2016-11-01 | 2017-03-29 | 郑州云海信息技术有限公司 | A kind of information display circuit, system and method |
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| CN117274720A (en) * | 2023-11-16 | 2023-12-22 | 深圳市七彩虹禹贡科技发展有限公司 | Computer hardware anomaly detection method and system |
| CN117274720B (en) * | 2023-11-16 | 2024-05-14 | 深圳市七彩虹禹贡科技发展有限公司 | Computer hardware anomaly detection method and system |
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