CN112397596A - Low-cost high-efficiency solar cell and preparation method thereof - Google Patents
Low-cost high-efficiency solar cell and preparation method thereof Download PDFInfo
- Publication number
- CN112397596A CN112397596A CN202011285647.5A CN202011285647A CN112397596A CN 112397596 A CN112397596 A CN 112397596A CN 202011285647 A CN202011285647 A CN 202011285647A CN 112397596 A CN112397596 A CN 112397596A
- Authority
- CN
- China
- Prior art keywords
- layer
- substrate
- silicon
- hydrogenated
- solar cell
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F77/00—Constructional details of devices covered by this subclass
- H10F77/30—Coatings
- H10F77/306—Coatings for devices having potential barriers
- H10F77/311—Coatings for devices having potential barriers for photovoltaic cells
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F10/00—Individual photovoltaic cells, e.g. solar cells
- H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
- H10F10/14—Photovoltaic cells having only PN homojunction potential barriers
- H10F10/146—Back-junction photovoltaic cells, e.g. having interdigitated base-emitter regions on the back side
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F71/00—Manufacture or treatment of devices covered by this subclass
- H10F71/121—The active layers comprising only Group IV materials
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F71/00—Manufacture or treatment of devices covered by this subclass
- H10F71/129—Passivating
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Landscapes
- Photovoltaic Devices (AREA)
Abstract
The invention relates to the technical field of solar cells, in particular to a low-cost and high-efficiency solar cell and a preparation method thereof, wherein the low-cost and high-efficiency solar cell comprises a substrate, a diffusion layer positioned on the upper surface of the substrate, a passivation layer positioned on the upper surface of the diffusion layer, a silicon oxide layer positioned on the lower surface of the substrate, a doped polycrystalline silicon layer positioned on the lower surface of the silicon oxide layer, a hydrogenated transparent conductive film positioned on the lower surface of the doped polycrystalline silicon layer, an upper electrode positioned on the upper surface of the passivation layer and a lower electrode positioned on the lower surface of; according to the invention, the passivation layer on the surface of the polycrystalline silicon is replaced by the hydrogenated TCO film, and the TCO film has good electrical property, can form good ohmic contact with the slurry, and does not need the slurry to burn through to contact with the polycrystalline silicon, so that the non-burn-through type slurry such as aluminum slurry can be used for replacing silver slurry, and the cost is reduced.
Description
Technical Field
The invention relates to the technical field of solar cells, in particular to a low-cost high-efficiency solar cell and a preparation method thereof.
Background
The passivated contact cell is a novel high conversion efficiency cell, and the conversion efficiency can reach 24%. The compatibility with a conventional production line is better, and the upgrading can be completed on an N-type conventional production line. Compared with heterojunction batteries and back junction batteries, the passivated contact battery has a relatively simple structure, is high in feasibility of mass production, and has certain advantages in production cost. At present, silver paste is adopted for realizing metallization of the battery, and the silver has the advantages of good conductivity, low work function, good weldability, difficulty in forming deep level defects in silicon and the like. But the price is higher because the content of the compound in the crust is low; furthermore, silver paste is often used to form ohmic contacts by etching a portion of the silicon through the glass frit therein, thus requiring thicker polysilicon films. Meanwhile, the silver paste corrodes the passivation layer and the polysilicon, so that the J0 of the area is higher than that of the non-metal contact area, and the passivation performance of the area is affected. Therefore, how to reduce or even eliminate the recombination of the metal region becomes the key of the future battery improvement.
Disclosure of Invention
The purpose of the invention is: the solar cell overcomes the defects in the prior art and has low cost and high conversion efficiency.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows:
a low-cost, high-efficiency solar cell includes a substrate,
a diffusion layer located on the upper surface of the substrate,
a passivation layer on the upper surface of the diffusion layer,
a silicon oxide layer on the lower surface of the substrate,
a doped polysilicon layer located on the lower surface of the silicon oxide layer,
a hydrogenated transparent conductive film located on the lower surface of the doped polysilicon layer,
and an upper electrode on the upper surface of the passivation layer and a lower electrode on the lower surface of the hydrogenated transparent conductive film.
According to the invention, the hydrogenated TCO film is adopted to replace a passivation layer on the surface of the polycrystalline silicon, and as the TCO film has good electrical property, the TCO film can form good ohmic contact with the slurry, and the slurry is not required to be burnt through to be in contact with the polycrystalline silicon, the non-burnt-through type slurry such as aluminum slurry can be adopted to replace silver slurry, so that the cost is reduced.
A TCO film is not adopted in a crystalline silicon battery in the prior art, because a common TCO film has good optical performance and electrical performance but poor passivation capability, the TCO film is generally used for a heterojunction or thin film battery, and because the passivation performance of amorphous silicon in the type of battery is far higher than that of the crystalline silicon battery, the amorphous silicon absorbs light seriously and causes low current, a transparent conductive film is needed to enhance the optical absorption and electrical transportation capability, so that the current is improved. The passivation performance of the crystalline silicon cell is slightly inferior to that of the crystalline silicon cell, but the optical absorption is better, so that the good passivation performance and the good electrical transport capacity are required, and the passivation capacity of the TCO film can be improved after the hydrogenation of the TCO film is creatively found in the invention.
Further, the substrate is an N-type substrate or a P-type substrate,
further, the diffusion layer is a p + layer or an n + layer,
when the diffusion layer is a p + layer, the passivation layer is a silicon oxide/aluminum oxide/silicon nitride lamination layer, the doped polysilicon layer is an n + polysilicon layer,
when the diffusion layer is n +, the passivation layer is a silicon oxide/silicon nitride lamination layer, and the doped polycrystalline silicon layer is a p + polycrystalline silicon layer.
Selection on battery structure: for example, 1) p +/p-Si/SiOx/n + poly and n +/n-Si/SiOx// p + poly structures, which are cell structures with pn junctions on the back side;
2) p +/n-Si/SiOx/n + poly and n +/p-Si/SiOx// p + poly structures, which are the cell structures with pn junctions on the front side;
when the front diffusion layer is p +, the silicon oxide/aluminum oxide/silicon nitride laminated layer can be selected as a passivation layer, and when the front diffusion layer is n +, the aluminum oxide can not be selected as one of the passivation layers, because the n + diffusion generally adopts 5-valent elements, and the aluminum is 3-valent elements, when the aluminum element enters the diffusion layer due to sintering, the two elements can compensate each other, the electron concentration is reduced, the minority carrier lifetime is reduced, and the battery efficiency is finally influenced.
Further, the hydrogenated transparent conductive film is selected from one of AZO H, IO H, IWO H and FTO H.
Furthermore, the upper electrode is made of silver paste or silver-aluminum paste, the lower electrode is made of aluminum paste, the hydrogenated TCO film is adopted to replace a passivation layer on the surface of the polycrystalline silicon, the TCO film has good electrical performance and can form good ohmic contact with the paste, the paste is not required to be burnt through to be contacted with the polycrystalline silicon, and therefore the non-burnt-through type paste such as the aluminum paste can be adopted to replace the silver paste, the cost is reduced, and meanwhile, the silver resource is saved.
Another object of the invention is: the preparation method of the high-efficiency solar cell with low cost has the advantages of simple process and low production cost.
In order to solve the technical problems, the technical scheme adopted by the invention is as follows:
a method for preparing a low-cost, high-efficiency solar cell, comprising the steps of:
texturing: texturing the substrate to form a textured structure with a light trapping effect;
diffusion: forming a diffusion layer on an upper surface of a substrate;
etching: removing the pn junction on the lower surface of the substrate;
and (3) oxidation: forming a silicon oxide layer on the lower surface of the substrate;
depositing doped polysilicon: forming doped amorphous silicon on the lower surface of the silicon oxide layer, and then crystallizing the doped amorphous silicon under a high-temperature process and activating doping atoms to form a doped polycrystalline silicon layer;
removing BSG and PSG;
depositing a passivation layer: silicon oxide is formed by thermal oxidation or PECVD, aluminum oxide is deposited by ALD or PECVD, and silicon nitride is deposited by PECVD;
depositing a hydrogenated transparent conductive film: hydrogenating the transparent conductive film on the outer side of the doped polysilicon by adopting a PVD (physical vapor deposition) or RPD (reverse plasma deposition) technology;
upper and lower electrodes are formed.
Further, the silicon oxide layer is formed by LPCVD, thermal oxidation or wet oxidation, and the thickness of the silicon oxide layer is 0.5-3 nm.
Furthermore, the doped amorphous silicon adopts LPCVD or PECVD mode, the forming temperature of the polysilicon layer is 600-.
Further, the hydrogenated transparent conductive film is one of AZO H, IO H, IWO H and FTO H, and the thickness is 30-150 nm;
further, the upper electrode and the lower electrode are formed by adopting screen printing and sintering, aluminum paste is printed on one side of the hydrogenated transparent conductive film, silver paste or silver-aluminum paste is printed on one side of the passivation layer, and electrode contact is formed by sintering at the temperature of 850 ℃ under 700-.
The technical scheme adopted by the invention has the beneficial effects that:
according to the invention, the passivation layer on the surface of the polycrystalline silicon is replaced by the hydrogenated TCO film, and the TCO film has good electrical property, can form good ohmic contact with the slurry, and does not need the slurry to burn through to contact with the polycrystalline silicon, so that the non-burn-through type slurry such as aluminum slurry can be used for replacing silver slurry, and the cost is reduced.
The solar cell of the present invention has high efficiency mainly because: 1. the hydrogenated transparent oxide film ensures the passivation effect, and 2, the transparent oxide film has good conductivity, so that no burn-through slurry is needed, the slurry does not burn through the film and the polysilicon, and the passivation loss of a part of metal areas caused by the burn-through slurry burning through the passivation film and the polysilicon is reduced.
Drawings
Fig. 1 is a schematic structural view of a solar cell according to the present invention.
In the figure: the structure comprises a substrate 1, a diffusion layer 2, a passivation layer 3, a silicon oxide layer 4, a doped polycrystalline silicon layer 5, a hydrogenated transparent conductive film 6, an upper electrode 7 and a lower electrode 8.
Detailed Description
The invention will now be described in further detail with reference to specific embodiments and the accompanying drawings. The following examples are intended to provide those skilled in the art with a more complete understanding of the present invention, and are not intended to limit the scope of the present invention. Reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic may be included in at least one implementation of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments.
Example 1
Referring to fig. 1, the low-cost and high-efficiency solar cell of the present invention includes a substrate 1, the substrate 1 is an N-type substrate,
a diffusion layer 2 on the upper surface of the substrate, the diffusion layer 2 being an n + layer,
a passivation layer 3 on the upper surface of the diffusion layer, the passivation layer 3 being a silicon oxide/silicon nitride stack,
a silicon oxide layer 4 on the lower surface of the substrate,
and the doped polycrystalline silicon layer 5 is positioned on the lower surface of the silicon oxide layer, and the doped polycrystalline silicon layer 5 is a p + polycrystalline silicon layer.
And the hydrogenated transparent conductive film 6 is positioned on the lower surface of the doped polycrystalline silicon layer, and the hydrogenated transparent conductive film 6 is AZO: H.
And the upper electrode 7 is positioned on the upper surface of the passivation layer, and the lower electrode 8 is positioned on the lower surface of the hydrogenated transparent conductive film 6, wherein the upper electrode 7 is made of silver paste, and the lower electrode 8 is made of aluminum paste.
The preparation method of the solar cell in this embodiment is as follows:
1) texturing: an N-type monocrystalline silicon wafer is taken as a substrate, firstly, an alkali texturing mode is adopted to form a light-trapping textured surface on the surface of the silicon wafer, the used solution is usually KOH solution, and the KOH solution is generally prepared according to the following formula: additive: h2Prepared at the ratio of 20:3:160 and the temperature is 80 ℃. Then washing in 2-5% HF solution, and washing to dryAnd cleaning the surface of the silicon wafer. Texturing the substrate 1 to form a textured structure with a light trapping effect;
2) diffusion: in a traditional diffusion furnace tube, a phosphorus diffusion process is carried out on the front surface of a silicon wafer to form an n + diffusion layer 2, the process temperature is 700-900 ℃, and POCl is adopted3The flow rate was 1000sccm for 900 seconds, resulting in a sheet resistance range of 100ohm/□.
3) Etching: the back phosphorus diffusion area is removed by etching, and back etching is generally performed by adopting an acid solution which is prepared from HF and HNO3And water is prepared according to the ratio of 1:3: 6;
4) and (3) oxidation: a silicon oxide layer 4 is formed on the upper surface of the substrate 1 by thermal oxidation with a thickness of 1.5 nm.
5) Depositing a doped polysilicon layer 5: placing the oxidized silicon wafer into an LPCVD furnace tube, forming doped p + amorphous silicon on the lower surface of the silicon oxide layer 4 in an in-situ doping mode, and then crystallizing the doped amorphous silicon at the high temperature of 600-1000 ℃ and activating doping atoms to form a doped polycrystalline silicon layer with the thickness of 180 nm;
6) removing BSG and PSG: cleaning in an HF solution with the volume concentration of 2%, and removing BSG and PSG on the upper surface and the lower surface of the silicon chip;
7) depositing a passivation layer 3: forming silicon oxide on the upper surface of the diffusion layer 2 by a thermal oxidation mode, and depositing silicon nitride on the surface of the diffusion layer by PECVD;
8) depositing the hydrogenated transparent conductive film 6: then, depositing a hydrogenated transparent conductive film AZO H with the thickness of 30nm on the outer side of the doped polycrystalline silicon layer 5 by adopting a PVD (physical vapor deposition) technology;
9) forming an upper electrode and a lower electrode: and finally, adopting screen printing and sintering to form an upper electrode 7 and a lower electrode 8, printing aluminum paste on one side of the hydrogenated transparent conductive film, printing silver paste on one side of the passivation layer, and sintering at the temperature of 700-850 ℃ to form electrode contact, thereby finishing the manufacture of the cell.
Example 2
Referring to fig. 1, the low-cost and high-efficiency solar cell of the present invention includes a substrate 1, the substrate 1 is an N-type substrate,
a diffusion layer 2 on the upper surface of the substrate, the diffusion layer 2 being a p + layer,
a passivation layer 3 on the upper surface of the diffusion layer, the passivation layer 3 being a silicon oxide/aluminum oxide/silicon nitride stack,
a silicon oxide layer 4 on the lower surface of the substrate,
a doped polysilicon layer 5 on the lower surface of the silicon oxide layer, the doped polysilicon layer 5 being an n + polysilicon layer,
and the hydrogenated transparent conductive film 6 is positioned on the lower surface of the doped polycrystalline silicon layer, and the hydrogenated transparent conductive film 6 is AZO: H.
And an upper electrode 7 on the upper surface of the passivation layer and a lower electrode 8 on the lower surface of the hydrogenated transparent conductive film. The upper electrode 7 is made of silver-aluminum paste, and the lower electrode 8 is made of aluminum paste.
The preparation method of the solar cell in this embodiment is as follows:
1) texturing: an N-type monocrystalline silicon wafer is taken as a substrate, firstly, an alkali texturing mode is adopted to form a light-trapping textured surface on the surface of the silicon wafer, the used solution is usually KOH solution, and the KOH solution is generally prepared according to the following formula: additive: h2Prepared at the ratio of 20:3:160 and the temperature is 80 ℃. Then cleaning the silicon wafer in 2-5% HF solution, and cleaning the surface of the silicon wafer. Texturing the substrate 1 to form a textured structure with a light trapping effect;
2) diffusion: in a traditional diffusion furnace tube, a B diffusion process is carried out on the front surface of a silicon wafer to form a p + diffusion layer 2, the process temperature is 1050 ℃, and BCl3The flow rate was 250sccm for 600s, resulting in a sheet resistance range of 120ohm/□.
3) Etching: removing the boron diffusion area on the back by etching, generally using an acid solution to perform back etching, wherein the acid solution is made of HF and HNO3And water is prepared according to the ratio of 1:3: 6;
4) and (3) oxidation: a silicon oxide layer 4 is formed on the upper surface of the substrate 1 by thermal oxidation with a thickness of 2 nm.
5) Depositing a doped polysilicon layer 5: placing the oxidized silicon wafer into an LPCVD furnace tube, forming doped n + amorphous silicon on the lower surface of the silicon oxide layer 4 in an in-situ doping mode, and then crystallizing the doped amorphous silicon at the high temperature of 600-1000 ℃ and activating doping atoms to form a doped polycrystalline silicon layer with the thickness of 150 nm;
6) removing BSG and PSG: cleaning in an HF solution with the volume concentration of 2%, and removing BSG and PSG on the upper surface and the lower surface of the silicon chip;
7) depositing a passivation layer 3: forming silicon oxide on the upper surface of the diffusion layer 2 by a thermal oxidation mode, depositing aluminum oxide on the surface by adopting PECVD (plasma enhanced chemical vapor deposition), and depositing silicon nitride on the surface by adopting PECVD;
8) depositing the hydrogenated transparent conductive film 6: then, depositing a hydrogenated transparent conductive film AZO H with the thickness of 50nm on the outer side of the doped polycrystalline silicon layer 5 by adopting a PVD (physical vapor deposition) technology;
9) forming an upper electrode and a lower electrode: and finally, screen printing and sintering are adopted to form an upper electrode 7 and a lower electrode 8, aluminum paste is printed on one side of the hydrogenated transparent conductive film, silver aluminum paste is printed on one side of the passivation layer, and sintering is carried out at the temperature of 700-850 ℃ to form electrode contact, so that the manufacturing of the battery is completed.
Example 3
Referring to fig. 1, the low-cost and high-efficiency solar cell of the present invention includes a substrate 1, the substrate 1 is an N-type substrate,
a diffusion layer 2 on the upper surface of the substrate, the diffusion layer 2 being a p + layer,
a passivation layer 3 on the upper surface of the diffusion layer, the passivation layer 3 being a silicon oxide/aluminum oxide/silicon nitride stack,
a silicon oxide layer 4 on the lower surface of the substrate,
a doped polysilicon layer 5 on the lower surface of the silicon oxide layer, the doped polysilicon layer 5 being an n + polysilicon layer,
and the hydrogenated transparent conductive film 6 is positioned on the lower surface of the doped polycrystalline silicon layer, and IO: H is selected as the hydrogenated transparent conductive film 6.
And an upper electrode 7 on the upper surface of the passivation layer and a lower electrode 8 on the lower surface of the hydrogenated transparent conductive film. The upper electrode 7 is made of silver-aluminum paste, and the lower electrode 8 is made of aluminum paste.
The preparation method of the solar cell in this embodiment is as follows:
1) texturing: an N-type monocrystalline silicon wafer is taken as a substrate, firstly, an alkali texturing mode is adopted to form a light-trapping textured surface on the surface of the silicon wafer, the used solution is usually KOH solution, and the KOH solution is generally according to the formulaKOH: additive: h2Prepared at the ratio of 20:3:160 and the temperature is 80 ℃. Then cleaning the silicon wafer in 2-5% HF solution, and cleaning the surface of the silicon wafer. Texturing the substrate 1 to form a textured structure with a light trapping effect;
2) diffusion: in a traditional diffusion furnace tube, a B diffusion process is carried out on the front surface of a silicon wafer to form a p + diffusion layer 2, the process temperature is 1050 ℃, and BCl3The flow rate was 250sccm for 600s, resulting in a sheet resistance range of 120ohm/□.
3) Etching: removing the boron diffusion area on the back by etching, generally using an acid solution to perform back etching, wherein the acid solution is made of HF and HNO3And water is prepared according to the ratio of 1:3: 6;
4) and (3) oxidation: a silicon oxide layer 4 was formed on the upper surface of the substrate 1 by LPCVD, and the thickness was controlled to 2 nm.
5) Depositing a doped polysilicon layer 5: placing the oxidized silicon wafer in an LPCVD furnace tube, forming doped n + amorphous silicon on the lower surface of the silicon oxide layer 4 in an in-situ doping mode, crystallizing the doped amorphous silicon at the high temperature of 600-1000 ℃, and activating doping atoms to form a doped polycrystalline silicon layer with the thickness of 100 nm;
6) removing BSG and PSG: cleaning in an HF solution with the volume concentration of 2%, and removing BSG and PSG on the upper surface and the lower surface of the silicon chip;
7) depositing a passivation layer 3: forming silicon oxide on the upper surface of the diffusion layer 2 by PECVD, depositing aluminum oxide on the surface by ALD, and depositing silicon nitride on the surface by PECVD;
8) depositing the hydrogenated transparent conductive film 6: then, depositing a hydrogenated transparent conductive film IO, H, with the thickness of 100nm on the outer side of the doped polycrystalline silicon layer 5 by adopting an RPD technology;
9) forming an upper electrode and a lower electrode: and finally, screen printing and sintering are adopted to form an upper electrode 7 and a lower electrode 8, aluminum paste is printed on one side of the hydrogenated transparent conductive film, silver aluminum paste is printed on one side of the passivation layer, and sintering is carried out at the temperature of 700-850 ℃ to form electrode contact, so that the manufacturing of the battery is completed.
Example 4
Referring to fig. 1, the low-cost and high-efficiency solar cell of the present invention includes a substrate 1, the substrate 1 is a P-type substrate,
a diffusion layer 2 on the upper surface of the substrate, the diffusion layer 2 being a p + layer,
a passivation layer 3 on the upper surface of the diffusion layer, the passivation layer 3 being a silicon oxide/aluminum oxide/silicon nitride stack,
a silicon oxide layer 4 on the lower surface of the substrate,
a doped polysilicon layer 5 on the lower surface of the silicon oxide layer, the doped polysilicon layer 5 being an n + polysilicon layer,
and the hydrogenated transparent conductive film 6 is positioned on the lower surface of the doped polycrystalline silicon layer, and IWO is selected as the hydrogenated transparent conductive film 6.
And an upper electrode 7 on the upper surface of the passivation layer and a lower electrode 8 on the lower surface of the hydrogenated transparent conductive film. The upper electrode 7 is made of silver-aluminum paste, and the lower electrode 8 is made of aluminum paste.
The preparation method of the solar cell in this embodiment is as follows:
1) texturing: a P-type monocrystalline silicon wafer is taken as a substrate, firstly, an alkali texturing mode is adopted to form a light-trapping textured surface on the surface of the silicon wafer, the used solution is usually KOH solution, and the KOH solution is generally prepared according to the following formula: additive: h2Prepared at the ratio of 20:3:160 and the temperature is 80 ℃. Then cleaning the silicon wafer in 2-5% HF solution, and cleaning the surface of the silicon wafer. Texturing the substrate 1 to form a textured structure with a light trapping effect;
2) diffusion: in a traditional diffusion furnace tube, a B diffusion process is carried out on the front surface of a silicon wafer to form a p + diffusion layer 2, the process temperature is 1050 ℃, and BCl3The flow rate was 250sccm for 600s, resulting in a sheet resistance range of 120ohm/□.
3) Etching: removing the boron diffusion area on the back by etching, generally using an acid solution to perform back etching, wherein the acid solution is made of HF and HNO3And water is prepared according to the ratio of 1:3: 6;
4) and (3) oxidation: a silicon oxide layer 4 was formed on the upper surface of the substrate 1 by LPCVD to a thickness of 3 nm.
5) Depositing a doped polysilicon layer 5: placing the oxidized silicon wafer into a PECVD furnace tube, forming doped n + amorphous silicon on the lower surface of the silicon oxide layer 4 by adopting an in-situ doping mode, and then crystallizing the doped amorphous silicon at the high temperature of 600-1000 ℃ and activating doping atoms to form a doped polycrystalline silicon layer with the thickness of 50 nm;
6) removing BSG and PSG: cleaning in an HF solution with the volume concentration of 2%, and removing BSG and PSG on the upper surface and the lower surface of the silicon chip;
7) depositing a passivation layer 3: forming silicon oxide on the upper surface of the diffusion layer 2 by PECVD, depositing aluminum oxide on the surface by ALD, and depositing silicon nitride on the surface by PECVD;
8) depositing the hydrogenated transparent conductive film 6: then, depositing a hydrogenated transparent conductive film IWO (indium tin oxide) H with the thickness of 120nm on the outer side of the doped polycrystalline silicon layer 5 by adopting an RPD (reverse plasma display panel) technology;
9) forming an upper electrode and a lower electrode: and finally, screen printing and sintering are adopted to form an upper electrode 7 and a lower electrode 8, aluminum paste is printed on one side of the hydrogenated transparent conductive film, silver aluminum paste is printed on one side of the passivation layer, and sintering is carried out at the temperature of 700-850 ℃ to form electrode contact, so that the manufacturing of the battery is completed.
Example 5
Referring to fig. 1, the low-cost and high-efficiency solar cell of the present invention includes a substrate 1, the substrate 1 is a P-type substrate,
a diffusion layer 2 on the upper surface of the substrate, the diffusion layer 2 being a p + layer, a passivation layer 3 being a silicon oxide/aluminum oxide/silicon nitride stack,
a passivation layer 3 on the upper surface of the diffusion layer,
a silicon oxide layer 4 on the lower surface of the substrate,
a doped polysilicon layer 5 on the lower surface of the silicon oxide layer, the doped polysilicon layer 5 being an n + polysilicon layer,
a hydrogenated transparent conductive film 6 positioned on the lower surface of the doped polycrystalline silicon layer, wherein the hydrogenated transparent conductive film 6 is selected from FTO: H,
and an upper electrode 7 on the upper surface of the passivation layer and a lower electrode 8 on the lower surface of the hydrogenated transparent conductive film. The upper electrode 7 is made of silver paste or silver-aluminum paste, and the lower electrode 8 is made of aluminum paste.
The preparation method of the solar cell in this embodiment is as follows:
1) texturing: by P-type single crystalThe silicon chip is taken as a substrate, firstly, an alkali texturing mode is adopted to form a light-trapping textured surface on the surface of the silicon chip, the used solution is usually KOH solution, and the KOH solution is generally prepared according to the following formula: additive: h2Prepared at the ratio of 20:3:160 and the temperature is 80 ℃. Then cleaning the silicon wafer in 2-5% HF solution, and cleaning the surface of the silicon wafer. Texturing the substrate 1 to form a textured structure with a light trapping effect;
2) diffusion: in a traditional diffusion furnace tube, a B diffusion process is carried out on the front surface of a silicon wafer to form a p + diffusion layer 2, the process temperature is 1050 ℃, and BCl3The flow rate was 250sccm for 600s, resulting in a sheet resistance range of 120ohm/□.
3) Etching: removing the boron diffusion area on the back by etching, generally using an acid solution to perform back etching, wherein the acid solution is made of HF and HNO3And water is prepared according to the ratio of 1:3: 6;
4) and (3) oxidation: a silicon oxide layer 4 is formed on the upper surface of the substrate 1 by wet oxidation with a thickness of 3 nm.
5) Depositing a doped polysilicon layer 5: placing the oxidized silicon wafer into a PECVD furnace tube, forming doped n + amorphous silicon on the lower surface of the silicon oxide layer 4 by adopting an in-situ doping mode, and then crystallizing the doped amorphous silicon at the high temperature of 600-1000 ℃ and activating doping atoms to form a doped polycrystalline silicon layer with the thickness of 30 nm;
6) removing BSG and PSG: cleaning in an HF solution with the volume concentration of 2%, and removing BSG and PSG on the upper surface and the lower surface of the silicon chip;
7) depositing a passivation layer 3: forming silicon oxide on the upper surface of the diffusion layer 2 by PECVD, depositing aluminum oxide on the surface by ALD, and depositing silicon nitride on the surface by PECVD;
8) depositing the hydrogenated transparent conductive film 6: then depositing a hydrogenated transparent conductive film FTO (fluorine doped oxide) H (H) with the thickness of 150nm on the outer side of the doped polycrystalline silicon layer 5 by adopting a PVD (physical vapor deposition) technology;
9) forming an upper electrode and a lower electrode: and finally, screen printing and sintering are adopted to form an upper electrode 7 and a lower electrode 8, aluminum paste is printed on one side of the hydrogenated transparent conductive film, silver aluminum paste is printed on one side of the passivation layer, and sintering is carried out at the temperature of 700-850 ℃ to form electrode contact, so that the manufacturing of the battery is completed.
Through simulation, the efficiency of the low-cost and high-efficiency solar cell disclosed by the invention can reach 23.9-24.1%, which is slightly higher than the efficiency of a mainstream contact passivation cell.
The performance test of the solar cells in examples 1 to 5 includes: open circuit voltage (Voc), short circuit current density (Jsc), Fill Factor (FF), conversion efficiency (Eta). The reference group is a mainstream contact passivated cell, i.e. a cell that does not employ a hydrogenated TCO film instead of a passivation layer on the polysilicon surface.
In light of the foregoing description of the preferred embodiment of the present invention, many modifications and variations will be apparent to those skilled in the art without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention. The technical scope of the present invention is not limited to the content of the specification, and must be determined according to the scope of the claims.
Claims (10)
1. A low cost, high efficiency solar cell, characterized by:
comprises a substrate and a plurality of metal layers,
a diffusion layer located on the upper surface of the substrate,
a passivation layer on the upper surface of the diffusion layer,
a silicon oxide layer on the lower surface of the substrate,
a doped polysilicon layer located on the lower surface of the silicon oxide layer,
a hydrogenated transparent conductive film located on the lower surface of the doped polysilicon layer,
and an upper electrode on the upper surface of the passivation layer and a lower electrode on the lower surface of the hydrogenated transparent conductive film.
2. A low cost, high efficiency solar cell as defined in claim 1, wherein: the substrate is an N-type substrate or a P-type substrate.
3. A low cost, high efficiency solar cell as defined in claim 1, wherein: the diffusion layer is a p + layer or an n + layer,
when the diffusion layer is a p + layer, the passivation layer is a silicon oxide/aluminum oxide/silicon nitride lamination layer, the doped polysilicon layer is an n + polysilicon layer,
when the diffusion layer is n +, the passivation layer is a silicon oxide/silicon nitride lamination layer, and the doped polycrystalline silicon layer is a p + polycrystalline silicon layer.
4. A low cost, high efficiency solar cell as defined in claim 1, wherein: the hydrogenated transparent conductive film is selected from one of AZO H, IO H, IWO H and FTO H.
5. A low cost, high efficiency solar cell as defined in claim 1, wherein: the upper electrode is made of silver paste or silver-aluminum paste, and the lower electrode is made of aluminum paste.
6. A preparation method of a low-cost high-efficiency solar cell is characterized by comprising the following steps: the preparation method comprises the following steps:
texturing: texturing the substrate to form a textured structure with a light trapping effect;
diffusion: forming a diffusion layer on an upper surface of a substrate;
etching: removing the pn junction on the lower surface of the substrate;
and (3) oxidation: forming a silicon oxide layer on the lower surface of the substrate;
depositing doped polysilicon: forming doped amorphous silicon on the lower surface of the silicon oxide layer, and then crystallizing the doped amorphous silicon under a high-temperature process and activating doping atoms to form a doped polycrystalline silicon layer;
removing BSG and PSG;
depositing a passivation layer: silicon oxide is formed by thermal oxidation or PECVD, aluminum oxide is deposited by ALD or PECVD, and silicon nitride is deposited by PECVD;
depositing a hydrogenated transparent conductive film: depositing a hydrogenated transparent conductive film on the outer side of the doped polysilicon by adopting a PVD (physical vapor deposition) or RPD (reverse plasma deposition) technology;
upper and lower electrodes are formed.
7. The method of claim 6, wherein the solar cell is fabricated at low cost and high efficiency by the steps of: the silicon oxide layer is formed by LPCVD, thermal oxidation or wet oxidation, and the thickness of the silicon oxide layer is 0.5-3 nm.
8. The method of claim 6, wherein the solar cell is fabricated at low cost and high efficiency by the steps of: the doped amorphous silicon adopts an LPCVD or PECVD mode, the forming temperature of the polycrystalline silicon layer is 600-1000 ℃, and the thickness is 30-200 nm.
9. The method of claim 6, wherein the solar cell is fabricated at low cost and high efficiency by the steps of: the hydrogenated transparent conductive film is one of AZO H, IO H, IWO H and FTO H, and the thickness of the hydrogenated transparent conductive film is 30-150 nm.
10. The method of claim 6, wherein the solar cell is fabricated at low cost and high efficiency by the steps of: the upper electrode and the lower electrode are formed by screen printing and sintering, aluminum paste is printed on one side of the hydrogenated transparent conductive film, silver paste or silver-aluminum paste is printed on one side of the passivation layer, and electrode contact is formed by sintering at the temperature of 850 ℃ through 700-.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011285647.5A CN112397596A (en) | 2020-12-28 | 2020-12-28 | Low-cost high-efficiency solar cell and preparation method thereof |
| PCT/CN2021/110869 WO2022142343A1 (en) | 2020-12-28 | 2021-08-05 | Solar cell and preparation method therefor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011285647.5A CN112397596A (en) | 2020-12-28 | 2020-12-28 | Low-cost high-efficiency solar cell and preparation method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112397596A true CN112397596A (en) | 2021-02-23 |
Family
ID=74600947
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202011285647.5A Pending CN112397596A (en) | 2020-12-28 | 2020-12-28 | Low-cost high-efficiency solar cell and preparation method thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN112397596A (en) |
| WO (1) | WO2022142343A1 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114649424A (en) * | 2022-03-28 | 2022-06-21 | 常州时创能源股份有限公司 | Electrode structure of crystalline silicon solar cell |
| WO2022142343A1 (en) * | 2020-12-28 | 2022-07-07 | 东方日升新能源股份有限公司 | Solar cell and preparation method therefor |
| CN119300530A (en) * | 2024-12-02 | 2025-01-10 | 宁波欧达光电有限公司 | A preparation process for tunneling oxide layer passivation contact solar cell |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115621333B (en) | 2022-11-22 | 2023-03-10 | 金阳(泉州)新能源科技有限公司 | Back contact solar cell passivated by double-sided tunneling silicon oxide and preparation method thereof |
| CN116799091B (en) * | 2023-06-16 | 2024-02-20 | 扬州大学 | A laminated p-type passivation contact structure based on Poly finger and its preparation method |
| CN118053919B (en) * | 2024-04-15 | 2024-09-13 | 福建金石能源有限公司 | Front-side specific passivated back contact solar cell, manufacturing method thereof and photovoltaic module |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102239572A (en) * | 2008-12-04 | 2011-11-09 | 太阳能公司 | Backside contact solar cell with formed polysilicon doped regions |
| CN102610670A (en) * | 2012-03-30 | 2012-07-25 | 鲁东大学 | Near-infrared transparent conducting film and method for producing same |
| CN103907205A (en) * | 2011-10-27 | 2014-07-02 | 三菱电机株式会社 | Photoelectric conversion device and method for manufacturing same, and photoelectric conversion module |
| CN103956391A (en) * | 2014-04-11 | 2014-07-30 | 中国科学院宁波材料技术与工程研究所 | AZO/Si heterojunction solar battery and manufacturing method thereof |
| CN104885232A (en) * | 2012-12-19 | 2015-09-02 | 太阳能公司 | Hybrid emitter all back contact solar cell |
| CN110459639A (en) * | 2019-08-13 | 2019-11-15 | 江苏爱康能源研究院有限公司 | Heterojunction battery structure with hydrogen annealed TCO conductive film and its preparation method |
| CN112054090A (en) * | 2020-08-12 | 2020-12-08 | 无锡琨圣智能装备股份有限公司 | Efficient double-sided TOPCON battery technology for superposing TCO transparent conductive film |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20170098722A1 (en) * | 2015-10-01 | 2017-04-06 | Lg Electronics Inc. | Solar cell |
| CN106024964B (en) * | 2016-07-13 | 2017-09-22 | 北京工业大学 | A kind of preparation method of n-type back of the body knot double-side solar cell |
| CN107845692A (en) * | 2016-09-20 | 2018-03-27 | 上海神舟新能源发展有限公司 | A kind of preparation method of modified back side tunnel oxidation passivation contact high-efficiency battery |
| CN111564517A (en) * | 2020-05-20 | 2020-08-21 | 东方日升（常州）新能源有限公司 | Fully-passivated contact heterojunction battery and manufacturing method thereof |
| CN112397596A (en) * | 2020-12-28 | 2021-02-23 | 东方日升新能源股份有限公司 | Low-cost high-efficiency solar cell and preparation method thereof |
-
2020
- 2020-12-28 CN CN202011285647.5A patent/CN112397596A/en active Pending
-
2021
- 2021-08-05 WO PCT/CN2021/110869 patent/WO2022142343A1/en active Application Filing
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102239572A (en) * | 2008-12-04 | 2011-11-09 | 太阳能公司 | Backside contact solar cell with formed polysilicon doped regions |
| CN103907205A (en) * | 2011-10-27 | 2014-07-02 | 三菱电机株式会社 | Photoelectric conversion device and method for manufacturing same, and photoelectric conversion module |
| CN102610670A (en) * | 2012-03-30 | 2012-07-25 | 鲁东大学 | Near-infrared transparent conducting film and method for producing same |
| CN104885232A (en) * | 2012-12-19 | 2015-09-02 | 太阳能公司 | Hybrid emitter all back contact solar cell |
| CN103956391A (en) * | 2014-04-11 | 2014-07-30 | 中国科学院宁波材料技术与工程研究所 | AZO/Si heterojunction solar battery and manufacturing method thereof |
| CN110459639A (en) * | 2019-08-13 | 2019-11-15 | 江苏爱康能源研究院有限公司 | Heterojunction battery structure with hydrogen annealed TCO conductive film and its preparation method |
| CN112054090A (en) * | 2020-08-12 | 2020-12-08 | 无锡琨圣智能装备股份有限公司 | Efficient double-sided TOPCON battery technology for superposing TCO transparent conductive film |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022142343A1 (en) * | 2020-12-28 | 2022-07-07 | 东方日升新能源股份有限公司 | Solar cell and preparation method therefor |
| CN114649424A (en) * | 2022-03-28 | 2022-06-21 | 常州时创能源股份有限公司 | Electrode structure of crystalline silicon solar cell |
| CN114649424B (en) * | 2022-03-28 | 2024-02-13 | 常州时创能源股份有限公司 | Electrode structure of crystalline silicon solar cell |
| CN119300530A (en) * | 2024-12-02 | 2025-01-10 | 宁波欧达光电有限公司 | A preparation process for tunneling oxide layer passivation contact solar cell |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2022142343A1 (en) | 2022-07-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| EP3916814B1 (en) | Photovoltaic module, solar cell, and method for producing solar cell | |
| CN109244194B (en) | A preparation method of low-cost p-type all-back-electrode crystalline silicon solar cell | |
| CN112397596A (en) | Low-cost high-efficiency solar cell and preparation method thereof | |
| TWI718703B (en) | Solar cell and manufacturing method thereof | |
| KR101597532B1 (en) | The Manufacturing Method of Back Contact Solar Cells | |
| CN112820793A (en) | Solar cell and preparation method thereof | |
| CN102623517A (en) | A kind of back contact type crystalline silicon solar cell and its manufacturing method | |
| CN116914012A (en) | A double-sided doped polycrystalline silicon passivated contact battery and its preparation method | |
| TWM527159U (en) | Heterojunction solar cell | |
| CN210349847U (en) | P-type tunneling oxide passivation contact solar cell | |
| CN112054068A (en) | Silicon heterojunction solar cell and manufacturing method thereof | |
| CN212874518U (en) | Solar cell | |
| CN110580969A (en) | A kind of crystalline silicon cell and its conductive paste | |
| CN118016766A (en) | A P-type TBC crystalline silicon solar cell and a manufacturing method thereof | |
| CN104868011A (en) | Manufacturing method of N type all-aluminum back emitter solar cell and solar cell prepared by the same | |
| KR101165915B1 (en) | Method for fabricating solar cell | |
| CN103066133A (en) | Photoelectric device | |
| CN114256361A (en) | Solar cell and photovoltaic module | |
| CN202076297U (en) | Back contact HIT solar cell structure based on P-type silicon chip | |
| US12062728B1 (en) | Solar cells | |
| CN101764180A (en) | Method for manufacturing local front-surface field N-type solar cell | |
| US11996494B2 (en) | Low-cost passivated contact full-back electrode solar cell and preparation method thereof | |
| CN208507687U (en) | Interdigital back contact heterojunction monocrystalline silicon battery | |
| CN116487482A (en) | Solar cell and manufacturing method thereof | |
| US20150187979A1 (en) | Heterojunction solar cell with epitaxial silicon thin film and method for preparing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20210223 |
|
| RJ01 | Rejection of invention patent application after publication |