CN112396981B - display panel - Google Patents

Abstract

A display panel includes: a first substrate, a second substrate, a plurality of pixel circuits and a plurality of through holes. The first substrate has a first surface and a second surface opposite to the first surface. The second substrate has a third surface and a fourth surface opposite to the third surface. Each of the pixel circuits has a first part and a second part, wherein the first part arrays of the pixel circuits are arranged on the first surface, and the second part arrays of the pixel circuits are arranged on the third surface. These through holes are formed on the first substrate and the second substrate to electrically connect the first part and the second part of each pixel circuit.

Description

display panel

Technical field

The present invention relates to a display panel, and in particular to a display panel with high pixel density.

Background technique

As color screens on mobile phones become more and more common, the material of mobile phone screens becomes increasingly important. The color screens of mobile phones vary due to different screen materials and development technologies. They generally include thin film field effect transistor (Thinfilm transistor liquid crystal display, TFT), thin film diode semi-transparent (Thin Film Diode, TFD), UFB, ultra Twisted nematic (Super Twisted Nematic, STN) and organic light emitting diode (Organic Light Emitting Display, OLED) and so on. Generally speaking, in addition to the color gamut of the display panel, the higher the resolution of the display panel, the better it can display complex images and make the picture richer. However, limited by the number of transistors in the pixel circuit, it is increasingly difficult to improve the resolution of display panels, so a new display panel structure is needed.

Contents of the invention

The present invention provides a display panel that can increase the resolution or space utilization of the display panel and achieve the purpose of narrowing the frame.

The display panel of the present invention includes: a first substrate, a second substrate, a plurality of pixel circuits and a plurality of through holes. The first substrate has a first surface and a second surface opposite to the first surface. The second substrate has a third surface and a fourth surface opposite to the third surface. Each of the pixel circuits has a first part and a second part, wherein the first part arrays of the pixel circuits are arranged on the first surface, and the second part arrays of the pixel circuits are arranged on the third surface. These through holes are formed on the first substrate and the second substrate to electrically connect the first part and the second part of each pixel circuit.

Based on the above, the display panel according to the embodiment of the present invention increases the circuit layout space of the display panel by using the first substrate and the second substrate superimposed in the vertical direction, thereby increasing the resolution or space utilization of the display panel, and also achieving narrow The purpose of the border.

In order to make the above-mentioned features and advantages of the present invention more obvious and easy to understand, embodiments are given below and described in detail with reference to the accompanying drawings.

Description of the drawings

FIG. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention.

FIG. 2 is a schematic cross-sectional view of a display panel according to an embodiment of the present invention.

FIG. 3 is a schematic cross-sectional view of a display panel according to another embodiment of the present invention.

FIG. 4 is a schematic diagram of a pixel circuit according to an embodiment of the present invention.

FIG. 5 is a schematic diagram of a pixel circuit according to another embodiment of the present invention.

FIG. 6 is a schematic diagram of a pixel circuit according to another embodiment of the present invention.

FIG. 7 is a schematic diagram of the wiring of power lines and signal lines of a display panel according to an embodiment of the present invention.

Explanation of reference symbols:

100: Display panel

110: First substrate

111: First surface

113: Second surface

120: Adhesive layer

130: Second substrate

131: Third surface

133: Fourth surface

APX: pixel array area

C1, C2, C3: capacitor

d1: first extension direction

d2: second extension direction

DATA: data voltage

ECS: control switching element

EDR: driving element

EIL, LDX1～LDX3: light-emitting elements

EM: luminous signal

LDX: data signal line

LEM: Luminous signal line

Lf1: The first active component layer

Lf2: The second active component layer

Lpw1: first power line

Lpw2: Second power cord

LSC: scanning signal line

LSE: detection signal line

Ltg: detection switch signal line

PIX, PIXa～PIXc: pixel circuit

PT1: Part One

PT2: Part Two

S1: first scan signal

S2: second scanning signal

SCAN: scan signal

SENSE: detection signal

Stg: detect switch signal

T11～T13, T21～T23, T31～T37: transistor

VA11, VA12, VA21, VA22, VA31～VA33: Internal perforation

VAX: perforation

VDD: system high voltage

VREF: reference voltage

VSS: system low voltage

Detailed ways

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms such as those defined in commonly used dictionaries should be construed to have meanings consistent with their meanings in the context of the relevant technology and the present invention, and are not to be construed as idealistic or excessive Formal meaning, unless expressly defined as such herein.

It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, and/or /or parts shall not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a "first element," "component," "region," "layer" or "section" discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms including "at least one" unless the content clearly dictates otherwise. "Or" means "and/or". As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. It will also be understood that when used in this specification, the terms "comprises" and/or "includes" designate the presence of stated features, regions, integers, steps, operations, elements and/or components but do not exclude one or more The presence or addition of other features, regions, steps, operations, elements, parts and/or combinations thereof.

FIG. 1 is a schematic structural diagram of a display panel according to an embodiment of the present invention. Please refer to Figure 1. In this embodiment, the display panel 100 at least includes a first substrate 110, an adhesive layer 120, a second substrate 130, a plurality of pixel circuits PIX, a plurality of first power lines Lpw1, and a plurality of second power lines. Lpw2, a plurality of scanning signal lines LSC, a plurality of data signal lines LDX, and a plurality of through holes VAX. The first power lines Lpw1 may each be substantially perpendicular to the second power lines Lpw2, and the first power lines Lpw1 may individually be substantially perpendicular to the second power lines Lpw2.

The first substrate 110 has a first surface 111 and a second surface 113 opposite to the first surface 111 , and the second substrate 130 has a third surface 131 and a fourth surface 133 opposite to the third surface 131 . The pixel circuits PIX are arranged in the pixel array area APX, and each has a first part PT1 and a second part PT2. The first partial PT1 arrays of the pixel circuits PIX are arranged on the first surface 111 , and the second partial PT2 arrays of the pixel circuits PIX are arranged on the third surface 131 .

The first part PT1 of each pixel circuit PIX includes at least one light-emitting element EIL and at least one driving element EDR, and the second part PT1 of each pixel circuit PIX includes at least one control switching element ECS. The light-emitting element EIL includes, for example, one of a light-emitting diode and an organic light-emitting diode.

The first power lines Lpw1 and the second power lines Lpw2 are arranged on the first surface 111 to respectively connect the corresponding first parts PT1 of the pixel circuits PIX. These scanning signal lines LSC and these data signal lines LDX are disposed on the third surface 131 to respectively connect the second portion PT2 of the corresponding pixel circuit PIX.

The adhesive layer 120 is disposed between the first substrate 110 and the second substrate 130 to adhere the first substrate 110 and the second substrate 130 . The through holes VAX are formed on the first substrate 110, the adhesive layer 120 and the second substrate 130 to electrically connect the first part PT1 and the second part PT2 of each pixel circuit PIX. Therefore, by utilizing the circuit layout space superimposed in the vertical direction, the resolution or space utilization of the display panel 100 can be increased, and the purpose of narrowing the frame can also be achieved. In other words, a pixel compensation circuit that accommodates a larger number of thin film transistors can be formed to achieve a display effect of a high number of pixels per inch. In addition, it can provide better resistance value and heat dissipation effect for the power lines (such as the first power line Lpw1 and the second power line Lpw2), and provide a four-sided narrow frame design.

In the embodiment of the present invention, the material of the semiconductor layer of the first substrate 110 may be the same as the material of the semiconductor layer of the second substrate 130 . In the embodiment of the present invention, the material of the semiconductor layer of the first substrate 110 may also be different from the material of the semiconductor layer of the second substrate 130 . For example, the material of the semiconductor layer of the first substrate 110 can be low-temperature polysilicon to have better driving capability (such as higher driving current), and the material of the semiconductor layer of the second substrate 130 can be metal oxide semiconductor. The material is made of low leakage current to prevent excessive leakage current from affecting the screen display when data is not written.

FIG. 2 is a schematic cross-sectional view of a display panel according to an embodiment of the present invention. Referring to FIGS. 1 and 2 , in this embodiment, a first active element layer Lf1 is formed on the first surface 111 of the first substrate 110 to form the first part PT1 of the pixel circuit PIX. A second active element layer Lf2 is formed on the third surface 131 of the second substrate 130 to form the second part PT2 of the pixel circuit PIX. The adhesive layer 120 is used to adhere the second surface 113 of the first substrate 110 to the third surface 131 of the second substrate 130 and the second active component layer Lf2. That is, based on the adhesive layer 120, the third surface 131 is opposite to the second surface 113. . Furthermore, a gate driving circuit (not shown) may be formed on the fourth surface 133 .

FIG. 3 is a schematic cross-sectional view of a display panel according to another embodiment of the present invention. Please refer to FIGS. 1 and 3 . Similar to the embodiment shown in FIG. 2 , a first active element layer Lf1 is formed on the first surface 111 of the first substrate 110 , and a second active element layer Lf1 is formed on the third surface 131 of the second substrate 130 . Element layer Lf2. However, the adhesive layer 120 is used to adhere the second surface 113 of the first substrate 110 and the fourth surface 133 of the second substrate 130 , that is, based on the adhesive layer 120 , the fourth surface 133 is opposite to the second surface 113 .

FIG. 4 is a schematic diagram of a pixel circuit according to an embodiment of the present invention. Referring to FIGS. 1 and 4 , in this embodiment, the second part PT2 of the pixel circuit PIXa includes a transistor T11, and the first part PT1 includes transistors T12, T13, a capacitor C1 and a light-emitting element LDX1. The first terminal of the transistor T11 is electrically connected to the data signal line LDX to receive the data voltage DATA, and the control terminal of the transistor T11 is electrically connected to the scan signal line LSC to receive the scan signal SCAN.

The first terminal of the transistor T12 is electrically connected to the first power line Lpw1 to receive the system high voltage VDD, and the control terminal of the transistor T12 is electrically connected to the second terminal of the transistor T11 through the internal through hole VA11. The capacitor C1 is electrically connected between the first terminal of the transistor T12 and the control terminal of the transistor T12 . The first terminal of the transistor T13 is electrically connected to the second terminal of the transistor T12, and the control terminal of the transistor T12 is electrically connected to the light-emitting signal line LEM through the internal through hole VA12 to receive the light-emitting signal EM. The anode terminal of the light-emitting element LDX1 is electrically connected to the second terminal of the transistor T13, and the cathode terminal of the light-emitting element LDX1 is electrically connected to the second power line Lpw2 to receive the system low voltage VSS.

In the embodiment of the present invention, the internal through holes VA11 and VA12 are arranged in the pixel circuit PIXa, that is, the internal through holes VA11 and VA12 are arranged in the pixel array area APX where these pixel circuits PIXa are arranged. Furthermore, the light-emitting signal line LEM can be provided outside the pixel array area APX, and the signal through holes electrically connected to the scanning signal line LSC, the data signal line LDX and the light-emitting signal line LEM can be arranged in the pixel array area APX where these pixel circuits PIXa are arranged. Within or outside the pixel array area APX, this may depend on the circuit design.

FIG. 5 is a schematic diagram of a pixel circuit according to another embodiment of the present invention. Referring to FIGS. 1 and 5 , in this embodiment, the second part PT2 of the pixel circuit PIXb includes a transistor T21, and the first part PT1 includes transistors T22, T23, a capacitor C2 and a light-emitting element LDX2. The first terminal of the transistor T21 is electrically connected to the data signal line LDX to receive the data voltage DATA, and the control terminal of the transistor T21 is electrically connected to the scan signal line LSC to receive the scan signal SCAN.

The first terminal of the transistor T22 is electrically connected to the first power line Lpw1 to receive the system high voltage VDD, and the control terminal of the transistor T22 is electrically connected to the second terminal of the transistor T21 through the internal through hole VA21. The capacitor C2 is electrically connected between the first terminal of the transistor T22 and the control terminal of the transistor T22. The first terminal of the transistor T23 is electrically connected to the second terminal of the transistor T12, the control terminal of the transistor T22 is electrically connected to the detection switch signal line Ltg through the internal through hole VA22 to receive the detection switch signal Stg, and the second terminal of the transistor T23 is electrically connected The detection signal line LSE provides the detection signal SENSE. The anode terminal of the light-emitting element LDX1 is electrically connected to the second terminal of the transistor T22, and the cathode terminal of the light-emitting element LDX1 is electrically connected to the second power line Lpw2 to receive the system low voltage VSS. The transistor T23 as a detection circuit switch is disposed on the first surface 111 of the first substrate 110 to form a shorter signal path, thereby providing a better resistance value.

In the embodiment of the present invention, the internal through holes VA21 and VA22 are arranged in the pixel circuit PIXb, that is, the internal through holes VA21 and VA22 are arranged in the pixel array area APX where these pixel circuits PIXb are arranged. Furthermore, the detection switch signal Stg can be provided outside the pixel array area APX, and signal through holes electrically connected to the scanning signal line LSC, the data signal line LDX and the detection switch signal Stg can be arranged in the pixel array area APX where these pixel circuits PIXb are arranged. Within or outside the pixel array area APX, this may depend on the circuit design.

FIG. 6 is a schematic diagram of a pixel circuit according to another embodiment of the present invention. Please refer to FIGS. 1 and 6 . In this embodiment, the second part PT3 of the pixel circuit PIXc includes transistors T31 to T35 and the capacitor C3, and the first part PT1 includes transistors T36, T37 and the light-emitting element LDX3.

The first terminal of the transistor T31 is electrically connected to a reference voltage line (not shown) to receive the reference voltage VREF, and the control terminal of the transistor T31 is electrically connected to a light-emitting signal line (LEM as shown in FIG. 4 ) to receive the light-emitting signal EM. The first terminal of the transistor T32 is electrically connected to the second terminal of the transistor T31, the control terminal of the transistor T32 is electrically connected to the second scanning signal line (not shown) to receive the second scanning signal S2, and the second terminal of the transistor T32 is electrically connected to the second scanning signal line (not shown). The data signal line LDX is electrically connected to receive the data voltage DATA.

One end of the capacitor C3 is electrically connected to the second end of the transistor T31. The first terminal of the transistor T33 is electrically connected to the other terminal of the capacitor C3, and the control terminal of the transistor T33 is electrically connected to the second scanning signal line (not shown) to receive the second scanning signal S2. The first terminal of the transistor T34 is electrically connected to the second terminal of the transistor T33, and the control terminal of the transistor T34 is electrically connected to the second scan signal line (not shown) to receive the second scan signal S2.

The first terminal of the transistor T35 is electrically connected to the second terminal of the transistor T33, the control terminal of the transistor T35 is electrically connected to the first scanning signal line (not shown) to receive the first scanning signal S1, and the second terminal of the transistor T35 is electrically connected to the first scanning signal line (not shown). A reference voltage line (not shown) is electrically connected to receive the reference voltage VREF. The first terminal of the transistor T36 is electrically connected to the first power line Lpw1 to receive the system high voltage VDD. The control terminal of the transistor T36 is electrically connected to the other terminal of the capacitor C3 through the internal through hole VA31, and the second terminal of the transistor T36 passes through the internal through hole VA32. The second terminal of the transistor T33 is electrically connected. The first terminal of the transistor T37 is electrically connected to the second terminal of the transistor T36, and the control terminal of the transistor T37 is electrically connected to the light-emitting signal line (the LEM shown in FIG. 4) through the internal through hole VA33 to receive the light-emitting signal EM. The anode terminal of the light-emitting element LDX3 is electrically connected to the second terminal of the transistor T37, and the cathode terminal of the light-emitting element LDX3 is electrically connected to the second power line Lpw2 to receive the system low voltage VSS. The transistors T31 to T35 as different control switching elements are all disposed on the third surface 131 of the second substrate 130, so they can operate more synchronously during driving, thereby reducing delay problems and reducing the number of through holes.

In the embodiment of the present invention, the internal through holes VA31 to VA33 are arranged in the pixel circuit PIXc, that is, the internal through holes VA31 to VA33 are arranged in the pixel array area APX where these pixel circuits PIXc are arranged. Furthermore, the reference voltage line and the light-emitting signal line can be set outside the pixel array area APX, and signal through holes electrically connected to the reference voltage line, the light-emitting signal line, the first scanning signal line, the second scanning signal line, and the like can be arranged in the configuration. These pixel circuits PIXc are within the pixel array area APX or outside the pixel array area APX, which may be determined according to the circuit design.

FIG. 7 is a schematic diagram of the wiring of power lines and signal lines of a display panel according to an embodiment of the present invention. Please refer to FIG. 1 and FIG. 7 . In this embodiment, the power line Lpw1 arranged on the first substrate 110 may be in a mesh shape. Furthermore, the interval between the extending direction d2 of the mesh of the power line Lpw1 arranged on the first substrate 110 (corresponding to the first extending direction) and the extending direction d1 (corresponding to the second extending direction) of the scanning signal line LSC arranged on the second substrate 130 is The angle θ can be 0 to 90 degrees. Furthermore, the angle θ between the extension direction d2 of the power line Lpw1 and the extension direction d1 of the scanning signal line LSC can be 30 to 60 degrees, which can be determined according to the circuit layout requirements, and the embodiment of the present invention is not limited thereto. Therefore, the problem of moiré pattern can be improved through different pitches and angles.

In summary, the display panel according to the embodiment of the present invention increases the circuit layout space of the display panel by using the first substrate and the second substrate stacked in the vertical direction to increase the resolution or space utilization of the display panel. It can also Achieve the purpose of narrow borders.

Although the present invention has been disclosed in the above embodiments, they are not intended to limit the present invention. Any person skilled in the art may make some changes and modifications without departing from the concept and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the claims.

Claims (15)

1. A display panel, comprising:

a first substrate having a first surface and a second surface opposite to the first surface;

a second substrate having a third surface and a fourth surface opposite to the third surface;

a plurality of pixel circuits, each pixel circuit having a first portion and a second portion, wherein the first portion arrays of the pixel circuits are arranged on the first surface, and the second portion arrays of the pixel circuits are arranged on the third surface; and

a plurality of through holes formed on the first substrate and the second substrate for electrically connecting the first portion and the second portion of each of the pixel circuits,

wherein the transistors of the pixel circuit for receiving the data voltage and the scanning signal are positioned in the second parts, the transistors of the pixel circuit for receiving the light emitting signal are positioned in the first parts,

the first part comprises at least one driving element, and the second part comprises at least one control switching element,

transistors serving as different control switch elements are arranged on the third surface of the second substrate.

2. The display panel of claim 1, further comprising an adhesive layer for adhering the first substrate and the second substrate.

3. The display panel of claim 2, wherein the third surface is opposite the second surface based on the adhesive layer.

4. The display panel of claim 2, wherein the fourth surface is opposite the second surface based on the adhesive layer.

5. The display panel of claim 1, wherein the plurality of internal through holes are disposed in a pixel array region where the pixel circuits are disposed.

6. The display panel of claim 1, wherein the plurality of signal vias are disposed in a pixel array region in which the pixel circuits are disposed.

7. The display panel of claim 1, wherein the plurality of signal vias are disposed outside a pixel array area where the pixel circuits are disposed.

8. The display panel of claim 1, wherein the first portions of the pixel circuits comprise at least one light emitting element.

9. The display panel of claim 8, wherein the at least one light emitting element comprises one of a light emitting diode and an organic light emitting diode.

10. The display panel of claim 8, further comprising a gate driving circuit disposed on the fourth surface.

11. The display panel of claim 1, wherein the material of the semiconductor layer of the first substrate is the same as the material of the semiconductor layer of the second substrate.

12. The display panel of claim 1, wherein a material of the semiconductor layer of the first substrate is different from a material of the semiconductor layer of the second substrate.

13. The display panel of claim 12, wherein the semiconductor layer of the first substrate is a low temperature polysilicon material and the semiconductor layer of the second substrate is a metal oxide semiconductor material.

14. The display panel of claim 1, wherein an angle between a first extension direction of the power line disposed on the first substrate and a second extension direction of the signal line disposed on the second substrate is 0-90 degrees.

15. The display panel of claim 14, wherein the angle between the first extending direction and the second extending direction is 30-60 degrees.