CN112383463B

CN112383463B - Repeater applied to AUTBUS bus and bus network

Info

Publication number: CN112383463B
Application number: CN202011270811.5A
Authority: CN
Inventors: 邵枝晖; 崔博
Original assignee: Beijing Neuron Network Technology Co ltd
Current assignee: Beijing Neuron Network Technology Co ltd
Priority date: 2020-11-13
Filing date: 2020-11-13
Publication date: 2022-03-25
Anticipated expiration: 2040-11-13
Also published as: CN112383463A

Abstract

The application provides a repeater for AUTBUS bus, includes: a first transceiver module; the second transceiver module and the first transceiver module are provided with mirror image circuit structures and are connected with the first transceiver module through a high-speed interface; the first transceiver module is a master node, and the second transceiver module is a slave node; or the first transceiver module is a slave node, and the second transceiver module is a master node. The first transceiver module and the second transceiver module which are arranged back to back carry out information transmission through a high-speed interface, and the real-time performance of data exchange can be ensured on the basis of realizing the number of networking nodes of the AUTBUS bus and the expansion of transmission distance.

Description

Repeater applied to AUTBUS bus and bus network

Technical Field

The application relates to the technical field of industrial control and communication, in particular to a repeater applied to an AUTBUS bus and a bus network.

Background

Currently, the existing industrial field buses include CAN, 485, PROFIBUS and the like. There are two main types of relay forms used in the application process: one is a signal amplification type, and the other is a message forwarding type.

As shown in fig. 1, the signal amplification type repeater increases the transmission distance, increases the number of bus nodes, and maintains the real-time performance of signals. But the message cannot be parsed and it is possible to forward the message including the error information.

As shown in fig. 2, the message forwarding repeater has a certain bridge function while increasing the transmission distance and the number of bus nodes, so that a certain message filtering can be performed. And the two ends of the repeater can also operate under different modes and communication rates, namely, network isolation can be carried out. But a certain storage and forwarding delay is added, and the real-time performance is deteriorated.

The AUTBUS bus is a novel high-speed industrial field bus, is used for transmission and application of real-time data and non-real-time data of automatic control industrial fields such as process control, discrete control and the like, and is compatible with applications such as ISO/IEC/IEEE 802.3 Ethernet, IPv6 and the like. The AUTBUS bus adopts a two-wire non-bridging medium and has an industrial field bus with multiple nodes, high bandwidth, high real-time performance and remote transmission. The bus data bandwidth reaches 100Mbps, the maximum transmission distance is 500 meters, the minimum cycle period is 8 microseconds, and the maximum number of nodes is 256. In industrial field application, if the distance between the nodes exceeds the transmission distance of the AUTBUS bus, the transmission distance can be enlarged by using the repeater, and meanwhile, the number of the nodes on the AUTBUS bus is increased.

Disclosure of Invention

Based on the structure and the defects of the existing bus repeater, aiming at the network expansion requirement of AUTBUS two-wire system bus communication, in order to meet the requirements of real-time performance and network isolation in AUTBUS bus transmission, the application provides the repeater applied to the AUTBUS bus.

An AUTBUS repeater provided in a first embodiment of the present application includes:

a first transceiver module;

the second transceiver module and the first transceiver module are provided with mirror image circuit structures and are connected with the first transceiver module through a high-speed interface;

the first transceiver module is a master node, and the second transceiver module is a slave node; and/or

The first transceiver module is a slave node, and the second transceiver module is a master node.

According to some embodiments of the present application, the first transceiver module comprises:

the first interface circuit is connected with an external AUTBUS bus to receive AUTBUS bus signaling data and carry out physical isolation when the external AUTBUS bus fails;

the first chip supports AUTBUS bus protocol, is connected with the first interface circuit to process the AUTBUS bus signaling data, and forwards the processed AUTBUS bus signaling data through the high-speed interface.

According to some embodiments of the present application, the first interface circuit comprises: and the first isolator is connected with the first chip through a third analog switch for impedance matching.

According to some embodiments of the present application, the second transceiver module comprises:

the second chip supports an AUTBUS bus protocol and is connected with the first chip through the high-speed interface;

and the second chip is connected with an external AUTBUS bus through the second interface circuit so as to receive AUTBUS bus signaling data and carry out physical isolation when the external AUTBUS bus fails.

According to some embodiments of the present application, the second interface circuit comprises: and the second isolator and the first isolator have a mirror image circuit structure and are connected with the second chip through a fourth analog switch for impedance matching.

According to some embodiments of the present application, the first transceiver module further comprises: the first state dial switch is connected with the first chip; and/or

The second transceiver module further comprises: and the second state dial switch is connected with the second chip.

According to some embodiments of the present application, the second state dial switch and the first state dial switch control the first chip to be in a master node state and the second chip to be in a slave node state; and/or

The second state dial switch and the first state dial switch jointly control the first chip to be in a slave node state and the second chip to be in a master node state.

According to some embodiments of the present application, the first interface circuit further comprises: one end of the first analog switch is connected with the external AUTBUS bus, and the other end of the first analog switch is connected with the first isolator and is used for electrical isolation when a fault occurs; and/or

The second interface circuit further comprises: and the second analog switch is connected with the second isolator, has a symmetrical structure with the first analog switch, has one end connected with the second isolator and the other end connected with an external AUTBUS bus, and is used for electrical isolation when a fault occurs.

According to some embodiments of the present application, the first isolator comprises: the first receiving interface is connected with the first chip; the first transmitting interface is connected with the first chip; the third analog switch is arranged between the first transmitting interface and the first chip and used for matching impedance between the first transmitting interface and the first receiving interface; and/or

The second isolator includes: the second receiving interface is connected with the second chip; the second transmitting interface is connected with the second chip; the fourth analog switch is arranged between the second transmitting interface and the second chip and used for matching impedance between the second transmitting interface and the second receiving interface.

The present application further provides a bus network comprising:

a first network segment;

the first transceiver module of the repeater is connected with the first network segment;

the second network segment is connected with a second transceiver module of the repeater;

the first transceiver module is used as a main node and is connected with a terminal node in the first network segment;

and the second transceiver module is used as a slave node and connected with the control node in the second network segment.

The repeater provided by the embodiment of the application adopts a forwarding type relay design, forwards through the high-speed interface, and guarantees the real-time performance of network transmission while isolating networks at two ends, so that the repeater is matched with the AUTBUS bus in high real-time performance and high reliability.

In the repeater 100 provided in the embodiment of the present application, the first transceiver module 110 may be a master node, and the second transceiver module 120 may be a slave node. According to other embodiments of the present application, the first transceiver module 110 may be a slave node, and the second transceiver module 120 may be a master node. The main node is connected with a terminal node (TN node) in the bus, and the slave node is connected with a control node (CN node) in the bus, so that the increase of the bus transmission distance and the expansion of the node number are realized.

Additional aspects and advantages of the present application will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the present application.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without exceeding the protection scope of the present application.

FIG. 1 shows a schematic diagram of a 485 repeater in the prior art;

FIG. 2 shows a schematic diagram of a prior art CAN repeater;

fig. 3 shows a block diagram of an AUTBUS repeater according to an exemplary embodiment of the present application;

fig. 4 shows a schematic circuit diagram of an AUTBUS repeater according to an exemplary embodiment of the present application;

FIG. 5 illustrates an interface circuit composition schematic of an exemplary embodiment of the present application;

FIG. 6 is a schematic diagram of a bus network application of the first exemplary embodiment of the present application;

FIG. 7 is a schematic diagram of a bus network application of a second exemplary embodiment of the present application;

fig. 8 shows a schematic diagram of a bus network application of the third exemplary embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Furthermore, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the application. One skilled in the relevant art will recognize, however, that the subject matter of the present application can be practiced without one or more of the specific details, or with other methods, components, devices, steps, and so forth. In other instances, well-known methods, devices, implementations, or operations have not been shown or described in detail to avoid obscuring aspects of the application.

It will be understood that, although the terms first, second, etc. may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first component discussed below may be termed a second component without departing from the teachings of the present concepts. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

Those skilled in the art will appreciate that the drawings are merely schematic representations of exemplary embodiments, which may not be to scale. The blocks or flows in the drawings are not necessarily required to practice the present application and therefore should not be used to limit the scope of the present application.

AUTBUS is a multi-channel frequency division multiplexing high-bandwidth transmission technology based on a wired physical medium, and a protocol stack architecture of the AUTBUS comprises a physical layer, a data link layer and an application layer. Wherein the physical layer is a shared medium based fieldbus created on two wires based on OFDM technology. The physical layer completes the conversion of physical signals to ensure high-reliability transmission, and divides and manages physical resources in the OFDM time domain and the frequency domain to carry data of the data link layer. The physical layer provides three major interfaces of clock management service, data transmission service and physical layer management service to the data link layer. The data link layer provides three service interfaces of data link service, data link management service and clock synchronization service for the application layer. The application layer comprises a data service module and a system management service module based on real-time application and non-real-time application, a time service module and a TCP/UDP module based on IPv4/IPv 6.

In field applications, an AUTBUS bus system can support 254 active nodes, one of which is a control node and the other of which is an end user node. The control node is responsible for managing, distributing and recovering system resources, pushing system configuration to all nodes in real time, distributing communication bandwidth and the like. AUTBUS uses bus type networking, and provides fixed bandwidth data service and variable bandwidth data service supporting burst data by means of system pre-configuration or dynamic application; for periodically sampled data, bursty control, alarms, and IPv4/IPv6 data in ISO/IEC/IEEE 8802-3 Ethernet format all provide reliable and deterministic bearers. The method has the function of high-precision clock synchronization, and provides deterministic data transmission service for time-sensitive and non-time-sensitive services based on time triggering.

When the distance between the field terminal user node and the control node (such as PLC) is far, the distance limit exceeding 500m of a single network segment is that a repeater is needed to forward data, so that the communication distance is increased. The communication distance can be increased by 500m through one repeater, and if optical module conversion is added, the communication distance can be increased to several kilometers to tens of kilometers, so that data remote transmission is realized.

In order to be compatible with the novel AUTBUS bus, the application provides a repeater matched with real-time performance and reliability. The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

Fig. 3 shows a block diagram of a repeater according to an exemplary embodiment of the present application.

As shown in fig. 3, the present application provides a repeater 100 including: a first transceiver module 110 and a second transceiver module 120. The second transceiver module 120 and the first transceiver module 110 have a mirror circuit structure, and are connected to the first transceiver module 110 through the high-speed interface 130.

The first transceiver module 110 includes a first interface circuit 111, a first chip 112, and a first status dial switch 113. The first interface circuit 111 is connected to the external AUTBUS bus 200 to receive AUTBUS bus signaling data and perform physical isolation when the external AUTBUS bus fails. The first chip 112 supports an AUTBUS bus protocol, is connected to the first interface circuit 111 to process the AUTBUS bus signaling data, and forwards the processed AUTBUS bus signaling data through the high-speed interface. A first state toggle switch 113 is coupled to the first chip 112.

Similarly, the second transceiver module 110 includes a second interface circuit 121, a second chip 122, and a second status dial switch 123. The second chip, which supports the AUTBUS bus protocol, 122 is connected to the first chip 121 through the high-speed interface 130. The second state toggle 123 is connected to the second chip 122. The second chip 122 is connected to the external AUTBUS bus 200 through the second interface circuit 121 to receive AUTBUS bus signaling data and perform physical isolation when the external AUTBUS bus fails.

In the repeater 100 provided in the present application, the first transceiver module 110 may be a master node, and the second transceiver module 120 may be a slave node. According to other embodiments of the present application, the first transceiver module 110 may be a slave node, and the second transceiver module 120 may be a master node. The main node is connected with a terminal node (TN node) in the bus, and the slave node is connected with a control node (CN node) in the bus, so that the increase of the bus transmission distance and the expansion of the node number are realized.

In addition, data exchange is performed between the first chip 112 and the second chip 122 which are back-to-back through a high-speed interface, so that 10/100/1000Mbps exchange capacity can be supported, and the signal real-time performance can be ensured when the delay is tens of microseconds.

The AUTBUS repeater 100 provided by the present application can control the node states of the first transceiver module 110 and the second transceiver module 120 through the first status dial switch 113 and the second status dial switch 123, so as to adapt to different bus network application scenarios. For example, the first chip 112 is controlled to be a master node and the second chip 122 is controlled to be a slave node by the first state dial switch 113 and the second state dial switch 123. In addition, the first state dial switch 113 and the second state dial switch 123 may also control the bit rate of the first chip 112 and the second chip 122, so as to adapt to different data transmission requirements.

According to other embodiments of the present application, the first chip 112 may be further controlled to be a master node or a slave node by the first status dial switch 113; the second chip 122 is controlled by the second status dial switch 123 to be a master node or a slave node, which is not limited in this application.

Fig. 4 shows a schematic circuit structure diagram of an AUTBUS repeater according to an exemplary embodiment of the present application.

As shown in fig. 4, in the AUTBUS repeater 100 provided in the present application, the first interface circuit 111 includes a first analog switch K1 and a first isolator BALUN 1. The first analog switch K1 is connected to an external AUTBUS bus Ring 1. The first isolator BALUN1 is connected to said first analog switch K1.

The second interface circuit 121 includes a second isolator BALUN2 and a second analog switch K2. The second isolator BALUN2 is connected to the second AUTBUS chip 122. The circuit configuration of the second isolator BALUN2 is a mirror image of the circuit configuration of the first isolator BALUN 1. The second analog switch K2 is connected to the second isolator BALUN 2. The second analog switch K2 has a structure symmetrical to that of the first analog switch K1. The first analog switch K1 is connected to the first chip 112, and the second analog switch K2 is connected to the second chip 122. Signal isolation across the repeater can be achieved by a first isolator BALUN1 and a second isolator BALUN 2. Physical isolation of power supply faults across the repeater can be achieved by the first analog switch K1 and the second analog switch K2. The two analog switches are used for realizing the disconnection and connection of the line, and the disconnection of the line when the analog switches are disconnected is physical isolation.

According to some embodiments of the application, the first isolator BALUN1 or the second isolator BALUN2, may be a BALUN. The first chip 112 is used for data or information transfer with the corresponding connected AUTBUS bus segment Ring 1. The second chip 122 is used for transmitting data or information with the corresponding connected AUTBUS bus segment Ring 2. The two KY3000S chips are in real-time data interaction through a high-speed interface.

According to an example embodiment of the present application, the first chip 112 and the second chip 122 may be AUTBUS bus interface chips, which may also be referred to as two-wire bus chips, which may also be referred to as field broadband bus, such as KY3000S chips.

According to some embodiments of the present application, the high speed interface may be an RGMII high speed interface. RGMII tells the interface to use a 4-bit data interface, operate at 125MHz, and transmit data on both the rising and falling edges, so the transmission rate can reach 1000 Mbps.

Referring to fig. 4, according to an exemplary embodiment of the present application, the first state dial switch 113 includes state dial switches S1 and S2, and the second state dial switch 123 includes state dial switches S3 and S4. S1, S2, S3 and S4 are used to commonly configure the ID information, bit rate and BOOT mode of the repeater of the first chip 112 and the second chip 122, on the one hand, and to commonly control the CN or TN node states of the first chip 112 and the second chip 122, on the other hand. For example, the first chip 112 is a CN node (master node), and the second chip 122 sends the states of the corresponding state dip switches S3 and S4 to the first chip through the RGMII interface, thereby implementing control of the two chips. According to the embodiment of the application, the opening and closing states of the state dial switches S1, S2, S3 and S4 and the working state of the repeater are related to table 1.

TABLE 1 open/close state of state dial switch and working state of repeater

S1	S2	S3	S4	First chip	112	Second chip 122
							0	—	—	—	CN node	TN node
1	—	—	—	TN node	CN node
						—	0	0	0	Bit rate: 33Mbps	Bit rate: 33Mbps
—	0	0	1	Bit rate: 33Mbps	Bit rate: 50Mbps
						—	0	1	0	Bit rate: 50Mbps	Bit rate: 33Mbps
—	0	1	1	Bit rate: 50Mbps	Bit rate: 50Mbps
						—	1	0	0	Bit rate: 75Mbps	Bit rate: 50Mbps
—	1	0	1	Bit rate: 50Mbps	Bit rate: 75Mbps
						—	1	1	0	Bit rate: 75Mbps	Bit rate: 75Mbps
—	1	1	1	Bit rate: 100Mbps	Bit rate: 100Mbps

Where "1" indicates that the switch is closed, "0" indicates that the switch is open, and "-" indicates an arbitrary state.

The first isolator BALUN1 and the second isolator BALUN2 realize signal isolation type coupling, the first analog switch K1 and the second analog switch K2 realize physical isolation of faults, and when a certain network segment fails, a transmission path of the certain network segment can be cut off, so that the safety of other network segments is protected.

Fig. 5 shows a schematic diagram of an interface circuit composition according to an exemplary embodiment of the present application.

When interfaces of the existing industrial control bus are matched, mostly only a 3-port transformer is adopted for matching, and the condition of node number change is not considered. This design substantially meets the impedance matching requirements for 2-node communications. But in many cases the fieldbus is a multi-node network of more than 2 nodes. The 3-port transformer matched design has the following problems: first, when the transmitter is turned on and off, the output impedance of the TX interface is different, which causes the impedance of the interface port of the receiver to fluctuate and affects the time domain consistency of the receive impedance matching. Secondly, when a multi-node networking is performed, the n receivers are always in an operating state and stand by to receive signals, which is equivalent to that the n RX input impedances are connected in parallel, so that the total receiving impedance is reduced. When n is large, the total receiving impedance is very small, resulting in a very weak transmitter signal that can be received, affecting transmission efficiency.

For this reason, in the embodiments provided in the present application, a telling analog switch may be further provided in the first interface circuit and/or the second interface circuit. As shown in fig. 5, taking the first interface circuit 111 as an example, the first isolator BALUN1 in the first interface circuit 111 includes: the first receiving interface RX and the first transmitting interface TX are respectively connected to the first chip 112. The first interface circuit 111 may further include: the third analog switch K3 is disposed between the first transmit interface TX and the first chip 112 for matching impedance between the first transmit interface TX and the first receive interface RX.

When the first receiving interface RX works, the first chip 112 controls the third analog switch K3 to be turned off, so as to prevent the first transmitting interface TX from affecting the output impedance of the first receiving interface RX. When the first transmission interface TX is operated, the first chip 112 controls the third analog switch K3 to be closed. The impedance of the first receiving interface RX is designed to be relatively large, so that the impedance of the first transmitting interface TX is influenced slightly, and thus, the impedance can be ignored.

By opening and closing the third analog switch K3, the best interface impedance matching can be achieved. When the third analog switch K3 is closed when transmitting analog signals, the bus interface impedance is the matched impedance of the transmitter transformer, and the impedance value is consistent with the characteristic impedance of the transmission line, thereby achieving the best matching between the transmitter and the transmission line impedance. When the receiver works, the third analog switch K3 is switched off, and the bus interface impedance is the receiver interface impedance and is not influenced by the transmitter interface impedance.

Similarly, the second isolator BALUN2 in the second interface circuit includes: and the second receiving interface and the second transmitting interface are respectively connected with the second chip. The second interface circuit may further include a fourth analog switch (not shown) disposed between the second transmitting interface of the second isolator and the second chip for matching impedance between the second transmitting interface and the second receiving interface.

Fig. 6 shows a schematic diagram of a bus network application of the first exemplary embodiment of the present application.

The present application further provides a bus network comprising: a first network segment 210, the repeater 100, and a second network segment 220. The first transceiver module 110 of the repeater 100 is connected with the first network segment 210; the second network segment 220 is connected to the second transceiver module 120 of the repeater 100.

As shown in fig. 6, in the field application, in response to the situation that the field layer network node 400 is far away from the process layer PLC controller 300, the AUTBUS bus may break through the distance limit of the single segment 500m by using the AUTBUS repeater 100 provided in the present application. With 1 AUTBUS repeater 100, the communication distance can be increased by 500 m. If the optical module conversion is added, several kilometers to dozens of kilometers can be achieved. Therefore, AUTBUS two-wire system communication multi-node networking remote transmission can be realized.

Fig. 7 shows a schematic diagram of a bus network application of the second exemplary embodiment of the present application.

As shown in fig. 7, when the PLC controller is far from the field, the number of the field layer network nodes is 10, including terminals such as temperature, pressure, differential pressure, material level, liquid level, flow rate, gas-liquid, and electric. Wherein, the bus can adopt CAT5 twisted pair, and the node CN1 simulates the remote PLC. The CN node (master node) of the repeater 100 is connected to the terminal, and the TN node (slave node) thereof is connected to the PLC.

The field layer network and the process layer network are bridged by an AUTBUS bus repeater. The CN1 may control each TN node in real time. Failure of CN1 does not result in a network failure of the CN and TN nodes of AUTBUS repeater 100 and vice versa. The distance from CN1 to AUTBUS repeater 100 is 500 meters, the distance from field layer ring network is also 500 meters, and AUTBUS repeater 100 extends the control distance of CN1 to 1000 meters.

As shown in fig. 8, when a terminal TN node in the network node of the field layer is far from the field layer network, the AUTBUS repeater 100TN node accesses the field layer network, and its CN node is connected to the terminal TN node of the far end.

The chips arranged back to back in the AUTBUS repeater carry out information transmission through the high-speed RGMII interface, and the real-time performance of data exchange can be guaranteed on the basis of realizing the number of networking nodes and the expansion of transmission distance. Meanwhile, the isolation between the network segments is ensured through the analog switch. In addition, the working state of the chip can be adjusted through the state dial switch, so that the chip is suitable for different field conditions.

The foregoing detailed description of the embodiments of the present application has been presented to illustrate the principles and implementations of the present application, and the description of the embodiments is only intended to facilitate the understanding of the methods and their core concepts of the present application. Meanwhile, a person skilled in the art should, according to the idea of the present application, change or modify the embodiments and applications of the present application based on the scope of the present application. In view of the above, the description should not be taken as limiting the application.

Claims

1. A repeater for use with an AUTBUS bus, comprising:

a first transceiver module;

the second transceiver module and the first transceiver module have a mirror image circuit structure and are connected with the first transceiver module through a high-speed interface, and the high-speed interface supports the switching capacity of 10/100/1000 Mbps;

the first transceiver module is a master node, and the second transceiver module is a slave node; or

The first transceiver module is a slave node, and the second transceiver module is a master node;

wherein the first transceiver module comprises:

the first interface circuit is connected with the external AUTBUS bus to receive AUTBUS bus signaling data and perform physical isolation when the external AUTBUS bus fails.

2. The repeater according to claim 1, wherein the first transceiver module further comprises:

3. The repeater according to claim 2, wherein the first interface circuit comprises:

and the first isolator is connected with the first chip through a third analog switch for impedance matching.

4. The repeater according to claim 3, wherein the second transceiver module comprises:

5. The repeater as recited in claim 4, wherein the second interface circuit comprises:

and the second isolator and the first isolator are provided with mirror image circuit structures and are connected with the second chip through a fourth analog switch for impedance matching.

6. The repeater according to claim 4,

the first transceiver module also comprises a first state dial switch connected with the first chip; and/or

The second transceiver module further comprises a second state dial switch connected with the second chip.

7. The repeater according to claim 6, wherein the second state dial switch and the first state dial switch control the first chip to be in a master node state and the second chip to be in a slave node state; or

8. The repeater according to claim 5,

the first interface circuit further comprises:

one end of the first analog switch is connected with an external AUTBUS bus, and the other end of the first analog switch is connected with the first isolator and is used for electrical isolation when a fault occurs; and/or

The second interface circuit further comprises:

and the second analog switch and the first analog switch have a symmetrical structure, one end of the second analog switch is connected with the second isolator, the other end of the second analog switch is connected with an external AUTBUS bus, and the second analog switch and the first analog switch are used for electric isolation when a fault occurs.

9. The repeater according to claim 5,

the first isolator includes:

the first receiving interface is connected with the first chip;

the first transmitting interface is connected with the first chip;

the third analog switch is arranged between the first transmitting interface and the first chip and used for matching impedance between the first transmitting interface and the first receiving interface; and/or

The second isolator includes:

the second receiving interface is connected with the second chip;

the second transmitting interface is connected with the second chip;

the fourth analog switch is arranged between the second transmitting interface and the second chip and used for matching impedance between the second transmitting interface and the second receiving interface.

10. A bus network, comprising:

a first network segment;

the repeater of any one of claims 1 to 9, wherein a first transceiver module is connected to the first network segment;