CN112382609A - Dual damascene process - Google Patents
Dual damascene process Download PDFInfo
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- CN112382609A CN112382609A CN202011215606.9A CN202011215606A CN112382609A CN 112382609 A CN112382609 A CN 112382609A CN 202011215606 A CN202011215606 A CN 202011215606A CN 112382609 A CN112382609 A CN 112382609A
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- 238000000034 method Methods 0.000 title claims abstract description 65
- 230000009977 dual effect Effects 0.000 title claims abstract description 26
- 239000010410 layer Substances 0.000 claims abstract description 127
- 239000011229 interlayer Substances 0.000 claims abstract description 50
- 238000005530 etching Methods 0.000 claims abstract description 48
- 239000002184 metal Substances 0.000 claims abstract description 44
- 229910052751 metal Inorganic materials 0.000 claims abstract description 44
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims abstract description 38
- 239000004065 semiconductor Substances 0.000 claims abstract description 29
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 28
- 230000000903 blocking effect Effects 0.000 claims abstract description 28
- 229910052802 copper Inorganic materials 0.000 claims abstract description 28
- 239000010949 copper Substances 0.000 claims abstract description 28
- 239000011241 protective layer Substances 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 16
- 238000004528 spin coating Methods 0.000 claims abstract description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 238000009792 diffusion process Methods 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 16
- 230000004888 barrier function Effects 0.000 claims description 14
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 8
- 235000012239 silicon dioxide Nutrition 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 8
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 4
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 4
- 239000011248 coating agent Substances 0.000 description 5
- 238000000576 coating method Methods 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000012528 membrane Substances 0.000 description 2
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/101—Forming openings in dielectrics
- H01L2221/1015—Forming openings in dielectrics for dual damascene structures
- H01L2221/1026—Forming openings in dielectrics for dual damascene structures the via being formed by burying a sacrificial pillar in the dielectric and removing the pillar
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a dual damascene process method, which comprises the following steps: sequentially forming a first interlayer film, a groove etching stop layer and a second interlayer film on a semiconductor substrate, and selectively etching to form an opening of a through hole; step two, forming a TEOS layer by spin coating and curing; step three, spin-coating on the surface of the TEOS layer to form a BARC layer; fourthly, carrying out a back etching process to form a light blocking protective layer which is formed by TEOS layers in the opening of the through hole and has the same top surface height; step five, forming a photoresist pattern to open the groove forming area; sixthly, etching the second interlayer film by taking the photoresist pattern as a mask and the groove etching stopping layer as a stopping layer to form a groove; and step seven, removing the photoresist pattern and the light blocking protective layer. The invention can improve the high uniformity of the light blocking protective layer, improve the process window of groove etching, prevent the generation of metal copper damage, and especially prevent the damage of the top copper with deeper depth.
Description
Technical Field
The present invention relates to a semiconductor integrated circuit manufacturing method, and more particularly, to a Dual Damascene (DD) process.
Background
As shown in fig. 1A to 1F, the structure diagrams in each step of the existing dual damascene process method are shown. The existing dual damascene process method comprises the following steps:
step one, as shown in fig. 1A, a semiconductor substrate (not shown) is provided, and a first interlayer film 103, a trench etching stop layer 104, and a second interlayer film 105 are sequentially formed on the semiconductor substrate.
Typically, an underlying metal layer wire 101 and an underlying dielectric film (not shown) for isolating the underlying metal layer wire 101 are also formed between the bottom surface of the first interlayer film 103 and the top surface of the semiconductor substrate.
And a metal diffusion barrier layer 102 is further formed on the surface of the bottom metal layer connecting line 101 and the bottom dielectric film.
As shown in fig. 1B, selective etching is performed to form an opening 106 of a via hole (via) that passes through the second interlayer film 105, the trench etching stopper 104, and the first interlayer film 103.
Typically, the etching of the opening 106 of the via stops in the metal diffusion barrier 102.
The semiconductor substrate includes a silicon substrate.
The material of the bottom metal layer wire 101 includes copper.
The material of the first interlayer film 103 is silicon dioxide.
The material of the second interlayer film 105 is silicon dioxide.
The material of the trench etch stop layer 104 is silicon nitride.
The metal diffusion barrier layer 102 is made of silicon nitride or nitrogen-doped silicon carbide.
Step two, as shown in fig. 1C, depositing a light blocking protective layer 107, wherein the light blocking protective layer 107 completely fills the opening 106 of the through hole and extends to the entire surface of the second interlayer film 105 outside the opening 106 of the through hole.
The light blocking protective layer 107 employs a bottom anti-reflective coating (BARC).
Step three, as shown in fig. 1D, performing etching back on the light blocking protective layer 107, after the etching back, opening the surface of the second interlayer film 105 outside the opening 106 of the through hole, and the top surface of the light blocking protective layer 107 in the opening 106 of the through hole is lower than the top surface of the opening 106 of the through hole.
Step four, as shown in fig. 1E, a photoresist pattern 108 is formed to open a trench forming region, and the opening 106 of the through hole is located in the trench forming region.
Step five, as shown in fig. 1F, the second interlayer film 105 is etched by using the photoresist pattern 108 as a mask and the trench etching stop layer 104 as a stop layer to form a trench 9.
Typically, the trench etching process further includes a step of removing the metal diffusion barrier layer 102 remaining at the bottom of the opening 106 of the via.
And sixthly, removing the photoresist pattern 108 and the light blocking protective layer 107.
And seventhly, simultaneously forming a copper layer in the groove and the opening 106 of the through hole, wherein the through hole is formed by the copper layer filled in the opening 106 of the through hole, and the copper connection is formed by the copper layer filled in the groove.
As chip technology develops, the process size becomes smaller and narrower, and the window for the process becomes narrower and narrower. Although the top metal (top metal) is much larger than the size of the inner metal (inter metal), the depth of the top metal becomes deeper and deeper, and the filling uniformity of BARC is difficult to be guaranteed after the Via is formed. Some researchers have improved the uniformity of BARC fill by multiple spin-coating of BARC, but it is still difficult to meet the requirements of mass production. That is, in the prior art, the light blocking protective layer 107 is realized by BARC coating and etching back processes, the flow of BARC is not very good, and when the depth of the opening 106 of the via is deeper, the BARC layer cannot realize uniform filling of the opening 106 of the via; after the BARC is etched back, the top surface of the light blocking protective layer 107 cannot be guaranteed to be uniform in height, which reduces the process window of trench etching and finally easily causes metallic copper damage; particularly, when the top metal electrode is formed by using the conventional process, the thickness of the second interlayer film 105 to be etched is thick due to the deep depth of the top metal electrode, which makes it easy to cause damage in the top metal electrode.
Disclosure of Invention
The invention aims to solve the technical problem of providing a dual damascene process method, which can improve the high uniformity of a light blocking protective layer, improve a groove etching process window and prevent the generation of metal copper damage.
In order to solve the technical problem, the dual damascene process method provided by the invention comprises the following steps:
the method comprises the steps of firstly, providing a semiconductor substrate, sequentially forming a first interlayer film, a groove etching stop layer and a second interlayer film on the semiconductor substrate, and selectively etching to form an opening of a through hole, wherein the through hole penetrates through the second interlayer film, the groove etching stop layer and the first interlayer film.
Step two, spin coating form the TEOS layer and right the TEOS layer solidifies, the TEOS layer will the opening of through-hole is filled completely and can be extended to outside the opening of through-hole the surface of second interlaminar membrane, TEOS's mobility makes the TEOS layer has flat surface and realizes right the even packing of the opening of through-hole.
And step three, spin-coating the surface of the TEOS layer to form a BARC layer.
And fourthly, carrying out a back etching process to form a light blocking protective layer with the top surface of the same height, wherein the back etching process removes the BARC layer and the TEOS layer outside the opening of the through hole and etches the top surface of the TEOS layer in the opening of the through hole to be lower than the top surface of the second interlayer film, and the light blocking protective layer consists of the TEOS layer remained in the opening of the through hole.
And step five, forming a photoresist pattern to open a groove forming area, wherein the opening of the through hole is positioned in the groove forming area.
And sixthly, etching the second interlayer film by taking the photoresist pattern as a mask and the groove etching stopping layer as a stopping layer to form a groove.
And seventhly, removing the photoresist pattern and the light blocking protective layer.
In a further improvement, after the seventh step, a copper layer is simultaneously formed in the trench and the opening of the via, the via is composed of the copper layer filled in the opening of the via, and the copper connection is composed of the copper layer filled in the trench.
In a further improvement, a bottom metal layer connecting line and a bottom dielectric film for isolating the bottom metal layer connecting line are further formed between the bottom surface of the first interlayer film and the top surface of the semiconductor substrate.
The further improvement is that a metal diffusion barrier layer is formed on the surface of the bottom metal layer connecting line and the bottom dielectric film.
In a further improvement, in the step one, the etching of the opening of the through hole is stopped in the metal diffusion barrier layer;
and step seven, removing the metal diffusion barrier layer remained at the bottom of the opening of the through hole after removing the light blocking protective layer.
In a further refinement, the semiconductor substrate comprises a silicon substrate.
In a further improvement, the material of the bottom metal layer wiring comprises copper.
In a further refinement, the material of the first interlayer film is silicon dioxide.
In a further refinement, the material of the second interlayer film is silicon dioxide.
In a further improvement, the material of the trench etch stop layer is silicon nitride.
In a further improvement, the metal diffusion barrier layer is made of silicon nitride or nitrogen-doped silicon carbide.
In a further improvement, the via is a top layer via and the trench is a top layer trench.
In a further improvement, a semiconductor device is formed on the semiconductor substrate, and the technical nodes of the semiconductor device comprise 32nm, 28nm, 22nm, 20nm and 16nm or less.
In a further improvement, the metal layer of the semiconductor device comprises eight layers, and the top layer is an eighth layer.
In a further improvement, the first interlayer film is formed using a PECVD process.
In a further improvement, the second interlayer film is formed by a PECVD process.
In a further improvement, in the fifth step, the trench forming region also has a region not covering the opening of the through hole.
After the etching of the opening of the through hole is finished, the BARC is not used for filling the opening of the through hole, but TEOS coating with better fluidity is added before the BARC coating, the formed TEOS layer can well fill the opening of the through hole and realize a flat surface, the smoothness of the BARC layer can be improved when the BARC is formed on the basis that the TEOS layer is used as a buffer layer, and then a back etching process is carried out to form a light blocking protective layer with consistent height.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIGS. 1A-1F are structural diagrams of steps of a conventional dual damascene process;
FIG. 2 is a flow chart of a method of an embodiment of the present invention;
fig. 3A-3G are device structure diagrams in steps of a method according to an embodiment of the invention.
Detailed Description
FIG. 2 is a flow chart of a method according to an embodiment of the present invention; as shown in fig. 3A to 3G, which are device structure diagrams in each step of the method according to the embodiment of the present invention; the dual damascene process method provided by the embodiment of the invention comprises the following steps:
step one, as shown in fig. 3A, providing a semiconductor substrate, sequentially forming a first interlayer film 4, a trench etching stop layer 5 and a second interlayer film 6 on the semiconductor substrate, and performing selective etching to form an opening 7 of a through hole, wherein the through hole penetrates through the second interlayer film 6, the trench etching stop layer 5 and the first interlayer film 4.
In the embodiment of the invention, a bottom-layer metal layer connecting line 2 and a bottom-layer dielectric film 1 for isolating the bottom-layer metal layer connecting line 2 are further formed between the bottom surface of the first interlayer film 4 and the top surface of the semiconductor substrate.
And a metal diffusion barrier layer 3 is also formed on the surfaces of the bottom metal layer connecting line 2 and the bottom dielectric film 1. The etching of the opening 7 of the via is stopped in the metal diffusion barrier layer 3.
Preferably, the semiconductor substrate comprises a silicon substrate.
The material of the bottom metal layer connecting wire 2 comprises copper.
The material of the first interlayer film 4 is silicon dioxide.
The material of the second interlayer film 6 is silicon dioxide.
The material of the groove etching stop layer 5 is silicon nitride.
The metal diffusion impervious layer 3 is made of silicon nitride or nitrogen-doped silicon carbide.
Step two, as shown in fig. 3B, spin-coating forms TEOS layer 8 and is right TEOS layer 8 solidifies, TEOS layer 8 will opening 7 of through-hole is completely filled and will extend to outside opening 7 of through-hole the surface of second interlaminar membrane 6, TEOS's mobility makes TEOS layer 8 have a flat surface and realizes to the even filling of opening 7 of through-hole, also because TEOS is liquid, can with the even filling of opening 7 of through-hole through spin-coating.
And step three, as shown in fig. 3C, spin-coating on the surface of the TEOS layer 8 to form a BARC layer 9.
Step four, as shown in fig. 3D, a back etching process is performed to form a light blocking protective layer 8a with a top surface having a uniform height, the back etching process removes all the BARC layers 9 and all the TEOS layers 8 outside the openings 7 of the through holes and etches the top surfaces of the TEOS layers 8 in the openings 7 of the through holes to be lower than the top surface of the second interlayer film 6, and the light blocking protective layer 8a is composed of the TEOS layers 8 remaining in the openings 7 of the through holes. The line AA of fig. 3D indicates that the top surface of the light blocking protective layer 8a in the opening 7 of each of the through-holes is flat.
Step five, as shown in fig. 3E, the photoresist 10 is coated.
As shown in fig. 3F, exposure and development are performed to form a resist 10 pattern to open a trench forming region in which the opening 7 of the via hole is located. In fig. 3F, the open area of the photoresist 10 pattern is indicated by reference numeral 10 a.
The trench forming region also has a region not covering the opening 7 of the via hole.
And sixthly, as shown in fig. 3G, etching the second interlayer film 6 by using the photoresist 10 pattern as a mask and the groove etching stop layer 5 as a stop layer to form a groove 11.
And step seven, removing the photoresist 10 pattern and the light blocking protective layer 8 a.
After removing the light blocking protective layer 8a, the method further comprises the step of removing the metal diffusion barrier layer 3 remained at the bottom of the opening 7 of the through hole.
And after the seventh step, simultaneously forming copper layers in the trench 11 and the opening 7 of the through hole, wherein the through hole is formed by the copper layers filled in the opening 7 of the through hole, and the copper connection is formed by the copper layers filled in the trench 11.
Preferably, a semiconductor device is formed on the semiconductor substrate, and the technical nodes of the semiconductor device include 32nm, 28nm, 22nm, 20nm and 16nm or less.
The through hole is a top layer through hole, and the groove 11 is a top layer groove 11. The copper connecting wire is a top layer copper connecting wire.
The metal layer of the semiconductor device comprises eight layers, and the top layer is an eighth layer. The top copper interconnect corresponds to T8Mx and the via corresponds to T8 Vx.
The first interlayer film 4 is formed by a PECVD process. The second interlayer film 6 is formed by a PECVD process. The spin coating process of the TEOS layer 8 is compatible with the processes of the second interlayer film 6 and the first interlayer film 4, and secondary development can be avoided.
In the embodiment of the invention, after the etching of the opening 7 of the through hole is finished, the BARC is not used for filling the opening 7 of the through hole, but TEOS coating with better fluidity is added before the BARC coating, the formed TEOS layer 8 can well fill the opening 7 of the through hole and realize a flat surface, the smoothness of the BARC layer 9 can be improved when the BARC is formed on the basis that the TEOS layer 8 is used as a buffer layer, and then a back etching process is carried out to form the light blocking protective layer 8a with consistent height, so the embodiment of the invention can improve the height uniformity of the light blocking protective layer 8a, improve the etching process window of the groove 11 and prevent the generation of metallic copper damage.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (16)
1. A dual damascene process method is characterized by comprising the following steps:
providing a semiconductor substrate, sequentially forming a first interlayer film, a groove etching stop layer and a second interlayer film on the semiconductor substrate, and selectively etching to form an opening of a through hole, wherein the through hole penetrates through the second interlayer film, the groove etching stop layer and the first interlayer film;
step two, forming a TEOS layer by spin coating and curing the TEOS layer, wherein the TEOS layer completely fills the opening of the through hole and can extend to the surface of the second interlayer film outside the opening of the through hole, and the TEOS layer has a flat surface due to the fluidity of TEOS and realizes uniform filling of the opening of the through hole;
step three, spin-coating on the surface of the TEOS layer to form a BARC layer;
step four, carrying out a back etching process to form a light blocking protective layer with the top surface height consistent, wherein the back etching process removes all the BARC layers and all the TEOS layers outside the openings of the through holes and etches the top surfaces of the TEOS layers in the openings of the through holes to be lower than the top surface of the second interlayer film, and the light blocking protective layer consists of the TEOS layers remained in the openings of the through holes;
fifthly, forming a photoresist pattern to open a groove forming area, wherein the opening of the through hole is positioned in the groove forming area;
sixthly, etching the second interlayer film by taking the photoresist pattern as a mask and the groove etching stopping layer as a stopping layer to form a groove;
and seventhly, removing the photoresist pattern and the light blocking protective layer.
2. The dual damascene process of claim 1, wherein: and seventhly, simultaneously forming copper layers in the groove and the opening of the through hole, wherein the through hole is formed by the copper layers filled in the opening of the through hole, and the copper connecting line is formed by the copper layers filled in the groove.
3. The dual damascene process of claim 1, wherein: and a bottom metal layer connecting wire and a bottom dielectric film for isolating the bottom metal layer connecting wire are also formed between the bottom surface of the first interlayer film and the top surface of the semiconductor substrate.
4. The dual damascene process of claim 3, wherein: and a metal diffusion barrier layer is also formed on the surface of the bottom metal layer connecting line and the bottom dielectric film.
5. The dual damascene process of claim 4, wherein: in the first step, the etching of the opening of the through hole is stopped in the metal diffusion barrier layer;
and step seven, removing the metal diffusion barrier layer remained at the bottom of the opening of the through hole after removing the light blocking protective layer.
6. The dual damascene process of claim 4, wherein: the semiconductor substrate includes a silicon substrate.
7. The dual damascene process of claim 3, wherein: the material of the bottom metal layer connecting wire comprises copper.
8. The dual damascene process of claim 6, wherein: the material of the first interlayer film is silicon dioxide.
9. The dual damascene process of claim 6, wherein: the material of the second interlayer film is silicon dioxide.
10. The dual damascene process of claim 6, wherein: the material of the groove etching stopping layer is silicon nitride.
11. The dual damascene process of claim 6, wherein: the metal diffusion impervious layer is made of silicon nitride or nitrogen-doped silicon carbide.
12. The dual damascene process of claim 1, wherein: the through hole is a top layer through hole, and the groove is a top layer groove.
13. The dual damascene process of claim 12, wherein: the semiconductor substrate is provided with a semiconductor device, and technical nodes of the semiconductor device comprise 32nm, 28nm, 22nm, 20nm and 16nm or less.
14. The dual damascene process of claim 8, wherein: the first interlayer film is formed by a PECVD process.
15. The dual damascene process of claim 9, wherein: the second interlayer film is formed by a PECVD process.
16. The dual damascene process of claim 12, wherein: in step five, the trench forming region also has a region not covering the opening of the through hole.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5883006A (en) * | 1997-12-12 | 1999-03-16 | Kabushiki Kaisha Toshiba | Method for making a semiconductor device using a flowable oxide film |
| JP2003234401A (en) * | 2001-12-07 | 2003-08-22 | Matsushita Electric Ind Co Ltd | Method for manufacturing semiconductor device |
| US20040087164A1 (en) * | 2002-10-31 | 2004-05-06 | Taiwan Semiconductor Manufacturing Company | Scum solution for chemically amplified resist patterning in cu/low k dual damascene |
| US20050003656A1 (en) * | 2002-08-21 | 2005-01-06 | Jin-Sung Chung | Metal interconnections for semiconductor devices including a buffer layer on a trench sidewall |
| CN101996934A (en) * | 2009-08-20 | 2011-03-30 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
-
2020
- 2020-11-04 CN CN202011215606.9A patent/CN112382609B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5883006A (en) * | 1997-12-12 | 1999-03-16 | Kabushiki Kaisha Toshiba | Method for making a semiconductor device using a flowable oxide film |
| JP2003234401A (en) * | 2001-12-07 | 2003-08-22 | Matsushita Electric Ind Co Ltd | Method for manufacturing semiconductor device |
| US20050003656A1 (en) * | 2002-08-21 | 2005-01-06 | Jin-Sung Chung | Metal interconnections for semiconductor devices including a buffer layer on a trench sidewall |
| US20040087164A1 (en) * | 2002-10-31 | 2004-05-06 | Taiwan Semiconductor Manufacturing Company | Scum solution for chemically amplified resist patterning in cu/low k dual damascene |
| CN101996934A (en) * | 2009-08-20 | 2011-03-30 | 中芯国际集成电路制造(上海)有限公司 | Method for manufacturing semiconductor device |
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| CN112382609B (en) | 2024-03-08 |
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