CN112382334A

CN112382334A - Testing device and testing method for mobile memory

Info

Publication number: CN112382334A
Application number: CN202011230058.7A
Authority: CN
Inventors: 张磊; 陈世兴; 颜振亮; 罗文良; 姜文贵
Original assignee: Runsheng System Testing Shenzhen Co ltd
Current assignee: Runsheng System Testing Shenzhen Co ltd
Priority date: 2020-11-06
Filing date: 2020-11-06
Publication date: 2021-02-19
Also published as: TW202219970A; TWM609546U; TWI789651B

Abstract

The present invention provides a memory testing device and a memory testing method for mobile memory. The memory test device includes a host and a plurality of test boards. The host provides multiple test flows. The plurality of memory chips to be tested are correspondingly arranged on the plurality of test boards in a one-to-one manner or a multi-to-one manner. Each of the plurality of test boards includes at least one application processor. The application processors are directly connected to the corresponding memory chips to be tested in a one-to-one manner. The activated application processor of each of the plurality of test boards receives at least one of the plurality of test procedures stored in the corresponding test board, and based on at least one of the plurality of test procedures, corresponds to the corresponding test procedure. Test the memory chip.

Description

Testing device and testing method for mobile memory

Technical Field

The present invention relates to a test apparatus and a test method, and more particularly, to a memory test apparatus and a memory test method capable of testing a plurality of memory chips to be tested.

Background

Generally, a memory test device uses a single motherboard to test at least one memory chip under test. In order to test a plurality of memory chips to be tested, the testing apparatus may test the plurality of memory chips to be tested simultaneously by a testing host. Based on the large increase in the demand of the memory chips, the testing apparatus needs to further accelerate the test throughput (throughput) of the memory chips to be tested, and can also test the memory chips to be tested simultaneously with different test conditions. The above-mentioned need is one of the subjects which the skilled person endeavors to investigate.

Disclosure of Invention

The invention provides a memory test device and a memory test method, which can accelerate the test output of a plurality of memory chips to be tested and can automatically test the plurality of memory chips to be tested simultaneously by using different test conditions.

The memory test device is used for testing a plurality of memory chips to be tested. The memory test device comprises a host and a plurality of test boards. The host is configured to provide a plurality of test flows. The test boards are respectively coupled to the host to receive the test flows and store the test flows. The memory chips to be tested are correspondingly arranged on the test boards in a one-to-one mode or a many-to-one mode. Each of the plurality of test boards includes at least one application processor. The at least one application processor is respectively directly connected with the corresponding memory chips to be tested in the plurality of memory chips to be tested in a one-to-one mode. The at least one application processor is a reduced instruction set processor. The at least one application processor of each of the plurality of test boards after being started receives at least one of the plurality of test procedures stored on the corresponding test board, and tests the corresponding memory chip to be tested based on the at least one of the plurality of test procedures.

The memory test method is used for testing a plurality of memory chips to be tested by the memory test device. The memory test device comprises a plurality of test boards. Each of the plurality of test boards includes at least one application processor. The at least one application processor is a reduced instruction set processor. The memory test method comprises the following steps: storing a plurality of test procedures by the plurality of test boards; correspondingly arranging the memory chips to be tested on a plurality of test boards in a one-to-one mode or a many-to-one mode, so that each application processor is directly connected with the corresponding memory chip to be tested in the memory chips to be tested in a one-to-one mode; and receiving at least one of a plurality of test procedures stored on the corresponding test board by the at least one application processor of each of the plurality of test boards after being started, and testing the corresponding memory chip to be tested based on at least one of the plurality of test procedures.

Based on the above, the memory test apparatus and the memory test method of the present invention enable the memory chips to be tested to be correspondingly disposed on the plurality of test boards in a one-to-one manner or a many-to-one manner, and the application processor is directly connected to the corresponding memory chips to be tested in a one-to-one manner. Therefore, the application processor can directly perform one-to-one test on the corresponding memory chip to be tested. Therefore, the invention can accelerate the test output of a plurality of memory chips to be tested and can automatically test the plurality of memory chips to be tested simultaneously under different test conditions.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1 is a schematic diagram illustrating an apparatus of a memory test apparatus according to an embodiment of the invention;

fig. 2 is a flowchart illustrating a method of testing a memory according to an embodiment of the invention;

FIG. 3 is a diagram illustrating a host according to an embodiment of the invention;

FIG. 4 is a schematic diagram of a testing board according to an embodiment of the present invention;

fig. 5 is a flowchart illustrating another method for testing a memory according to an embodiment of the invention.

Description of the reference numerals

100: a memory test device;

110: a host;

111: an operating system;

112: a writing tool;

113: a database;

120_1 to 120_ n: a test board;

121_1 to 121_ n: an application processor;

122_ 1: a storage circuit;

123_ 1: testing the power supply;

124_ 1: an adapter;

1231: a power management controller;

1232: a voltage regulator;

130: a sorter;

ADD: testing the address;

CMD: a test command;

CS: a control signal;

DP _ 1: a drive power supply;

DAT1, DAT 2: data;

DUT _1 to DUT _ n: a memory chip to be tested;

EP: an external power supply;

TI _1 to TI _ n: testing information;

TP 01-TP 40: testing process;

s100, S200: a memory test method;

s110 to S130: a step of;

s201 to S212: a step of;

VDD1, VDD2, VDDQ: and testing the power supply.

Detailed Description

Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.

Referring to fig. 1, fig. 1 is a schematic device diagram illustrating a memory test apparatus according to an embodiment of the invention. In this embodiment, the memory test apparatus 100 is suitable for testing the memory chips DUT _1 to DUT _ n to be tested. The memory test device 100 includes a host 110 and test boards 120_1 to 120_ n. The host 110 may provide 40 test flows TP 01-TP 40 (the number of test flows is not limited in the present invention). The host 110 may be any type of central control electronic device, such as an industrial computer, a notebook computer, or a personal computer with an operation interface. In this embodiment, the Memory chips DUT _1 to DUT _ n are Dynamic Random Access Memory (DRAM) chips applied to the mobile electronic device, respectively. Further, the memory chips DUT _1 to DUT _ n to be tested are Low Power Double Data Rate (LPDDR) dram chips, such as LPDDR4, LPDDR4X, LPDDR5 or higher specification dram chips, respectively. In this embodiment, n may be any integer greater than 2 (e.g., 128 or 256).

In the present embodiment, the test boards 120_1 to 120_ n are respectively coupled to the host 110. The testing boards 120_1 to 120_ n receive the testing processes TP01 to TP40 from the host 110, respectively, and store the testing processes TP01 to TP40, respectively. In the present embodiment, the memory chips DUT _1 to DUT _ n to be tested are correspondingly disposed on the test boards 120_1 to 120_ n in a one-to-one manner or a many-to-one manner. For example, the test boards 120_ 1-120 _ n can communicate with the host 110 through any type of communication interface (e.g., USB, UART, WiFi, etc.). The memory chip under test DUT _1 is disposed on the test board 120_ 1. The memory chip under test DUT _2 is disposed on the test board 120_2, and so on.

In the present embodiment, each of the test boards 120_ 1-120 _ n includes an Application Processor (Application Processor)121_ 1-121 _ n. The application processors 121_ 1-121 _ n are directly connected with the corresponding memory chips DUT _ 1-DUT _ n to be tested. For example, on the test board 120_1, the application processor 121_1 is directly connected to the memory chip under test DUT _ 1. On the test board 120_2, the application processor 121_2 is directly connected to the memory chip under test DUT _2, and so on. In the embodiment, the application processors 121_1 to 121_ n receive at least one of the test flows TP01 to TP40 stored in the corresponding test boards 120_1 to 120_ n, and test the corresponding memory chips DUT _1 to DUT _ n to be tested based on the received at least one of the test flows TP01 to TP 40. In the embodiment, the application processors 121_1 to 121_ n are processors (e.g., ARM processors) conforming to various versions of Reduced Instruction Set (RISC/RISC-V) standards.

For example, the application processor 121_1 receives the test procedures TP 01-TP 20 stored in the test board 120_1, and tests the memory chip DUT _1 according to the test procedures TP 01-TP 20. The application processor 121_2 receives the testing processes TP 01-TP 20 stored in the testing board 120_2, and tests the memory chip DUT _2 to be tested according to the testing processes TP 01-TP 20. The application processor 121_ n receives the testing processes TP 30-TP 40 stored in the testing board 120_ n, and tests the memory chip DUT _ n to be tested according to the testing processes TP 30-TP 40.

It should be noted that the memory chips DUT _1 to DUT _ n to be tested are correspondingly disposed on the test boards 120_1 to 120_ n in a one-to-one manner. The application processors 121_1 to 121_ n respectively disposed on the test boards 120_1 to 120_ n are directly connected to the corresponding memory chips DUT _1 to DUT _ n to be tested in a one-to-one manner. Therefore, the application processors 121_1 to 121_ n can directly perform one-to-one test on the corresponding memory chips DUT _1 to DUT _ n to be tested. Compared to Application Specific Integrated Circuits (ASICs) or Field Programmable Gate Arrays (FPGAs) used in a general test apparatus, the Application processors 121_1 to 121_ n of the present embodiment have higher processing performance. In this way, the memory test apparatus 100 can accelerate the test throughput of the memory chips DUT _1 to DUT _ n to be tested, and can automatically test the memory chips DUT _1 to DUT _ n to be tested simultaneously under different test conditions.

In this embodiment, the memory test apparatus 100 can also automatically test the memory chips DUT _1 to DUT _ n to be tested through different test flows with different test speeds to obtain test results corresponding to the different test speeds. The memory test apparatus 100 also classifies the memory chips DUT _1 to DUT _ n to be tested based on the test results corresponding to the different test speeds.

In addition, the application processors 121_1 to 121_ n are processors conforming to various versions of the reduced instruction set. Compared with the CPU, the application processors 121_1 to 121_ n of the present embodiment have lower cost. Therefore, the cost of the memory test apparatus 100 can be reduced. In addition, the automatic test of the application processors 121_1 to 121_ n for testing the memory chips DUT _1 to DUT _ n is close to the access of the mobile device to the memory chips.

In this embodiment, the application processor 121_1 tests the memory chip DUT _1 to be tested to obtain the test information TI _1, and provides the obtained test information TI _1 to the host 110. The test information TI _1 is information for representing whether the memory chip DUT _1 under test passes the test. The application processor 121_2 tests the memory chip under test DUT _2 to obtain test information TI _2, and provides the obtained test information TI _2 to the host 110. The test information TI _2 is used to represent whether the memory chip DUT _2 under test passes the test, and so on.

In this embodiment, the memory test apparatus 100 further includes a sorter 130. The sorter 130 may be coupled to the host 110 via a wired or wireless communication interface. In the present embodiment, the communication interface is, for example, RJ45 (the invention is not limited thereto). The memory test apparatus 100 is capable of correspondingly disposing the memory chips DUT _1 to DUT _ n to be tested on the test boards 120_1 to 120_ n in a one-to-one manner by the sorter 130. The host 110 instructs the sorter 130 to sort the memory chips DUT _1 to DUT _ n to be tested according to the test information TI _1 to TI _ n.

For example, the test information TI _1 represents that the memory chip DUT _1 under test Passes (PASS). The test information TI _2 represents that the memory chip under test DUT _2 passes the test (PASS). The test information TI _ n indicates that the memory chip DUT _ n under test FAILs the test (FAIL). After the test is finished, the host 110 controls the classifier 130 according to the test information TI _1, TI _2, TI _ n. The handler 130 takes the memory chip under test DUT _1 out of the test board 120_1 in response to the control of the host 110 and moves the memory chip under test DUT _1 to a first tray (not shown). The first tray is a tray for receiving memory modules that PASS a test (PASS). The handler 130 takes the memory chip under test DUT _2 out of the test board 120_2 and moves the memory chip under test DUT _2 to the first tray. The sorter 130 takes the memory chip under test DUT _ n out of the test board 120_ n and moves the memory chip under test DUT _ n to a second tray (not shown). The second tray is a tray for receiving memory modules that FAIL a test (FAIL).

In some embodiments, at least one of the test boards 120_ 1-120 _ n may each include a plurality of application processors. Here, the test board 120_1 includes 3 application processors for example. The 3 memory chips to be tested are correspondingly arranged on the test board 120_1 in a many-to-one manner. The 3 application processors disposed in the test board 120_1 test the 3 memory chips to be tested in a one-to-one manner. For example, the first application processor of the 3 application processors tests the first to-be-tested memory chip of the 3 to-be-tested memory chips. And a second application processor in the 3 application processors tests a second memory chip to be tested in the 3 memory chips to be tested. And the third application processor in the 3 application processors tests a third memory chip to be tested in the 3 memory chips to be tested.

Referring to fig. 1 and fig. 2, fig. 2 is a flowchart illustrating a method for testing a memory according to an embodiment of the invention. In the embodiment, the memory test method S100 is applicable to the memory test apparatus 100. In step S110, the test boards 120_1 to 120_ n receive the test flows TP01 to TP40, respectively. In the case where no additional test flow is generated, step S110 may not be performed any more. Once the new test flow is generated, the host 110 can execute step S110 according to the actual test requirement, so as to provide the new test flow to the test boards 120_1 to 120_ n. In step S120, the memory chips DUT _1 to DUT _ n to be tested are correspondingly disposed on the test boards 120_1 to 120_ n in a one-to-one manner, or are correspondingly disposed on at least one of the test boards 120_1 to 120_ n in a many-to-one manner, so that the application processors 121_1 to 121_ n are directly connected to the corresponding memory chips DUT _1 to DUT _ n to be tested in a one-to-one manner, respectively. The implementation details of steps S110 and S120 can be sufficiently taught or explained in the related embodiment of fig. 1, and therefore cannot be reiterated here. In step S130, the memory test device 100 attempts to boot up the test boards 120_1 to 120_ n. If the memory test device 100 knows that at least one of the test boards 120_ 1-120 _ n cannot be activated, the memory test device 100 determines that the test board that cannot be activated is Failed (FAIL) and cannot be tested. The application processor of the test board successfully started receives at least one of the test flows TP 01-TP 40 stored in the test board, and tests the corresponding memory chip to be tested based on at least one of the test flows TP 01-TP 40. For example, taking test board 120_1 as an example, if test board 120_1 successfully boots up, application processor 121_1 receives test flows TP 01-TP 20 stored in test board 120_1, and tests the memory chip DUT _1 under test based on test flows TP 01-TP 20.

It should be noted that, before testing, the test flows TP 01-TP 40 are pre-stored in test board 120_ 1. Therefore, once the test board 120_1 is successfully booted, the application processor 121_1 obtains the test procedures TP 01-TP 20 from the test board 120_1, instead of obtaining the test procedures TP 01-TP 20 from the host 110. Thus, the time for the application processor 121_1 to obtain the test flows TP 01-TP 20 can be shortened.

In the present embodiment, step S110 is performed before step S120. However, the invention is not limited thereto. In some embodiments, step S110 may be performed between steps S120, S130.

Referring to fig. 1 and fig. 3, fig. 3 is a schematic diagram of a host according to an embodiment of the invention. In the present embodiment, the host 110 includes an operating system 111 and a writing tool 112. The operating system 111 is operated to edit the test flows TP 01-TP 40. The writing tool 112 is coupled to the operating system 111. The write tool 112 is operated to provide the edited test flows TP 01-TP 40 to the test boards 120_ 1-120 _ n in advance. In this embodiment, the host 110 further includes a database 113. The database 113 is coupled to the operating system 111. The database 113 can at least store the edited test flows TP 01-TP 40, the test information TI _ 1-TI _ n of the memory chips DUT _ 1-DUT _ n to be tested, and the statistical results associated with the test information TI _ 1-TI _ n. In this embodiment, the database 113 may be implemented by a server or a storage device. In some embodiments, the database 113 may be located external to the host 110.

Referring to fig. 1 and fig. 4, fig. 4 is a schematic view of a test board according to an embodiment of the invention. In the present embodiment, the test board 120_1 includes an application processor 121_1, a storage circuit 122_1, and a test power supply 123_ 1. The storage circuit 122_1 is coupled to the host 110 and the application processor 121_ 1. The storage circuit 122_1 stores the test flows TP 01-TP 40 from the host 110. The host 110 writes the test flows TP 01-TP 40 into the storage circuit 122_1 through the write tool 112 shown in FIG. 3, for example. After the test board 120_1 is activated, the application processor 121_1 receives the test procedures TP 01-TP 20 from the storage circuit 122_1, for example. In the embodiment, the storage circuit 122_1 may be a Flash memory (Flash memory), for example. In some embodiments, the storage circuit 122_1 may also be implemented by other memories.

For example, the application processor 121_1 can inform the host 110 of the address block to write or record to the storage circuit 122_ 1. Before testing (as step S110 in fig. 2), the host 110 can write or write the test procedures TP 01-TP 40 into a specified address block (e.g., a pre-loader or a lite kernel block in a flash memory) of the storage circuit 122_1 according to the instruction of the application processor 121_ 1. In this way, when starting the test (as step S130 in fig. 2), the application processor 121_1 can receive at least one of the test flows TP 01-TP 40 from the designated address block of the storage circuit 122_ 1.

In the embodiment, the test power supply 123_1 is coupled to the application processor 121_ 1. The test power supply 123_1 provides at least one test power to the memory chip under test DUT _1 in response to the control of the application processor 121_ 1. In the present embodiment, the test power supply 123_1 includes a power management controller 1231 and a voltage regulator 1232. The power management controller 1231 provides the corresponding control signal CS according to one of the test procedures TP 01-TP 20. The voltage regulator 1232 regulates the voltage of the plurality of test power supplies (e.g., VDD1, VDD2, VDDQ, but not limited thereto) to a voltage corresponding to one of the test procedures TP 01-TP 20 according to the control signal CS. For example, during a test period, the power management controller 1231 provides the control signal CS corresponding to the test flow TP01 according to the test flow TP 01. The voltage regulator 1232 adjusts the voltages of the test power supplies VDD1, VDD2, VDDQ to the voltage corresponding to the test flow TP01 according to the control signal CS, and the voltage regulator 1232 further provides the adjusted test power supplies VDD1, VDD2, VDDQ to the memory chip DUT _1 under test.

In addition, during the test process, the application processor 121_1 provides the test command CMD, the test address ADD and the data DAT1 with corresponding timing to the memory chip DUT _1 under test based on one of the test flows TP01 to TP20, and receives the data DAT2 fed back by the memory chip DUT _1 under test. Application processor 121_1 obtains test information TI _1 according to data DAT2 and provides test information TI _1 to host 110. The host 110 determines whether the memory chip DUT _1 under test passes the test according to the test information TI _ 1. In some embodiments, the application processor 121_1 may also determine whether the memory chip DUT _1 under test passes the test according to the test information TI _ 1.

In this embodiment, the test board 120_1 further includes an adapter 124_ 1. The adaptor 124_1 receives the external power EP and converts the external power EP into the driving power DP _1 to drive at least the application processor 121_ 1. That is, the driving power sources of the test boards 120_ 1-120 _ n are independent of each other.

Referring to fig. 1, fig. 4 and fig. 5, fig. 5 is a flowchart illustrating another method for testing a memory according to an embodiment of the invention. In the embodiment, the memory test method S200 is applicable to the memory test apparatus 100. The test board of this embodiment is exemplified by test board 120_ 1. In step S201, the test board 120_1 first receives the test flows TP01 to TP40, and stores the test flows TP01 to TP40 in the storage circuit 122_ 1. In step S202, the memory chip under test DUT _1 is correspondingly disposed on the test board 120_1, such that the application processor 121_1 is directly connected to the memory chip under test DUT _ 1.

In step S203, the test board 120_1 starts to be activated. If the test board 120_1 is not successfully booted, the memory test method S200 proceeds to step S204 to determine that the test board 120_1 fails. On the other hand, if the test board 120_1 is successfully activated, the application processor 121_1 receives at least one of the test procedures TP 01-TP 40 from the storage circuit 122_1 in step S205. In the embodiment, the application processor 121_1 receives the test flow TP01 from the storage circuit 122_1 as an example. In step S205, the application processor 121_1 knows the supply timing of the data DAT1, the supply timing of the test power (e.g., VDD1, VDD2, VDDQ, although the invention is not limited thereto), and the test address ADD based on the test flow TP 01. In step S206, the application processor 121_1 defines a test address range of the test address ADD based on the test flow TP 01. After steps S205 and S206 are completed, the application processor 121_1 tests the memory chip DUT _1 to be tested in step S207. In this embodiment, the test addresses of the test address range may be consecutive or scattered.

In step S207, the application processor 121_1 tests each test address ADD of the memory chip DUT _1 to be tested based on the test flow TP 01. In the test, the application processor 121_1 determines whether the tested address is the last address in the test address range after each test address ADD is tested (step S208). If the application processor 121_1 confirms that the currently tested test address ADD is not the last address in the test address range, it indicates that the test flow TP01 has not yet ended. The application processor 121_1 counts the tested addresses (step S209). On the other hand, if the application processor 121_1 confirms that the current test address ADD is the last address in the test address range, it indicates that the test flow TP01 ends. The application processor 121_1 obtains test information TI _ 1.

For example, in step S207, the application processor 121_1 starts testing a first address in the test address ADD of the memory chip DUT _1 to be tested, and in step S208, determines that the tested first address is not a last address in the test address range. Therefore, the application processor 121_1 counts in step S209 to generate a count value, and goes to step S207 to test the second address in the test address ADD, and determines in step S208 that the tested second address is not the last address in the test address range. Therefore, the application processor 121_1 counts in step S209, and so on. In the present embodiment, it can be seen that, in the case that the tested address is not the last address in the test address range, the application processor 121_1 executes the loop of steps S207 to S209. The operation of counting described above is an Increment (Increment) count. The count value is incremented by 1 every time the loop of steps S207-S209 is executed. Under some test requirements, such as requirements of having a larger test address range or having a longer test time, the test flow TP01 may need to be completed in a segmented manner. Therefore, the application processor 121_1 obtains the count value after completing the first segment test in the test flow TP 01. This count value is associated with the last tested address in the first segment test. In this way, the application processor 121_1 can continue to perform the next segment test in the test flow TP01 according to the count value.

In some embodiments, the operation of counting may be counting by decrementing (Decrement). The application processor 121_1 is capable of determining an initial count value (e.g., a number of bits greater than or equal to the test address range) when defining the test address range for the test address ADD. The count value is decremented by 1 every time the loop of steps S207-S209 is executed. Thus, the count value obtained in the down-count manner may also be associated with the last tested address.

In the present embodiment, the application processor 121_1 provides the test information TI _1 to the host 110 after obtaining the test information TI _ 1. When the memory chip DUT _1 under test is determined to pass the test in step S210, the host 110 determines that the memory chip DUT _1 under test is qualified in step S211. On the other hand, when the memory chip DUT _1 under test is determined not to pass the test in step S210, the host 110 determines the memory chip DUT _1 under test as a fail in step S212.

In summary, the memory test apparatus and the memory test method of the invention enable the memory modules to be tested to be correspondingly disposed on the plurality of test boards in a one-to-one manner. The application processor of the test board is directly connected to the corresponding memory chip to be tested. Therefore, the application processor can directly perform one-to-one test on the memory chips to be tested on each test board. Therefore, the invention can greatly accelerate the test output of a plurality of memory chips to be tested and can automatically test the plurality of memory chips to be tested simultaneously under different test conditions.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. a memory testing device, in order to test a plurality of memory chips to be tested, it is characterized in that, described memory testing device comprises:

a host, configured to provide multiple test flows; and

a plurality of test boards, respectively coupled to the host to receive the plurality of test procedures and store the plurality of test procedures, wherein the plurality of memory chips to be tested are corresponding to one-to-one or many-to-one set on the multiple test boards, wherein each of the multiple test boards includes:

At least one application processor is directly connected to the corresponding memory chip to be tested among the plurality of memory chips to be tested in a one-to-one manner, wherein the at least one application processor is a reduced instruction set (Reduced Instruction Set Computer, RISC) processor,

Wherein, the at least one application processor of each of the plurality of test boards after being started receives at least one of the plurality of test procedures stored on the corresponding test board, and based on the results of the plurality of test procedures At least one of them is to test the corresponding memory chip to be tested.

2 . The memory testing device of claim 1 , wherein the plurality of memory chips to be tested are dynamic random access memory chips applied to mobile electronic devices, respectively. 3 .

3. The memory test device according to claim 1, wherein each of the plurality of test boards further comprises:

a storage circuit, coupled to the host and the at least one application processor, configured to store the plurality of test procedures,

Wherein, after the corresponding test board is activated, the at least one application processor receives at least one of the plurality of test procedures from the storage circuit.

4. The memory test device according to claim 1, wherein each of the plurality of test boards further comprises:

Test the power supply, including:

a power management controller, coupled to the at least one application processor, configured to provide control signals according to one of the test procedures; and

A voltage regulator, coupled to the power management controller, is configured to provide at least one test power source according to the control signal.

5 . The memory testing apparatus of claim 1 , wherein the at least one application processor is further configured to define a test address range based on at least one of the plurality of test procedures, and according to the The address range is tested to test the corresponding memory chip under test.

6. The memory testing apparatus of claim 1, wherein the at least one application processor is further configured to count tested addresses.

7. memory testing device according to claim 1, is characterized in that:

the at least one application processor is also configured to test the corresponding memory chip under test to obtain test information and to provide the test information to the host, and

The test information is information used to represent whether the corresponding memory chip to be tested passes the test.

8. The memory testing device according to claim 7, wherein the memory testing device further comprises:

A sorter, wherein the host is further configured to instruct the sorter to sort the plurality of memory chips under test according to the test information.

9. A memory testing method for testing a plurality of memory chips to be tested by a memory testing device, wherein the memory testing device comprises a plurality of test boards, wherein each of the plurality of test boards comprises at least one application processor , wherein the application processor is a Reduced Instruction Set Computer (RISC) processor, wherein the memory testing method includes:

storing a plurality of test procedures by the plurality of test boards;

The plurality of memory chips to be tested are correspondingly arranged on a plurality of test boards in a one-to-one manner or a multi-to-one manner, so that each of the at least one application processor is in a one-to-one manner with the plurality of memory chips to be tested The corresponding memory chip under test in the chip is directly connected; and

At least one of the plurality of test procedures stored on the corresponding test board is received by the at least one application processor of each of the plurality of test boards after being activated, and based on at least one of the plurality of test procedures First, test the corresponding memory chip to be tested.

10 . The memory testing method according to claim 9 , wherein the plurality of memory chips to be tested are respectively dynamic random access memory chips applied to mobile electronic devices. 11 .

11 . The memory testing method according to claim 9 , wherein the at least one application processor of each of the plurality of test boards after being started receives at least one of the plurality of test procedures. 11 . Steps include:

storing the plurality of test procedures by a storage circuit; and

After the corresponding test board is activated, at least one of the plurality of test procedures is received from the storage circuit by the at least one application processor.

12. The memory testing method according to claim 9, wherein the memory testing method further comprises:

At least one test power is provided to the corresponding memory chip under test in response to the control of the at least one application processor.

13. The memory testing method according to claim 9, wherein the step of testing the corresponding memory chip under test based on at least one of the plurality of test procedures comprises:

A test address range is defined based on at least one of the plurality of test procedures, and the corresponding memory chip under test is tested according to the test address range.

14. The memory testing method according to claim 9, wherein the step of testing the corresponding memory chip under test based on at least one of the plurality of test procedures comprises:

Count the tested addresses.

15. The memory testing method according to claim 9, wherein the memory testing method further comprises:

The corresponding memory chip to be tested is tested to obtain test information, wherein the test information is information used to characterize whether the corresponding memory chip to be tested passes the test.

16. The memory testing method according to claim 15, wherein the memory testing method further comprises:

The plurality of memory chips to be tested are classified according to the test information.