CN112380805A - First-layer metal layout method and integrated circuit - Google Patents
First-layer metal layout method and integrated circuit Download PDFInfo
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Abstract
本发明提供了一种第一层金属布局方法，包括计算得到绕线格点线间距，以所述第一层金属a或所述第一层金属b的长度方向为第一方向，然后以所述第一方向为延伸方向以及间距为所述绕线格点线间距设置多条绕线格点线，其中，所述第一层金属a和所述第一层金属b的长度方向相同，沿所述绕线格点线设置第一层金属c，沿所述绕线格点线设置第一层金属e和第一层金属f，增加了第一层金属的布线通道数，提高了布通率，且有源区和栅极接触孔数量大于或等于一个，无需额外占用第一层金属的布线通道，接触孔数量增加，从而增加了版图的可靠性。本发明还提供了一种集成电路。
The present invention provides a first-layer metal layout method, which includes calculating the grid point line spacing of the windings, taking the length direction of the first-layer metal a or the first-layer metal b as the first direction, and then using all The first direction is the extension direction and the spacing is the spacing between the winding grid points and a plurality of winding grid lines are arranged, wherein the length directions of the first layer of metal a and the first layer of metal b are the same, The first layer of metal c is arranged on the winding grid point line, and the first layer of metal e and the first layer of metal f are arranged along the winding grid point line, which increases the number of wiring channels of the first layer of metal and improves the routing and the number of active area and gate contact holes is greater than or equal to one, without additionally occupying the wiring channel of the first layer of metal, and the number of contact holes is increased, thereby increasing the reliability of the layout. The present invention also provides an integrated circuit.
Description
Technical Field
The present invention relates to the field of integrated circuit technologies, and in particular, to a first-layer metal layout method and an integrated circuit.
Background
In the field of integrated circuits, each standard cell is often designed to have the same height for the convenience of wiring, and the width can be adjusted according to actual conditions.
In the present stage, most of standard cells are wired by using a first layer of metal inside the cells, the horizontal wiring and the vertical wiring are both available, and a power supply rail and a ground rail are all transversely connected together through the first layer of metal, so that after the standard cells are spliced to form an array, the first layer of metal can hardly be used for wiring, the wiring resources of the first layer of metal are wasted, and the wiring rate of the first layer of metal is low. In addition, because only the first layer of metal routing is used inside a single standard cell, contact holes on active regions and gates need to be removed, and thus reliability of a layout is reduced.
Chinese patent publication No. CN107464802A discloses an integrated circuit and a standard cell library, wherein the integrated circuit includes at least one cell. The at least one cell includes: a cell region defined by a cell boundary; a power line structure parallel to and extending in a first direction along the cell boundary and including a first power line extending in the first direction along the cell boundary, a plurality of metal islands spaced apart from each other in the first direction over the first power line, and a second power line extending in the first direction over the plurality of metal islands; and a signal line structure disposed in the cell region at the same level as the first power line and the plurality of metal islands. A separation distance between each of the plurality of metal islands and a portion of the signal line structure at the same level as the plurality of metal islands is equal to or greater than a critical separation distance. In the invention patent, the routing resources of the first layer of metal are wasted, so that the routing rate of the first layer of metal is low, and some contact holes on an active region and a grid electrode need to be removed, so that the reliability of a standard cell is reduced.
Therefore, there is a need for a new first-level metal layout method and an integrated circuit to solve the above-mentioned problems in the prior art.
Disclosure of Invention
The invention aims to provide a first-layer metal layout method and an integrated circuit, which improve the routing rate of first-layer metal in a layout and increase the reliability of the layout.
In order to achieve the above object, the first layer metal layout method of the present invention includes the following steps:
calculating to obtain the minimum width of the first layer of metal according to the width of the first layer of metal a at the source end of the transistor and the minimum distance between the first layer of metal, or calculating to obtain the minimum width of the first layer of metal according to the width of the first layer of metal b at the drain end of the transistor and the minimum distance between the first layer of metal;
calculating the number of the first layer of metal arranged between the middle lines of the first layer of metal a and the middle lines of the first layer of metal b according to the distance from the middle lines of the first layer of metal a to the middle lines of the first layer of metal b and the minimum width, wherein the number of the first layer of metal is an integer;
calculating to obtain the spacing of the winding grid points according to the distance from the middle line of the first layer metal a to the middle line of the first layer metal b and the number of the first layer metals;
setting a plurality of winding lattice lines by taking the length direction of the first layer of metal a or the first layer of metal b as a first direction, then taking the first direction as an extension direction and taking the first direction as the winding lattice line interval, wherein the length directions of the first layer of metal a and the first layer of metal b are the same, and the first layer of metal a, the first layer of metal b and a grid electrode of a transistor are all positioned on the winding lattice line;
arranging a first layer of metal c along the winding lattice point line to connect with a corresponding first layer of metal a or first layer of metal b on the same winding lattice point line so as to complete the layout of the first layer of metal in the standard cell;
arranging a first layer of metal e along the winding lattice line to realize the connection between the standard cells;
and arranging a first layer of metal f along the winding lattice line to realize the connection of other units except the standard unit.
The invention has the beneficial effects that: calculating to obtain the minimum width of a first layer of metal according to the width of the first layer of metal a at the source end of the transistor and the minimum distance between the first layer of metal a, or calculating to obtain the minimum width of the first layer of metal according to the width of the first layer of metal b at the drain end of the transistor and the minimum distance between the first layer of metal b, calculating the number of the first layer of metal arranged according to the minimum width between the middle branch line of the first layer of metal a and the middle branch line of the first layer of metal b according to the distance between the middle branch line of the first layer of metal a and the middle branch line of the first layer of metal b and the minimum width, wherein the number of the first layer of metal is an integer, calculating to obtain the routing grid point line spacing according to the distance between the middle branch line of the first layer of metal a and the middle branch line of the first layer of metal b and the number of the first layer of metal, and taking the length direction of the first layer of metal a at the source end, then, a plurality of parallel winding lattice lines are arranged by taking the first direction as an extension direction, a first layer of metal c is arranged along the winding lattice lines to connect the corresponding first layer of metal a or the corresponding first layer of metal b on the same winding lattice line, a first layer of metal e is arranged along the winding lattice lines to realize the connection between the standard units, a first layer of metal f is arranged along the winding lattice lines to realize the connection of other units outside the standard units, the number of wiring channels of the first layer of metal is increased, the wiring rate is improved, the active area and the grid contact holes can be arranged along the length direction of the first layer of metal c, the number of the active area and the grid contact holes is more than or equal to one, the wiring channels of the first layer of metal do not need to be additionally occupied, the number of the contact holes is increased, and the reliability of the layout is increased.
Preferably, the first layer metal layout method further includes disposing a first layer metal d along the winding grid line to connect the gates of the corresponding transistors on the same winding grid line. The beneficial effects are that: the contact holes of the grid and the first layer of metal are arranged in the first direction, the number of the contact holes is larger than or equal to one, and the wiring channel of the first layer of metal does not need to be occupied additionally, so that the number of the contact holes is increased, and the reliability of the standard unit is improved.
Further preferably, the widths of the first layer metal d and the first layer metal c are the same as the width of the first layer metal a.
Further preferably, the width of the first layer metal e is the same as the width of the first layer metal a.
Further preferably, the wire wrap grid line bisects the first layer metal e located thereon.
Further preferably, a first layer of metal d is arranged along the winding lattice point line to connect the gates of the corresponding transistors on the same winding lattice point line, and the first layer of metal e is connected with the first layer of metal d and arranged on the winding lattice point line where the first layer of metal d is located.
Further preferably, a first layer of metal d is disposed along the winding lattice line to connect the gates of the corresponding transistors on the same winding lattice line, and the first layer of metal e is disposed on the winding lattice line without the first layer of metal a, the first layer of metal c or the first layer of metal d. The beneficial effects are that: simplifying the design and simplifying the arrangement difficulty of the first layer of metal d.
Preferably, the first-layer metal layout method further includes disposing a power trace with an nth-layer metal and connecting the power trace with the corresponding first-layer metal c through a via, where n is a natural number greater than 1.
Preferably, the first-layer metal layout method further includes setting a ground trace with an nth-layer metal and connecting the ground trace with a corresponding first-layer metal c through a via, where n is a natural number greater than 1.
Further preferably, the length direction of the nth layer of metal is perpendicular to the first direction. The beneficial effects are that: the first layer metal c is convenient to be connected with the nth layer metal.
Preferably, the winding grid line bisects the first layer metal a and the first layer metal c located thereon.
The invention also provides an integrated circuit, which comprises at least two standard cells, wherein each standard cell comprises a first layer of metal a at a transistor source end, a first layer of metal b at a transistor drain end, a first layer of metal c, a first layer of metal e and a first layer of metal f, the length directions of the first layer of metal a and the first layer of metal b are the same, the length direction of the first layer of metal a or the first layer of metal b is taken as a first direction, the first direction is taken as an extension direction, and the distance is taken as a winding lattice point line distance to arrange a plurality of winding lattice points, the first layer of metal c, the first layer of metal e and the first layer of metal f are arranged along the same or different winding lattice points, the first layer of metal c is used for connecting the corresponding first layer of metal a or the first layer of metal b, and the first layer of metal e is used for connecting different standard cells, the first layer of metal f is used for connecting other units except the standard unit.
The integrated circuit has the effects that: the length direction of the first layer of metal a or the first layer of metal b is taken as a first direction, a plurality of parallel winding lattice lines are arranged by taking the first direction as an extension direction, the first layer of metal c is arranged along the winding lattice lines and is connected with the corresponding first layer of metal a or the first layer of metal b, the first layer of metal e is used for connecting different standard units, the first layer of metal f is used for connecting other units outside the standard units, the number of wiring channels of the first layer of metal is increased, the wiring rate is improved, the active area and the grid contact holes can be arranged in the length direction of the first layer of metal c, the number of the active area and the grid contact holes is more than or equal to one, the wiring channels of the first layer of metal do not need to be additionally occupied, the number of the contact holes is increased, and the reliability of the standard units is improved.
Preferably, the standard cell further comprises a first layer of metal d connected to the gate of the corresponding transistor and disposed along the wire grid line. The beneficial effects are that: the contact holes of the grid and the first layer of metal are arranged in the first direction, the number of the contact holes is larger than or equal to one, and the wiring channel of the first layer of metal does not need to be occupied additionally, so that the number of the contact holes is increased, and the reliability of the standard unit is improved.
Drawings
FIG. 1 is a flow chart of a first level metal layout method of the present invention;
FIG. 2 is a schematic diagram of a first integrated circuit according to some embodiments of the present invention;
FIG. 3 is a schematic diagram of a second integrated circuit according to some embodiments of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings of the present invention, and it is obvious that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention. Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and similar words are intended to mean that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items.
In view of the problems in the prior art, an embodiment of the present invention provides an integrated circuit, which includes at least two standard cells, where each standard cell includes a first layer of metal a at a transistor source end, a first layer of metal b at a transistor drain end, a first layer of metal c, a first layer of metal d, a first layer of metal e, and a first layer of metal f, where the first layer of metal a and the first layer of metal b have the same length direction, the length direction of the first layer of metal a or the first layer of metal b is a first direction, the first direction is an extension direction, and the first direction and the first layer of metal f are winding lattice line intervals, where the first layer of metal c, the first layer of metal d, the first layer of metal e, and the first layer of metal f are arranged along the same or different winding lattice line intervals, the first layer of metal c is used to connect the corresponding first layer of metal a or the first layer of metal b, the first layer of metal d is used for connecting the grid electrodes of corresponding transistors, the first layer of metal e is used for connecting different standard cells, and the first layer of metal f is used for connecting other cells except the standard cells.
The invention also provides a first layer metal layout method, which comprises the following steps with reference to fig. 1:
s1: calculating to obtain the minimum width of the first layer of metal according to the width of the first layer of metal a at the source end of the transistor and the minimum distance between the first layer of metal, or calculating to obtain the minimum width of the first layer of metal according to the width of the first layer of metal b at the drain end of the transistor and the minimum distance between the first layer of metal;
s2: calculating the number of the first layer of metal arranged between the middle lines of the first layer of metal a and the middle lines of the first layer of metal b according to the distance from the middle lines of the first layer of metal a to the middle lines of the first layer of metal b and the minimum width, wherein the number of the first layer of metal is an integer;
s3: calculating to obtain the spacing of the winding grid points according to the distance from the middle line of the first layer metal a to the middle line of the first layer metal b and the number of the first layer metals;
s4: setting a plurality of winding lattice lines by taking the length direction of the first layer of metal a or the first layer of metal b as a first direction, then taking the first direction as an extension direction and taking the first direction as the winding lattice line interval, wherein the length directions of the first layer of metal a and the first layer of metal b are the same, and the first layer of metal a, the first layer of metal b and a grid electrode of a transistor are all positioned on the winding lattice line;
s5: arranging a first layer of metal c along the winding lattice point line to connect with a corresponding first layer of metal a or first layer of metal b on the same winding lattice point line so as to complete the layout of the first layer of metal in the standard cell;
s6: arranging a first layer of metal e along the winding lattice line to realize the connection between the standard cells;
s7: and arranging a first layer of metal f along the winding lattice line to realize the connection of other units except the standard unit.
In some embodiments, in the step S1, the minimum distance between the first layer metals is the minimum distance between the first layer metal a, the first layer metal b, and the gate first layer metal.
In some embodiments, the first metal layout method further includes disposing a first metal layer d along the routing grid line to connect gates of corresponding transistors on the same routing grid line.
In some embodiments, the first-layer metal layout method further includes disposing a power trace and a ground trace in an nth-layer metal, and connecting the power trace and the ground trace to the corresponding first-layer metal c and/or first-layer metal d through a via, where a length direction of the nth-layer metal is perpendicular to the first direction, and n is a natural number greater than 1.
In some embodiments, the width of the first layer metal d and the first layer metal c are the same as the width of the first layer metal a.
In some embodiments, the wire grid dot lines bisect the first layer metal a, the first layer metal c, and the first layer metal d located thereon.
Referring to fig. 2, the first integrated circuit includes a first standard cell 10, the first standard cell 10 including a source terminal 11, a drain terminal 12, and a gate 13.
Referring to fig. 2, the source terminal 11 includes a first source terminal 111, a second source terminal 112, a third source terminal 113, a fourth source terminal 114, and a fifth source terminal 115, where the first layer metal a of the first source terminal 11111111 surrounds the outside of the first source terminal 111, and the first layer metal a of the second source terminal 11221121 surrounds the outside of the second source terminal 112, and the first layer metal a of the third source terminal 11331131 surrounds the outside of the third source terminal 113, and the first layer metal a of the fourth source terminal 11441141 surrounds the outer side of the fourth source terminal 114, and the first layer metal a of the fifth source terminal 11551151 surrounds the outside of said fifth source terminal 115.
Referring to fig. 2, the drain terminal 12 includes a first drain terminal 121, a second drain terminal 122, a third drain terminal 123, a fourth drain terminal 124 and a fifth drain terminal 125, and the first layer metal b of the first drain terminal 12111211 surrounds the first drain terminal 121 on the outside thereof,the first layer metal b of the second drain terminal 12221221 surrounding the outside of the second drain terminal 122, and the first layer metal b of the third drain terminal 12331231 is wound outside the third drain terminal 123, and the first layer metal b of the fourth drain terminal 12441241 surrounding the outside of the fourth drain 124, the first layer metal b of the fifth drain 12551251 surround the outside of the fifth drain 125.
Referring to fig. 2, the first layer metal a11111. The first layer of metal a21121. The first layer of metal a31131. The first layer of metal a41141. The first layer of metal a51151. The first layer of metal b 11211. The first layer of metal b21221. The first layer of metal b 31231. The first layer of metal b 41241 and the first layer metal b 51251 are identical and the length direction is the first direction, i.e. the y direction indicated in the figure.
Referring to fig. 2, a first winding lattice line 14, a second winding lattice line 15, a third winding lattice line 16, a fourth winding lattice line 17, a fifth winding lattice line 18 and a sixth winding lattice line 19 are sequentially arranged from left to right at equal intervals with the first direction as an extending direction, and a distance between the first winding lattice line 14 and the second winding lattice line 15 is greater than that of the first layer metal a11111 width.
Referring to fig. 2, the first layer metal a11111. The first layer of metal a21121. The first layer of metal a31131. The first layer of metal a41141 and the first layer metal a51151 is located on the second wire grid line 15, and the second wire grid line 15 bisects the first layer metal a11111. The first layer of metal a21121. The first layer of metal a31131. The first layer of metal a41141 and the first layer metal a51151. A first layer of metal c is arranged along said second winding lattice line 1411161 for connecting the first layer of metal a11111. The first layer of metal a21121 andthe first layer of metal a31131, carrying out filtration; a first layer of metal c is arranged along said second winding lattice line 1421171 to connect said first layer metal a41141 and the first layer metal a51151. Preferably, the first layer of metal c 11161 and said first layer of metal c 21171 and said first layer metal a11111 are the same width.
Referring to fig. 2, the first layer of metal b 11211. The first layer of metal b21221. The first layer of metal b 31231. The first layer of metal b 41241 and the first layer metal b512151 are located on the fifth winding lattice line 18, and the fifth winding lattice line 18 bisects the first layer metal b 11211. The first layer of metal b21221. The first layer of metal b 31231. The first layer of metal b 41241 and the first layer metal b 51251. A first layer of metal c is arranged along said fifth winding lattice line 1831261 for connecting said first layer of metal b 11211. The first layer of metal b21221. The first layer of metal b 31231. The first layer of metal b 41241 and the first layer metal b 51251. Preferably, the first layer of metal c 31261 and said first layer of metal b 11211 is of the same width.
Referring to fig. 2, the gate 13 includes a first gate 131 and a second gate 132, and the first gate 131 and the second gate 132 are located on the third winding dot line 16. Arranging said first layer of metal d along said third winding lattice line 161133 to connect the first gate 131 and the second gate 132, and the first layer of metal d 1133 and the first layer metal a11111 are the same width, the third winding grid point line bisects the first layer metal d 1133。
Referring to fig. 2, the standard cell further includes an nth layer metal f 120 and n-th layer of metal f 221, the n-th layer of metal f 120 and the n-th layer metal f 221 longitudinal direction of the shaftThe nth layer of metal f is perpendicular to the first direction, i.e. the x direction marked in the figure120 and the n-th layer metal f 221 are provided with a power rail (not shown) and a ground rail (not shown), and the first layer of metal c 11161 passing through the first via 201 and the n-th layer of metal f 120 connection, said first layer of metal c 21171 through a second via 211 with said nth layer of metal f 221 are connected, n is a natural number greater than 1.
In some embodiments, in the first layer metal layout method, the number of the standard cells is a natural number greater than 1, and the first layer metal layout method further includes disposing a first layer metal e along the dot-around-dot line to achieve connection between the standard cells.
In some embodiments, the width of the first layer metal e is the same as the width of the first layer metal a, and the wire grid lines bisect the first layer metal e located thereon.
In some embodiments, the first layer metal e is connected to the first layer metal d and disposed on a winding grid point line where the first layer metal d is located.
In still other embodiments, the first layer metal e is disposed on a routing grid without the first layer metal a, the first layer metal c, or the first layer metal d.
Referring to fig. 3, the second integrated circuit includes a first standard cell 10 and a second standard cell 30, the first layer metal of the first standard cell 10 is shown in fig. 2, the first layer metal of the second standard cell 30 is disposed in the same manner as the first standard cell 10, the second standard cell 30 includes a third gate 31 and a fourth gate 32, the third gate 31 and the fourth gate 32 are disposed on the fourth winding grid line 17, and the first layer metal d is disposed along the fourth winding grid line 172134 to connect the third gate 31 and the fourth gate 32, and the first layer of metal d 2134 and the first layer metal a11111 are the same width, the fourth winding lattice line 17 bisects the first layer metal d 2134 along the fourth winding lattice line 17Placing a first layer of metal e 1171 to enable connection of the first standard cell 10 and the second standard cell 30, the first layer of metal e 1171 of 134 a width and the first layer of metal a11111 are of the same width, the fourth winding lattice line 17 bisecting the first layer of metal e lying thereon1171, and the first layer of metal e 1171 and the first layer of metal d 2134 are connected.
In some embodiments, referring to fig. 3, a first layer of metal e is disposed along the first winding grid 142141 for connecting the first standard cell 10 and the second standard cell 30, and a first layer of metal e is disposed along the sixth winding lattice line 193191 to connect other cells except the first standard cell 10 and the second standard cell 30, and the first layer metal e 3191 are not in communication with the first standard cell 10 and the second standard cell 30.
Although the embodiments of the present invention have been described in detail hereinabove, it is apparent to those skilled in the art that various modifications and variations can be made to these embodiments. However, it is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention as described herein is capable of other embodiments and of being practiced or of being carried out in various ways.
Claims (13)
1. A first level metal layout method, comprising the steps of:
calculating to obtain the minimum width of the first layer of metal according to the width of the first layer of metal a at the source end of the transistor and the minimum distance between the first layer of metal, or calculating to obtain the minimum width of the first layer of metal according to the width of the first layer of metal b at the drain end of the transistor and the minimum distance between the first layer of metal;
calculating the number of the first layer of metal arranged between the middle lines of the first layer of metal a and the middle lines of the first layer of metal b according to the distance from the middle lines of the first layer of metal a to the middle lines of the first layer of metal b and the minimum width, wherein the number of the first layer of metal is an integer;
calculating to obtain the spacing of the winding grid points according to the distance from the middle line of the first layer metal a to the middle line of the first layer metal b and the number of the first layer metals;
setting a plurality of winding lattice lines by taking the length direction of the first layer of metal a or the first layer of metal b as a first direction, then taking the first direction as an extension direction and taking the first direction as the winding lattice line interval, wherein the length directions of the first layer of metal a and the first layer of metal b are the same, and the first layer of metal a, the first layer of metal b and a grid electrode of a transistor are all positioned on the winding lattice line;
arranging a first layer of metal c along the winding lattice point line to connect with a corresponding first layer of metal a or first layer of metal b on the same winding lattice point line so as to complete the layout of the first layer of metal in the standard cell;
arranging a first layer of metal e along the winding lattice line to realize the connection between the standard cells;
and arranging a first layer of metal f along the winding lattice line to realize the connection of other units except the standard unit.
2. The method as claimed in claim 1, further comprising disposing a first layer of metal d along the routing grid line to connect gates of corresponding transistors on the same routing grid line.
3. The method of claim 2, wherein the width of each of the first layer metal d and the first layer metal c is the same as the width of the first layer metal a.
4. The method of claim 1, wherein the width of the first layer metal e is the same as the width of the first layer metal a.
5. The first level metal layout method of claim 1, wherein the wire wrap grid line bisects the first level metal e located thereon.
6. The method as claimed in claim 1, wherein a first layer of metal d is disposed along the routing grid line to connect the gates of the corresponding transistors on the same routing grid line, and the first layer of metal e is connected to the first layer of metal d and disposed on the routing grid line where the first layer of metal d is located.
7. The method as claimed in claim 1, wherein a first layer of metal d is disposed along the routing grid line to connect gates of corresponding transistors on the same routing grid line, and the first layer of metal e is disposed on the routing grid line without the first layer of metal a, the first layer of metal c or the first layer of metal d.
8. The method of claim 1, further comprising providing power traces in an nth metal layer and connecting the power traces to corresponding first metal layer c through vias, wherein n is a natural number greater than 1.
9. The method of claim 1, further comprising providing a ground trace with an nth metal layer and connecting to a corresponding first metal layer c through a via, n being a natural number greater than 1.
10. The first layer metal layout method of claim 8 or 9, wherein a length direction of the nth layer metal is perpendicular to the first direction.
11. The first layer metal layout method of claim 1, wherein the wire wrap grid line bisects the first layer metal a and the first layer metal c located thereon.
12. An integrated circuit, comprising at least two standard cells, wherein each standard cell comprises a first layer of metal a at a transistor source end, a first layer of metal b at a transistor drain end, a first layer of metal c, a first layer of metal e and a first layer of metal f, the length directions of the first layer of metal a and the first layer of metal b are the same, the length direction of the first layer of metal a or the first layer of metal b is a first direction, the first direction is an extension direction, and the first direction is a winding lattice point line interval to form a plurality of winding lattice point lines, the first layer of metal c, the first layer of metal e and the first layer of metal f are arranged along the same or different winding lattice point lines, the first layer of metal c is used for connecting the corresponding first layer of metal a or the first layer of metal b, and the first layer of metal e is used for connecting different standard cells, the first layer of metal f is used for connecting other units except the standard unit.
13. The integrated circuit of claim 12, wherein the standard cell further comprises a first layer of metal d connecting gates of respective transistors and disposed along the wire grid line.
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| US20120241986A1 (en) * | 2011-03-23 | 2012-09-27 | Synopsys, Inc. | Pin Routing in Standard Cells |
| CN103955582A (en) * | 2014-05-05 | 2014-07-30 | 格科微电子（上海）有限公司 | Cell library-based integrated circuit design method and structure of cell library-based integrated circuit |
| CN111488722A (en) * | 2020-04-16 | 2020-08-04 | 清华大学 | Design method for full-customized low-leakage digital circuit standard unit |
| US10796061B1 (en) * | 2019-08-29 | 2020-10-06 | Advanced Micro Devices, Inc. | Standard cell and power grid architectures with EUV lithography |
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| US20120241986A1 (en) * | 2011-03-23 | 2012-09-27 | Synopsys, Inc. | Pin Routing in Standard Cells |
| CN103955582A (en) * | 2014-05-05 | 2014-07-30 | 格科微电子（上海）有限公司 | Cell library-based integrated circuit design method and structure of cell library-based integrated circuit |
| US10796061B1 (en) * | 2019-08-29 | 2020-10-06 | Advanced Micro Devices, Inc. | Standard cell and power grid architectures with EUV lithography |
| CN111488722A (en) * | 2020-04-16 | 2020-08-04 | 清华大学 | Design method for full-customized low-leakage digital circuit standard unit |
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