CN112349683B - A four-layer wiring LCP package substrate, manufacturing method and multi-chip system-in-package structure - Google Patents

Abstract

The invention discloses a four-layer wiring LCP packaging substrate, a manufacturing method and a multi-chip system-level packaging structure, wherein the LCP packaging substrate comprises 4 graphical metal circuit layers distributed from the surface to the bottom surface, namely a first graphical metal circuit layer, a second graphical metal circuit layer, a third graphical metal circuit layer and a fourth graphical metal circuit layer in sequence; at least one edge of the outermost periphery of the first layer of patterned metal circuit layer is distributed with pads or patterns for external secondary cascade I/O welding; the insulating medium layer is positioned between the adjacent graphical metal circuit layers; the plurality of blind grooves are positioned in the insulating medium layer and have openings facing the first patterned metal circuit layer; and the plurality of blind holes penetrate through and are connected with the adjacent patterned metal circuit layers. The LCP packaging substrate with the airtight packaging structure can meet the system-level packaging requirements of multiple chips, high airtight requirements, high electromagnetic shielding and high reliable interconnection.

Description

A four-layer wiring LCP package substrate, manufacturing method and multi-chip system-in-package structure

technical field

The invention relates to the technical field of integrated circuits and chip packaging, in particular to a four-layer wiring LCP packaging substrate, a manufacturing method and a multi-chip system-level packaging structure, which are used for high-reliability system-level applications for radio frequency, microwave, millimeter wave and other high-frequency applications package.

Background technique

With the advancement of semiconductor and integrated circuit technology, the requirements for system integration have been further improved. The current electronic circuit design and manufacturing are developing towards smaller size and higher integration density. A considerable amount of work is carried out in the field of multi-chip packaging. In advanced packaging forms, through SIP technology, multiple radio frequency (RF) chips, digital integrated circuit (IC) chips, micro-miniature chip components, etc. are assembled on the packaging substrate, and then integrated into a package body. This multi-chip packaging form shortens the pin distance between chips, greatly improves the packaging density, and can meet the needs of system-level packaging to a certain extent.

According to the different packaging substrate materials, packaging methods can usually be divided into two types: one is a multi-layer ceramic packaging with a cavity structure, and the other is a plastic packaging using a multi-layer PCB substrate as the chip substrate material.

Ceramic packaging substrates have the advantages of high integration density, high reliability, high air tightness, high thermal conductivity, and excellent corrosion resistance. However, due to the thermal mismatch between ceramic materials and PCB circuit board materials, large-scale packaging cannot be performed, and ceramic packaging has the problem of extremely high manufacturing costs.

The plastic packaging substrate has the characteristics of low cost, relatively simple process and high interconnection density, and can realize secondary high-density interconnection with the PCB motherboard through BGA and other forms. Its biggest disadvantage is that ordinary PCB materials have high moisture absorption rate and poor water vapor blocking performance, so they cannot be airtightly packaged; at the same time, due to the limited dielectric properties (dielectric constant, dielectric loss) of general resin materials, they cannot be applied to radio frequency/microwave transmission. . These deficiencies limit the application of plastic packaging in high-reliability, high-performance chip packaging, and its main application field is consumer electronics.

Liquid crystal polymer (LCP) material, due to its excellent dielectric transmission properties, extremely low moisture absorption rate, water permeability and oxygen permeability, in-plane thermal expansion coefficient matching copper, high heat resistance and chemical resistance, etc. The outstanding advantages meet the strict requirements of RF/microwave chips for packaging substrate materials. It is a new generation of substrate materials with great potential and broad application prospects in the field of high reliability and high performance chip packaging.

Liquid crystal polymer (LCP) material, due to its excellent dielectric transmission properties, extremely low moisture absorption rate, water permeability and oxygen permeability, in-plane thermal expansion coefficient matching copper, high heat resistance and chemical resistance, etc. The outstanding advantages meet the strict requirements of RF/microwave chips for packaging substrate materials. It is a new generation of substrate materials with great potential and broad application prospects in the field of high reliability and high performance chip packaging.

Chinese patents CN106486427A and CN206259334U disclose a packaging shell based on an LCP substrate and a preparation method. The LCP substrate is used as the substrate layer for chip mounting, supplemented by technologies such as chip assembly, metal enclosure, cover plate welding, etc., to provide a chip hermetic seal installed solution. In this packaging form, the specific structure and manufacturing method of the packaging substrate are not given; the packaging form lacks external interconnection interfaces, and cannot realize the secondary cascade of the packaging; Provides a good electromagnetic shielding foundation, and the problem of circuit crosstalk is difficult to avoid.

Chinese patent CN102593077A discloses a liquid crystal polymer packaging structure, which adopts a high melting point LCP composite cover plate and a low melting point LCP tube shell to hot-melt together to form a structure for chip hermetic packaging. The package structure is too simple, and does not involve specific structural features and implementation methods of the substrate.

Chinese patent CN104282632B discloses a packaging shell based on an LCP substrate and a preparation method. The LCP multi-layer substrate is used as a carrier board to carry out hermetic packaging of chips. It divides the LCP package substrate structure according to surface sealing layer, chip mounting layer, soldering layer, interconnection layer, etc., defines the structural features of each composition, and provides an implementation method. In this substrate structure, the holes of the circuit interconnection layer are located around the chip sealing area. Due to the existence of the through holes, the periphery of the chip is not airtight. This substrate structure reduces the effective airtight packaging area of the substrate. The circuit interconnection design of the layer has certain limitations; its surface layer is defined as a sealing area, which is designed separately from the inner bonding layer, and is not electrically connected to each other or only has a ground connection. This structure is only suitable for simple packaging of a single chip, not applicable Complex system-level applications with multi-chip packages and multiple electromagnetic shielding requirements. Moreover, the disclosed realization method adopts the method of multiple lamination and hot pressing. The LCP adhesive film material is thermoplastic in nature, and theoretically it is impossible to perform multiple lamination operations, so it is still very difficult and unrealistic to realize the process of this structure.

Chinese patent CN107324273B discloses a packaging method for MEMS devices based on LCP multi-layer stacking technology, using multi-layer LCP stacking and lamination to prepare caps for MEMS devices, and applying LCP materials directly to single-chip plastic packaging. In this invention, the LCP material only plays the role of the package cap, the application field does not involve the package substrate, and the wiring design cannot be performed.

Chinese patent CN102683220B discloses a method for fabricating a multi-layer organic liquid crystal polymer substrate structure, which can simultaneously embed active and passive devices in the multi-layer liquid crystal polymer substrate to realize hermetic sealing of the chip. It uses flip-chip welding technology to connect active devices with bumps to the LCP substrate, then open the LCP adhesive film, laminate, and finally interconnect through metallized through holes to finally form a package structure. This kind of package structure adopts the manufacturing route of the substrate embedded in the chip, which is mainly for single-chip packaging, and is not suitable for multi-chip packaging applications with high electromagnetic shielding requirements; the interconnection holes of the substrate are fabricated by one-time drilling and metallization, and the interconnection function of the substrate is simple. , unable to meet the complex interconnect requirements required for multi-chip packaging.

Chinese patent CN106252339B discloses a high-density radio frequency multi-chip packaging structure, using a multi-layer substrate and a casing as a carrier, stacking multiple chips and devices in a vertical direction for three-dimensional high-density hybrid integration. This kind of multi-chip package is essentially a hybrid integration in the form of a multi-chip package, with limited electromagnetic shielding performance, and involves multiple temperature gradients and selection of solders, making the process difficult to implement.

Chinese patent CN103165479B discloses a method for manufacturing a multi-chip system-in-package structure. By vertically stacking multi-chips, multiple chips are integrated on an adapter board to form a system packaging structure. This structure is suitable for high-density integration of IC chips, but it is no longer applicable to the electromagnetic shielding requirements of multi-radio frequency chips.

Chinese patent CN103930989B discloses a radio-frequency package-on-package circuit, which forms a two-level package of a radio-frequency package-on-package (PoP) circuit by vertically stacking two radio frequency packages. This structural package does not deal with the electromagnetic shielding problem of the chip in a single package in detail, and the function of the substrate is simple, and the structure of the substrate is not described in detail.

U.S. Patent US2019/0080817Al discloses a method for manufacturing an LCP resin multilayer substrate. Using a special LCP paste as an adhesive layer and a thickness adjustment layer for an LCP multilayer substrate, it can improve the flatness and avoid the lack of glue. warping and other manufacturing issues. The interconnection holes of the substrate structure are filled with conductive paste. Due to the adhesive component of the conductive paste, there will be volatilization under high temperature, which may cause the substrate to form layers, bubbling or even the risk of explosion. The substrate produced in this way cannot withstand the High temperature applications. And the adhesion between LCP paste and LCP layer, LCP paste and conductive paste is theoretically much worse than that of conventional LCP adhesive film lamination method. The multilayer LCP substrate produced in this way is not suitable for RF chip packaging applications with high interconnection hole reliability.

However, there is no technical solution for realizing the packaging substrate and the system-in-package structure that meets the system-in-package requirements of multi-chip, high air tightness, high electromagnetic shielding, and high-reliable interconnection by using LCP in the existing disclosed technologies.

SUMMARY OF THE INVENTION

The technical problem to be solved by the present invention is to provide a four-layer wiring LCP packaging substrate, a manufacturing method and a multi-chip system-level packaging structure based on the substrate to meet the requirements of multi-chip, high air tightness and high System-in-package requirements for electromagnetic shielding and high-reliability interconnection.

A four-layer wiring LCP packaging substrate provided by the present invention includes:

The 4-layer patterned metal circuit layer distributed from the surface to the bottom surface is the first layer of patterned metal circuit layer, the second layer of patterned metal circuit layer, the third layer of patterned metal circuit layer and the fourth layer of patterned metal circuit layer. layer; at least one edge of the outermost periphery of the first layer of patterned metal circuit layer is distributed with the external secondary cascade I/O soldering pads or patterns of the LCP package substrate;

3 insulating dielectric layers between adjacent patterned metal circuit layers;

a plurality of blind trenches located in the insulating dielectric layer and opening toward the first patterned metal circuit layer;

A plurality of blind vias running through and connecting adjacent patterned metal circuit layers, wherein several blind vias are distributed on the external secondary cascade I/O soldering pads or patterns.

Further, the first layer of patterned metal circuit layer includes a surrounding metal layer on the outermost periphery of the external secondary cascading I/O soldering pad or the inner side of the pattern, and multiple groups of chip I/O on the inner side of the surrounding metal layer. O welding and signal transmission circuit layer, the shape of each group of chip I/O welding and signal transmission circuit layer is a rectangular or special-shaped island, and each group of chip I/O welding and signal transmission circuit layer is connected to the surrounding metal through an electrical insulating area The electrical property of the surrounding metal layer is a ground layer, and the process property is an airtight soldering layer; the upper surface of the first layer of patterned metal circuit layer is sequentially provided with a coating layer and an upper surface solder resist layer; the The coating layer covers the pads or patterns for external secondary cascade I/O welding, the surrounding metal layer, and the I/O welding and signal transmission circuit layers of each group of chips; the upper surface solder resist layer includes a first surrounding resistor. a solder layer and a plurality of second surrounding solder mask layers, wherein each second surrounding solder mask layer surrounds each electrical insulating region correspondingly, and the first surrounding solder mask layer surrounds all the second surrounding solder mask layers;

Each group of chip I/O soldering and signal transmission line layers includes chip I/O pads, signal transmission lines, and one or more blind slots; The transmission is completed through the chip I/O pads and signal transmission lines in the circuit layer for chip I/O welding and signal transmission of the group, or through the blind holes of each layer and the corresponding parts in the lower patterned metal circuit layer; two groups of and the above chip I/O soldering and signal transmission layers, as well as the signal transmission between multiple groups of chip I/O soldering and signal transmission layers and the pads or patterns for external secondary cascade I/O soldering. The blind hole and the corresponding part in the lower patterned metal circuit layer are completed together.

Further, in the four-layer patterned metal circuit layer, an insulating medium layer located between the second layer of patterned metal circuit layer and the third layer of patterned metal circuit layer is composed of an LCP substrate; located in the first layer of patterned metal circuit layer; The insulating medium layers between the circuit layer and the second patterned metal circuit layer and between the third patterned metal circuit layer and the fourth patterned metal circuit layer are composed of an LCP substrate and an LCP adhesive film.

Further, the melting point of the LCP adhesive film is 10-60° C. lower than the melting point of the LCP substrate.

Further, the bottom of the blind groove is a large-area metal ground layer in the second layer of patterned metal circuit layers, the third layer of patterned metal circuit layers or the fourth layer of patterned metal circuit layers, and has a coating layer; The blind grooves are surrounded by chip I/O pads or patterns around the opening of the first patterned metal circuit layer; the number, size and depth of the blind grooves are determined according to the number, size and height of the mounted chips.

Further, all blind vias can be stacked vertically or staggered to meet the interconnection requirements of any layer in the 4-layer patterned metal circuit layer; the diameter of each blind via is the same, and the blind via depth-to-diameter ratio ≤ 1. Fill the blind hole with solid electroplated copper.

The present invention also provides a manufacturing method of a four-layer wiring LCP packaging substrate, the manufacturing method is used to manufacture the above-mentioned LCP packaging substrate, and includes the following steps:

S1, laser drilling blind holes on the double-sided copper-clad LCP substrate to connect the second layer of patterned metal circuit layer and the third layer of patterned metal circuit layer, and the blind hole depth-diameter ratio is less than or equal to 1;

S2, blind hole metallization to form blind holes filled with solid electroplated copper;

S3, fabricating a second patterned metal circuit layer and a third patterned metal circuit layer on the upper surface and the lower surface of the double-sided copper-clad LCP substrate;

S4, take the first single-sided copper-clad LCP substrate, the second single-sided copper-clad LCP substrate, the first LCP adhesive film, and the second LCP adhesive film, and then follow the first single-sided copper-clad LCP substrate, The sequence of the first LCP adhesive film, the double-sided copper-clad LCP substrate processed by S3, the second LCP adhesive film, and the second single-sided copper-clad LCP substrate are aligned and laminated to form an LCP multilayer substrate; wherein , the copper-clad surface of the first single-sided copper-clad LCP substrate faces up, and the copper-clad surface of the second single-sided copper-clad LCP substrate faces down; the melting points of the first LCP adhesive film and the second LCP adhesive film are higher than the The melting point of one single-sided copper-clad LCP substrate and the second single-sided copper-clad LCP substrate is low;

S5, laser drilling blind holes on the first single-sided copper-clad LCP substrate and the second single-sided copper-clad LCP substrate of the LCP multilayer substrate, which are respectively used to connect the first layer of patterned metal circuit layer and the second layer of patterned metal The circuit layer, as well as the third layer of patterned metal circuit layer and the fourth layer of patterned metal circuit layer, the blind hole aspect ratio is less than or equal to 1;

S6, blind hole metallization to form blind holes filled with solid electroplated copper;

S7, fabricating a first layer of patterned metal circuit layers on the upper surface of the first single-sided copper-clad LCP substrate, and fabricating a fourth layer of patterned metal circuit layers on the lower surface of the second single-sided copper-clad LCP substrate; and removing the first layer of patterned metal circuit layers Copper in the blind groove slotted area in the layer patterned metal circuit layer;

S8, use laser processing to slot the blind slot slotted area to form a blind slot for mounting chips, and decontaminate the bottom and side walls of the blind slot;

S9, the coating layer is fabricated on the first layer of patterned metal circuit layer, the fourth layer of patterned metal circuit layer and the bottom of the blind groove, and the upper surface solder resist layer is formed on the corresponding part of the coating layer to obtain an LCP package substrate;

S10 , if the LCP package substrate is manufactured in a spliced form through steps S1 to S9 , the LCP package substrate manufactured in the spliced form is milled to form a single LCP package substrate.

Further, the aspect ratio of the blind hole is less than or equal to 1.

Further, the melting points of the first LCP adhesive film and the second LCP adhesive film are 10-60° C. lower than the melting points of the first single-sided copper-clad LCP substrate and the second single-sided copper-clad LCP substrate.

The present invention also provides a multi-chip system-level packaging structure, comprising: the above-mentioned LCP packaging substrate, and a chip, a metal enclosure and a metal cover;

The multi-chip system-level packaging structure is fixed on the PCB motherboard by means of conductive adhesive bonding or welding, and the external secondary cascade I/O soldering pads or patterns on the LCP packaging substrate are used as the multi-chip. Chip system-in-package structure to external secondary cascade I/O interface;

The metal enclosure is distributed with metal ribs; the metal enclosure and the metal ribs are welded on the upper surface of the LCP package substrate, and the external secondary cascade I/O welding pads or patterns are placed on the metal enclosure. In addition, the metal cover plate is welded on the metal enclosure frame and the metal spacer ribs, so that between the LCP package substrate and the metal cover plate, a multi-layer structure with airtight packaging performance and electromagnetic shielding performance is formed through the metal enclosure frame and the metal spacer ribs. Each cavity structure contains one or more blind slots; each blind slot is used to install a chip, when the installed chip does not require electromagnetic shielding, it is installed in the same cavity structure, when the installation When the chip has electromagnetic shielding requirements, it is installed in different cavity structures; the chip is bonded in the blind groove by conductive glue, and is bonded with the first layer of patterned metal circuit layer by gold wire bonding. The chip I/O soldering and signal transmission use the circuit layer to achieve electrical interconnection.

To sum up, due to the adoption of the above-mentioned technical solutions, the beneficial effects of the present invention are:

1. The packaging substrate of the present invention is manufactured based on an all-LCP material system, and utilizes the excellent high-frequency transmission characteristics, extremely low moisture absorption and water permeability and oxygen permeability of liquid crystal polymer (LCP) materials, and realizes a LCP package substrate for hermetically packaged chips.

2. The package substrate can realize any layer interconnection wiring of 4-layer pattern circuit, and contains multiple blind slots for chip mounting. With the electromagnetic compatibility and process compatibility design of the surface layer circuit of the substrate, it is a kind of multi-chip, high electromagnetic compatibility design. Package substrate for shielded, highly reliable system-in-package requirements.

3. The multi-chip system-level packaging structure realized by the LCP packaging substrate of the present invention is fixed on the PCB motherboard by means of conductive adhesive bonding or welding, and is welded with the external secondary cascade I/O located at the outermost periphery of the LCP packaging substrate. Using pads or graphics as the external secondary cascade I/O interface of the multi-chip system-in-package structure, it has good compatibility with the PCB motherboard, and the packaging is simple to use, with high assembly efficiency, and can be large-scale and highly integrated. density system-in-package.

Description of drawings

In order to illustrate the technical solutions of the embodiments of the present invention more clearly, the following briefly introduces the accompanying drawings used in the embodiments. It should be understood that the following drawings only show some embodiments of the present invention, and therefore do not It should be regarded as a limitation of the scope, and for those of ordinary skill in the art, other related drawings can also be obtained according to these drawings without any creative effort.

1 is a schematic structural diagram of an LCP package substrate according to Embodiment 1 of the present invention;

Among them: 1-LCP packaging substrate; 11-patterned metal circuit layer; 111-first layer of patterned metal circuit layer; 112-second layer of patterned metal circuit layer; 113-third layer of patterned metal circuit layer; 114 -The fourth layer of patterned metal circuit layer; 12-Blind slot; 13-Coating layer; 14-Blind hole; 141-Type 1 blind hole; 142-Type 2 blind hole; 15-Insulation dielectric layer; 151-LCP substrate; 152-LCP adhesive film; 16-Signal transmission path in the substrate; 17-Solder resist layer on the upper surface; 1111- External secondary cascade I/O soldering pad or pattern .

2 is a schematic diagram of the structure of the first layer of patterned metal circuit layers according to Embodiment 1 of the present invention;

Among them, 21, 22, 23 - chip I/O welding and signal transmission circuit layer; 211, 221, 231 - chip mounting blind slot position; 212, 222, 232 - chip I/O pad and signal transmission line; 213 , 223, 233—electrically insulating area; 171, 172, 173—the second surrounding solder resist layer; 24—the surrounding metal layer; 174—the first surrounding solder resist layer; 16—the signal transmission path in the substrate.

FIG. 3 is a flow chart of a method for manufacturing an LCP package substrate according to Embodiment 2 of the present invention.

4a to 4i are schematic structural diagrams of steps in the process of manufacturing a LCP package substrate according to Embodiment 2 of the present invention:

Figure 4a is a schematic structural diagram of a double-sided copper-clad LCP substrate after laser drilling blind holes;

Figure 4b is a schematic structural diagram of blind via metallization to obtain the second type of blind via;

4c is a schematic structural diagram of the second layer and the third layer of patterned metal circuit layers after manufacturing;

4d is a schematic structural diagram of an alignment stack for manufacturing an LCP multilayer substrate;

FIG. 4e is a schematic diagram of the laminated structure of the LCP multilayer substrate;

FIG. 4f is a schematic structural diagram of a laser-drilled blind hole in an LCP multilayer substrate;

FIG. 4g is a schematic structural diagram of blind via metallization to obtain the first type blind via and the third blind via;

FIG. 4h is a schematic view of the structure after the first and fourth layers of patterned metal circuit layers are fabricated; wherein: 121-blind slot slotting area.

Fig. 4i is the structural schematic diagram after making blind groove;

FIG. 4j is a schematic structural diagram of the LCP package substrate obtained after the coating layer and the solder resist layer are fabricated.

5 is a schematic diagram of a multi-chip system-in-package structure based on an LCP packaging substrate according to Embodiment 3 of the present invention;

Among them: 1-LCP packaging substrate; 2-Multi-chip system-level packaging structure; 3-Chip; 4-Gold wire; 5-Metal enclosure; 51-Metal ribs; 6-Metal cover plate; 7-Cavity structure; 12-blind slot; 16-signal transmission path in the substrate.

Detailed ways

The features and performances of the present invention will be further described in detail below in conjunction with the embodiments.

Example 1

As shown in FIG. 1 , a four-layer wiring LCP packaging substrate of this embodiment includes:

The 4-layer patterned metal circuit layer distributed from the surface to the bottom surface is the first layer of patterned metal circuit layer, the second layer of patterned metal circuit layer, the third layer of patterned metal circuit layer and the fourth layer of patterned metal circuit layer. layer; at least one edge of the outermost periphery of the first layer of patterned metal circuit layer is distributed with the external secondary cascade I/O soldering pads or patterns of the LCP package substrate;

3 insulating dielectric layers between adjacent patterned metal circuit layers;

a plurality of blind trenches located in the insulating dielectric layer and opening toward the first patterned metal circuit layer;

A plurality of blind vias running through and connecting adjacent patterned metal circuit layers, wherein several blind vias are distributed on the external secondary cascade I/O soldering pads or patterns.

1. 4-layer patterned metal circuit layer:

As shown in FIG. 2 , the first layer of patterned metal circuit layer 111 includes a surrounding metal layer 24 on the outermost periphery of the external secondary cascading I/O soldering pads or the inner side of the pattern 1111 , and the surrounding metal layer 24 Multiple groups of chip I/O soldering and signal transmission line layers 21, 22, 23 on the inner side, each group of chip I/O soldering and signal transmission line layers 21, 22, 23 are connected to the surrounding metal through an electrical insulating area 213, 223, 233. The electrical property of the surrounding metal layer 24 is a ground layer, and the process property is an airtight soldering layer; the upper surface of the first layer of patterned metal circuit layer 111 is sequentially provided with a coating layer 13 and an upper surface solder resist Layer 17; the coating layer 13 covers the external secondary cascade I/O soldering pads or patterns 1111, the surrounding metal layer 24 and the I/O soldering and signal transmission circuit layers 21, 22, 23 of each group of chips ; The upper surface solder mask layer 17 includes a first surrounding solder mask layer 174 and a plurality of second surrounding solder mask layers 171, 172, 173, wherein each second surrounding solder mask layer 171, 172, 173 corresponds to surrounding each electrically insulating regions 213, 223, 233, the first surrounding solder resist layer 174 surrounds all the second surrounding solder resist layers 171, 172, 173;

Each group of chip I/O soldering and signal transmission circuit layers 21, 22, and 23 includes chip I/O pads, signal transmission lines 212, 222, and 223, and one or more blind slots 12; The signal transmission in the circuit layers 21, 22, 23 for soldering and signal transmission passes through the chip I/O pads and signal transmission lines 212 in the circuit layers 21, 22, and 23 for chip I/O soldering and signal transmission. , 222, 223, or through each layer of blind vias 14 (141, 142, 143) and the lower patterned metal circuit layer (the second layer of patterned metal circuit layer 112, the third layer of patterned metal circuit layer 113, the fourth layer The corresponding parts in the patterned metal circuit layer 114) are jointly completed; between two or more chip I/O welding and signal transmission layers 21, 22, 23, and between multiple groups of chip I/O welding and signal transmission layers 21, 22, 23 and the external secondary cascade I/O soldering pads or patterns 1111 for signal transmission, by the blind holes 14 (141, 142, 143) of each layer and the lower patterned metal circuit layer (the second layer of patterned metal Corresponding parts of the circuit layer 112 , the third-layer patterned metal circuit layer 113 , and the fourth-layer patterned metal circuit layer 114 ) are completed together, such as the transmission path 16 in FIG. 2 .

Furthermore, the second patterned metal circuit layer 112 and the third patterned metal circuit layer 113 include multiple groups of chip I/O soldering and signal transmission circuit layers, electrical insulating regions and surrounding metal layers, all of which are conventional patterned layers. The specific structure of the metal circuit layer is not repeated here. The technological and electrical properties of the fourth patterned metal circuit layer 114 are large area metal formations.

2. Insulating dielectric layer

In the four-layer patterned metal circuit layer 11, the insulating dielectric layer 15 is located between the second layer of patterned metal circuit layer 112 and the third layer of patterned metal circuit layer 113, and is composed of an LCP substrate 151; The insulating dielectric layers between the patterned metal circuit layer 111 and the second patterned metal circuit layer 112, and between the third patterned metal circuit layer 113 and the fourth patterned metal circuit layer 114 are composed of the LCP substrate 151 and the The LCP adhesive film constitutes 152 . The melting point of the LCP adhesive film 152 is 10-60°C lower than the melting point of the LCP substrate 151; the mixed medium of the LCP substrate 151 and the LCP adhesive film 152 is used because a low melting point needs to be used in the multi-layer substrate lamination manufacturing process The LCP adhesive film 152 is used as the adhesive layer of the LCP substrate 152 .

3. Blind slot

The bottom of the blind trenches 12 ( 211 , 221 , 231 ) is a large-area metal ground layer in the second-layer patterned metal circuit layer 112 , the third-layer patterned metal circuit layer 113 or the fourth-layer patterned metal circuit layer 114 , and has a coating layer; the blind groove 12 is a chip I/O pad or pattern around the opening of the first patterned metal circuit layer 111 (ie, the chip I/O pad and the signal transmission lines 212, 222, 223 chip I/O pads or patterns); the number, size and depth of the blind grooves 12 are determined according to the number, size and height of the mounted chips.

4. Blind hole

The blind vias 14 can be classified into three types according to their positions in the four-layer patterned metal circuit layer 11:

The first type of blind vias 141 run through and connect the first patterned metal circuit layer 111 and the second patterned metal circuit layer 112, including being distributed on the external secondary cascade I/O soldering pads or patterns 1111 several blind holes;

The second type of blind vias 142 penetrate and connect the second patterned metal circuit layer 112 and the third patterned metal circuit layer 113;

The third type of blind vias 143 penetrate and connect the third patterned metal circuit layer 113 and the fourth patterned metal circuit layer 114;

All the blind vias 14 of the above three types can be vertically aligned or stacked in a staggered direction, so as to realize the interconnection requirements of any layer in the four-layer patterned metal circuit layer 11 . In addition, each blind hole 14 has the same diameter, and the blind hole depth-diameter ratio is less than or equal to 1, and the blind hole 14 is filled with solid electroplated copper. The diameters of the three types of blind holes 14 are the same. On the one hand, the solid electroplating copper can be uniformly fabricated in the later stage; more importantly, it can be uniformly deformed during the later high-temperature assembly process, thereby improving the interconnection reliability of the overall package substrate. The blind hole depth-to-diameter ratio is less than or equal to 1, which can better realize the process of blind hole filling and solid copper electroplating, and avoid the appearance of void defects in electroplated copper.

Example 2

As shown in FIG. 3 , this embodiment provides a method for manufacturing a four-layer wiring LCP package substrate 1 as described in Embodiment 1, which includes the following steps:

S1, as shown in FIG. 4a, laser drilling blind holes on the double-sided copper-clad LCP substrate 151 for connecting the second patterned metal circuit layer 112 and the third patterned metal circuit layer 113, the blind hole aspect ratio ≤1;

S2, as shown in Figure 4b, blind holes are metallized to form blind holes filled with solid electroplated copper; before blind hole metallization, blind hole decontamination, plasma activation and other pretreatments need to be carried out; blind hole metallization is performed by filling The hole electroplating copper process is realized. After the hole is filled and electroplated, the copper plating layer on the surface is thinned to form a blind hole filled with solid electroplated copper, and the blind hole is the second type of blind hole 142;

S3, as shown in Fig. 4c, the second layer of patterned metal circuit layer 112 and the second layer of patterned metal circuit layer 112 and the second layer of patterned metal circuit layer 112 and the second layer of patterned metal circuit layer 112 and the second layer of patterned metal circuit layer 112 and the second layer of patterned metal circuit layer 112 and the second layer of patterned metal circuit layer 112 and the second layer of patterned metal circuit layer 112 and the second layer of the double-sided copper-clad LCP substrate can be fabricated on the upper and lower surfaces of the double-sided copper-clad LCP substrate through conventional processes such as film bonding of the printed board → exposure → development → etching, as shown in Fig. 4c. Three-layer patterned metal circuit layer 113;

S4, take the first single-sided copper-clad LCP substrate 151, the second single-sided copper-clad LCP substrate 152, the first LCP adhesive film 151, and the second LCP adhesive film 152, and then cover the first single-sided coating from top to bottom. The order of the copper LCP substrate 151, the first LCP adhesive film 152, the double-sided copper-clad LCP substrate 151 after S3 treatment, the second LCP adhesive film 152, and the second single-sided copper-clad LCP substrate 151 is performed as shown in FIG. 4d. The LCP multi-layer substrate shown in FIG. 4e is formed by pressing and laminating as shown in FIG. 4e; wherein, the copper-clad surface of the first single-sided copper-clad LCP substrate 151 faces upward, and the second single-sided copper-clad LCP substrate 152 is The copper-clad surface faces down; the melting points of the first LCP adhesive film and the second LCP adhesive film are lower than the melting points of the first single-sided copper-clad LCP substrate and the second single-sided copper-clad LCP substrate, generally 10-60 °C;

S5, as shown in FIG. 4f, laser drilling blind holes on the first single-sided copper-clad LCP substrate 151 and the second single-sided copper-clad LCP substrate 151 of the LCP multilayer substrate, wherein the first single-sided copper-clad LCP substrate is The blind hole on 151 is used to connect the first layer of patterned metal circuit layer 111 and the second layer of patterned metal circuit layer 112, and the blind hole on the second single-sided copper-clad LCP substrate 151 is used to connect the third layer The patterned metal circuit layer 113 and the fourth layer of patterned metal circuit layer 114, the blind hole aspect ratio≤1;

S6, as shown in FIG. 4g, blind holes are metallized to form blind holes filled with solid electroplated copper; the method of this step is the same as that of step S2, and finally the first type blind holes 141 and the third type blind holes 143 are formed;

S7, as shown in FIG. 4h, the same method as in step S3 can be used to manufacture the first patterned metal circuit layer 111 (including the external secondary cascade I) on the upper surface of the first single-sided copper-clad LCP substrate 151 /O soldering pad or pattern 1111), fabricate the fourth layer of patterned metal circuit layer 115 on the lower surface of the second single-sided copper-clad LCP substrate 151; and remove the blind groove in the first layer of patterned metal circuit layer. Copper in area 121; blind slot slot area 121 is a location determined according to design, this area is a non-metallic area, and can be processed by etching copper process, and the copper layer of blind slot slot area 121 is removed to facilitate subsequent laser slotting processing ;

S8, as shown in FIG. 4i, the blind groove area is grooved by a laser processing method to form a blind groove 12 on which the chip is mounted, and the bottom and side walls of the blind groove 12 are decontaminated; the laser processing method, the The laser light source is solid ultraviolet laser or gas carbon dioxide laser;

S9, as shown in FIG. 4j, the coating layer is fabricated on the first layer of patterned metal circuit layer 111, the fourth layer of patterned metal circuit layer 114 and the bottom of the blind groove 12, and is fabricated on the corresponding part of the coating layer 13 After the solder resist layer 17 is formed on the upper surface, the LCP package substrate 1 is obtained. The material of the coating layer 13 includes but is not limited to electroplating gold, electroless nickel gold, and electroless nickel palladium gold.

S10 , if the LCP package substrate is manufactured in a spliced form through steps S1 to S9 , the LCP package substrate manufactured in the spliced form is milled to form a single LCP package substrate.

That is to say, when a single LCP substrate is directly used to manufacture the LCP packaging substrate through steps S1 to S9, the obtained LCP packaging substrate 1 is the required structure; when the LCP packaging substrate is manufactured in a spliced form through steps S1 to S9, the obtained LCP packaging substrate The substrate 1 needs to be milled to be the required structure.

Example 3

As shown in FIG. 5 , based on the LCP packaging substrate described in Embodiment 1-2, this embodiment provides a multi-chip system-in-package structure 2 , including: the LCP packaging substrate 1 described in Embodiment 1-2, and Chip 3, metal frame 5 and metal cover 6;

The multi-chip system-in-package structure 2 is fixed on the PCB motherboard by means of conductive adhesive bonding or welding, and the external secondary cascade I/O welding pads or patterns 1111 located on the LCP packaging substrate 1 are used. As the multi-chip system-in-package structure 2 to the external secondary cascade I/O interface;

Metal rib 51 is distributed in the metal enclosure 5; the metal enclosure 5 and the metal rib 51 are welded to the upper surface of the LCP package substrate 1 and make the external secondary cascade I/O soldering pads or The pattern 1111 is outside the metal enclosure 5, and the metal cover 6 is welded to the metal enclosure 5 and the metal spacer 51, so that the LCP package substrate 1 and the metal cover 6 pass through the metal enclosure 5 and the metal spacer. The ribs 51 form a plurality of cavity structures 7 with hermetic packaging performance and electromagnetic shielding performance; each cavity structure 7 contains one or more blind grooves 12; each blind groove 12 is used to install a chip 3, when installed When the chip 3 has no electromagnetic shielding requirements, it can be installed in the same cavity structure 7, and when the installed chip 3 has electromagnetic shielding requirements, it is installed in a different cavity structure 7; the chips 3 are bonded by conductive glue. In the blind groove 12 , it is electrically interconnected with the chip I/O soldering and signal transmission circuit layers 21 , 22 and 23 in the first patterned metal circuit layer 111 by means of gold wire 4 bonding.

The signal transmission in each group of chip I/O soldering and signal transmission circuit layers 21, 22, and 23 passes through the chip I/O pads in the group of chip I/O soldering and signal transmission circuit layers 21, 22, and 23. and signal transmission lines 212, 222, 223, or through the blind vias 14 (141, 142, 143) of each layer and the lower patterned metal circuit layers (the second patterned metal circuit layer 112, the third patterned metal circuit layer 113. Corresponding parts in the fourth layer of patterned metal circuit layer 114) are jointly completed; two or more chip I/O welding and signal transmission layers 21, 22, 23, and multiple groups of chip I/O welding and signal transmission The signal transmission between the layers 21, 22, 23 and the external secondary cascade I/O soldering pads or patterns 1111 is performed by the blind holes 14 (141, 142, 143) of each layer and the lower patterned metal circuit layer (No. The corresponding parts of the second-layer patterned metal circuit layer 112 , the third-layer patterned metal circuit layer 113 , and the fourth-layer patterned metal circuit layer 114 ) are completed together, as shown in the transmission path 16 in FIG. 5 .

The above descriptions are only preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention shall be included in the protection of the present invention. within the range.

Claims (8)

1. A four-layer wiring LCP package substrate, comprising:

the metal circuit layer comprises 4 graphical metal circuit layers distributed from the surface to the bottom surface, namely a first graphical metal circuit layer, a second graphical metal circuit layer, a third graphical metal circuit layer and a fourth graphical metal circuit layer in sequence; at least one edge of the outermost periphery of the first patterned metal circuit layer is distributed with bonding pads or patterns for external secondary cascade I/O welding of the LCP packaging substrate; the process property and the electrical property of the fourth patterned metal circuit layer are large-area metal strata;

3 insulating medium layers positioned between the adjacent graphical metal circuit layers;

the plurality of blind grooves are positioned in the insulating medium layer and have openings facing the first patterned metal circuit layer;

a plurality of blind holes penetrating and connecting the adjacent patterned metal circuit layers, wherein a plurality of blind holes are distributed on the pad or the pattern for the outward secondary cascade I/O welding;

the first layer of graphical metal circuit layer comprises a bonding pad or graph for external secondary cascade I/O welding at the outermost periphery, a surrounding metal layer at the inner side and a plurality of groups of chip I/O welding and signal transmission line layers at the inner side of the surrounding metal layer, each group of chip I/O welding and signal transmission line layers is in a rectangular or special-shaped island shape, and each group of chip I/O welding and signal transmission line layers are connected with the surrounding metal layer through an electric insulation area; the surrounding metal layer has an electrical property of a grounding layer and a process property of an airtight welding layer; a coating layer and an upper surface solder mask layer are sequentially arranged on the upper surface of the first patterned metal circuit layer; the coating layer covers the external secondary cascade I/O welding bonding pad or pattern, the surrounding metal layer and each group of chip I/O welding and signal transmission line layer; the upper surface solder mask layer comprises a first surrounding solder mask layer and a plurality of second surrounding solder mask layers, wherein each second surrounding solder mask layer correspondingly surrounds each electric insulation area, and the first surrounding solder mask layer surrounds all the second surrounding solder mask layers;

each group of chip I/O welding and signal transmission line layers comprise chip I/O bonding pads, signal transmission lines and one or more blind slots; the transmission of signals in the circuit layer for I/O welding and signal transmission of each group of chips is completed through chip I/O bonding pads and signal transmission lines in the circuit layer for I/O welding and signal transmission of the group of chips or through corresponding parts in each layer of blind holes and the lower patterned metal circuit layer; signal transmission between two or more groups of chip I/O welding and signal transmission layers, between a plurality of groups of chip I/O welding and signal transmission layers and a bonding pad or a pattern for external secondary cascade I/O welding is jointly completed by corresponding parts in each layer of blind holes and the lower layer of graphical metal circuit layer;

the insulating medium layer is positioned between the second layer of graphical metal circuit layer and the third layer of graphical metal circuit layer and consists of LCP substrates; and the insulating dielectric layers are positioned between the first layer of graphical metal circuit layer and the second layer of graphical metal circuit layer and between the third layer of graphical metal circuit layer and the fourth layer of graphical metal circuit layer and comprise LCP substrates and LCP adhesive films.

2. The LCP package substrate of claim 1, wherein in the 4 patterned metal circuit layers, the LCP adhesive film has a melting point 10-60 ℃ lower than the melting point of the LCP substrate.

3. The LCP package substrate of claim 1, wherein the bottom of the blind trench is a large-area metal ground layer in the second, third or fourth patterned metal circuit layer, and has a coating layer; the blind groove is a chip I/O bonding pad or a pattern around the opening of the first patterned metal circuit layer; the number, size and depth of the blind grooves are determined according to the number, size and height of the mounted chips.

4. The LCP package substrate of claim 1, wherein all blind vias are vertically aligned or staggered for stacking, for implementing any of the 4 patterned metal wiring layers; the diameter of each blind hole is the same, the depth-diameter ratio of the blind holes is less than or equal to 1, and the blind holes are filled with solid electrolytic copper.

5. A method of manufacturing a four-layer wire LCP package substrate, wherein the method is used to manufacture the LCP package substrate of any one of claims 1 to 4, comprising the steps of:

s1, laser drilling blind holes on the double-sided copper-clad LCP substrate for connecting the second patterned metal circuit layer and the third patterned metal circuit layer;

s2, performing blind hole metallization to form blind holes filled with solid electroplated copper;

s3, manufacturing a second layer of graphical metal circuit layer and a third layer of graphical metal circuit layer on the upper surface and the lower surface of the double-sided copper-clad LCP substrate;

s4, taking a first single-sided copper-clad LCP substrate, a second single-sided copper-clad LCP substrate, a first LCP adhesive film and a second LCP adhesive film, and then aligning, laminating and laminating the first single-sided copper-clad LCP substrate, the first LCP adhesive film, the double-sided copper-clad LCP substrate processed in the step S3, the second LCP adhesive film and the second single-sided copper-clad LCP substrate from top to bottom to form an LCP multi-layer substrate; the copper-clad surface of the first single-sided copper-clad LCP substrate faces upwards, and the copper-clad surface of the second single-sided copper-clad LCP substrate faces downwards; the melting points of the first LCP adhesive film and the second LCP adhesive film are lower than those of the first single-sided copper-clad LCP substrate and the second single-sided copper-clad LCP substrate;

s5, blind holes are drilled on a first single-side copper-clad LCP substrate and a second single-side copper-clad LCP substrate of the LCP multilayer substrate through laser, and the blind holes are respectively used for connecting a first graphical metal circuit layer and a second graphical metal circuit layer, and a third graphical metal circuit layer and a fourth graphical metal circuit layer;

s6, performing blind hole metallization to form blind holes filled with solid electroplated copper;

s7, manufacturing a first patterned metal circuit layer on the upper surface of the first single-sided copper-clad LCP substrate, and manufacturing a fourth patterned metal circuit layer on the lower surface of the second single-sided copper-clad LCP substrate; removing copper in a blind groove slotting region in the first patterned metal circuit layer;

s8, grooving the grooving region of the blind groove by adopting a laser processing means to form a blind groove for mounting the chip, and performing decontamination treatment on the bottom and the side wall of the blind groove;

s9, coating layer manufacturing is carried out on the first layer of graphical metal circuit layer, the fourth layer of graphical metal circuit layer and the bottom of the blind groove, and after an upper surface solder mask layer is manufactured on the corresponding part of the coating layer, the LCP packaging substrate is obtained;

and S10, if the LCP packaging substrate is manufactured in a splicing mode through the steps S1-S9, milling the LCP packaging substrate manufactured in the splicing mode to form a single LCP packaging substrate.

6. The method for manufacturing the LCP package substrate as claimed in claim 5, wherein the ratio of the blind hole depth to the blind hole depth is less than or equal to 1.

7. The method for manufacturing the LCP packaging substrate as claimed in claim 5, wherein the melting point of the first LCP adhesive film and the second LCP adhesive film is 10-60 ℃ lower than that of the first single-sided copper-clad LCP substrate and the second single-sided copper-clad LCP substrate.

8. A multi-chip system-in-package structure, comprising: the LCP package substrate of any one of claims 1-4, and a chip, a metal enclosure and a metal lid;

the multi-chip system-in-package structure is fixed on a PCB motherboard in a conductive adhesive bonding or welding mode, and a bonding pad or a pattern for external secondary cascade I/O welding on the LCP packaging substrate is used as an external secondary cascade I/O interface of the multi-chip system-in-package structure;

metal spacer bars are distributed in the metal surrounding frame; the metal enclosure frame and the metal spacer ribs are welded on the upper surface of the LCP packaging substrate, the external secondary cascade I/O welding pads or patterns are arranged outside the metal enclosure frame, the metal cover plate is welded on the metal enclosure frame and the metal spacer ribs, and a plurality of cavity structures with airtight packaging performance and electromagnetic shielding performance are formed between the LCP packaging substrate and the metal cover plate through the metal enclosure frame and the metal spacer ribs; each cavity structure comprises one or more blind grooves; each blind slot is used for mounting a chip, when the mounted chip has no electromagnetic shielding requirement, the mounted chip is mounted in the same cavity structure, and when the mounted chip has the electromagnetic shielding requirement, the mounted chip is mounted in different cavity structures; the chip is adhered in the blind groove through the conductive adhesive and is electrically interconnected with the chip I/O welding and signal transmission circuit layer in the first patterned metal circuit layer in a gold wire bonding mode.

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