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CN112346296A - Process control method for photolithographically processed semiconductor devices - Google Patents

Process control method for photolithographically processed semiconductor devices Download PDF

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Publication number
CN112346296A
CN112346296A CN201910720035.5A CN201910720035A CN112346296A CN 112346296 A CN112346296 A CN 112346296A CN 201910720035 A CN201910720035 A CN 201910720035A CN 112346296 A CN112346296 A CN 112346296A
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exposure
wafer
characteristic
uncorrected
dose
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CN112346296B (en
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S·布尔
B·哈贝茨
金晥洙
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Konjac Ltd
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Konjac Ltd
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    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/54—Absorbers, e.g. of opaque materials
    • G03F1/56—Organic absorbers, e.g. of photo-resists
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
    • G03F1/68—Preparation processes not covered by groups G03F1/20 - G03F1/50
    • G03F1/76—Patterning of masks by imaging
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
    • G03F7/70605—Workpiece metrology
    • G03F7/70616—Monitoring the printed patterns
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

The present disclosure provides a process control method for a lithographically processed semiconductor device and a corresponding apparatus. Exposing the photoresist layer to an exposure beam using an exposure tool assembly, wherein the photoresist layer coats the semiconductor substrate, and wherein, for each exposure, a current exposure parameter set is used that includes at least a defocus value and an exposure dose. The exposed photoresist layer is developed, wherein a resist pattern is formed from the photoresist layer. Characteristic features of the resist pattern and/or characteristic features of a substrate pattern derived from the resist pattern are measured. Updating the current exposure parameter set in response to a deviation of the measured feature characteristic from a target feature characteristic. Uncorrected feature characteristics of a hypothetical resist pattern to be formed without updating the exposure parameter set are estimated. In response to information obtained from the uncorrected feature characteristics, a measurement strategy for the feature characteristics may be changed or the current exposure parameter set may be updated.

Description

Process control method for semiconductor device processed by photoetching
Technical Field
Embodiments relate to the fabrication of semiconductor devices, such as volatile and non-volatile memory devices, logic circuits, microprocessors, power semiconductor devices, and flat panel devices, in which an exposure process transfers a pattern into a photoresist layer on a semiconductor wafer. The exposure process may use APC (advanced process control) to determine the exposure parameters for the current exposure based on the metrology results from previously exposed semiconductor wafers. Embodiments further relate to a wafer fabrication assembly including an exposure tool assembly.
Background
During the manufacturing process of semiconductor devices, various physical components of functional elements, such as transistors, diodes, capacitors, resistors, and wiring connections, are formed in and on the semiconductor substrate, for example as doped regions in the semiconductor substrate and in layers deposited on the processed surface of the semiconductor substrate. These solid features may be formed layer-by-layer by combining the deposition of one or more layers on a machined surface and transferring a particular pattern into the layers using a patterning process, wherein the patterning process locally modifies (modifies) or removes portions of the relevant layer(s) (e.g., by etching). Fluctuations in the patterning process result in deviations from the target dimensions and may adversely affect process yield or may result in a relatively broad distribution of parameters of the final semiconductor device.
Patterning by photomask (photomasking) involves depositing a photoresist layer on the processed surface of a semiconductor wafer. The exposure process projects a reticle (reticle) pattern of a photomask into a photoresist layer, wherein in the photoresist layer, photoactive components are selectively modified in exposed portions relative to unexposed portions such that after exposure the photoresist layer comprises a latent image of the reticle pattern. The development process selectively removes the modified or unmodified portions. The developed resist layer may be used as an etch mask (etch mask) or an implant mask (implant mask).
The physical size of the resist pattern (resist pattern) depends on, among other things, the exposure dose (exposure dose) and defocus value (defocus value). The exposure dose represents the energy of the exposure radiation used to expose the photoresist layer in a particular pattern. Defocus refers to the distance between the wafer surface and the focal plane (focal plane) of the exposure radiation. The physical dimensions of certain critical patterns in the photoresist layer can be measured and compared to target dimensions. The APC can adjust the exposure dose and/or defocus (defocus) of the next exposure according to the measurement result for the critical dimension.
There is a need to improve the physical dimension uniformity of photoresist patterns across wafers (e.g., intra-wafer uniformity), and between wafers (e.g., inter-wafer uniformity) with less effort and/or to reduce metrology work without adversely affecting intra-wafer uniformity and inter-wafer uniformity.
Disclosure of Invention
In one aspect, an embodiment provides an advanced process control method, including: exposing the photoresist layer coating the semiconductor substrate to an exposure beam using an exposure tool assembly, wherein for each exposure a current exposure parameter set comprising at least a defocus value and an exposure dose is used; developing the exposed photoresist layer to form a resist pattern; measuring a characteristic of the resist pattern and/or a characteristic of a substrate pattern derived from the resist pattern and updating the current exposure parameter set in response to a deviation of the measured characteristic from a target characteristic; estimating an uncorrected feature characteristic of a hypothetical resist pattern formed without updating the exposure parameter set; and at least one of the following: (i) change a measurement strategy for the feature characteristic in response to information obtained from the uncorrected feature characteristic, and (ii) update the current exposure parameter set in response to information obtained from the uncorrected feature characteristic.
According to another aspect, embodiments provide a wafer fabrication assembly comprising: an exposure tool assembly configured to i) expose a photoresist layer coating a semiconductor substrate to an exposure beam according to a current exposure parameter set, and ii) form a resist pattern through the exposed photoresist layer; a metrology unit configured to measure a characteristic of at least one of the resist pattern and a substrate pattern derived from the resist pattern; an APC unit configured to update the set of exposure parameters in response to a deviation of the measured feature characteristic from a target feature characteristic; and a calculation unit configured to estimate an uncorrected feature characteristic of a hypothetical resist pattern formed without updating the exposure parameter set.
Drawings
Fig. 1 is a schematic block diagram of a portion of a semiconductor device manufacturing assembly including an advanced process control unit for controlling exposure parameters according to a reference example for illustrating a context useful for understanding embodiments.
Fig. 2 is a schematic block diagram of a portion of a semiconductor device manufacturing assembly including a computing unit for estimating uncorrected (de-corrected) feature characteristics of hypothetical structures formed without updating exposure parameters, according to an embodiment.
Fig. 3 is a schematic flow chart diagram illustrating a method for advanced process control according to an embodiment involving an update of exposure parameters.
FIG. 4 is a schematic block diagram of a portion of a semiconductor device manufacturing assembly including a computing unit in accordance with an embodiment involving control of calibration data for an exposure tool assembly.
Fig. 5 is a block diagram schematically illustrating an advanced process control method according to an embodiment.
FIG. 6 is a schematic diagram illustrating measured and uncorrected critical dimensions for illustrating the effect of the embodiment of FIG. 4.
Fig. 7 is a block diagram schematically illustrating a method of using information obtained by an apc method according to a further embodiment.
Fig. 8 is a schematic block diagram of a portion of a semiconductor device manufacturing assembly including a computational unit according to an embodiment involving modification of a sampling plan.
Fig. 9 is a schematic block diagram of a portion of a semiconductor device manufacturing assembly including a computational unit according to an embodiment involving control of an etching process.
Fig. 10 is a schematic block diagram of a portion of a semiconductor device fabrication assembly according to a further embodiment.
Detailed Description
Fig. 1 shows a portion of a conventional semiconductor device manufacturing assembly 390 having an exposure tool assembly 320 that includes a coater unit 322, an exposure unit 324, and a developer unit 326. A plurality of input wafer lots (lot)410 of pre-processed semiconductor substrates are provided in sequence to a semiconductor device manufacturing assembly 390. The semiconductor substrate may be, for example, a semiconductor wafer, a glass substrate having a semiconductor structure formed thereon, or an SOI (semiconductor on insulator) wafer. Regardless of the type of semiconductor substrate, the semiconductor substrate is hereinafter referred to as wafer 401.
The number of wafers 401 per wafer lot 410 is typically up to 25. Wafers 401 in the same wafer lot 410 may undergo the same process to form the same electronic circuit. For example, the wafers 401 in each wafer lot 410 may be provided to different process units of the same type in sequence, wherein the same process is applied to the process units of the same type. Alternatively, the wafers 401 may be provided to the same processing unit in sequence, wherein each processing unit may include one or more sub-units at which some of the wafers 401 in each wafer lot 410 may be processed in parallel.
In the example of fig. 1, wafers 401 in a wafer lot 410 are provided to an applicator unit 322 of an exposure tool assembly 320. The applicator unit 322 coats the wafer 401 with a photoresist layer or a photoresist layer system with or without an anti-reflection coating. The coater unit 322 may include a spin body unit that dispenses resist material on the wafer surface and distributes the resist material uniformly by rotating the wafer 401. The applicator unit 322 may include a heating facility for evaporating a portion of the solvent in the photoresist. The wafer 401 coated with at least a photoresist layer is transferred to an exposure unit 324.
The exposure unit 324 generates an exposure beam that transfers the target pattern into the photoresist layer, wherein the exposure beam can selectively activate the photoactive component of the photoresist layer in the exposed portions. The exposure beam may be a beam of electromagnetic radiation or a particle beam. For example, the exposure beam is an electron beam that can scan the photoresist layer, wherein intensity modulation or blanking (blanking) of the beam can generate the target pattern. According to another embodiment, the exposure beam comprises light or electromagnetic radiation having a wavelength shorter than 365nm (e.g., 193nm or less), wherein the electromagnetic radiation passes through or is reflected at the reticle and images the reticle pattern into the photoresist layer.
In the portion of the photoresist layer exposed to the exposure beam, the photoactive component can affect polymerization of a previously unpolymerized compound or depolymerization of a previously polymerized compound.
The exposure of one wafer 401 may comprise a single exposure of the entire processed surface, or may comprise multiple exposures in adjacent exposure fields on the processed surface, wherein the same pattern is imaged into each exposure field. Each exposure is defined by an exposure dose of the exposure radiation and a defocus value indicative of a distance between the processed surface and a focal plane of the exposure radiation. The defocus and/or exposure dose may be different for different exposure fields on the same wafer 401, different between different wafers in a wafer lot 410, and/or different between different wafer lots 410. The wafer 401 with the exposed photoresist layer is transferred to a developer unit 326.
The developer unit 326 removes the exposed portions of the photoresist layer relative to the unexposed portions or removes the unexposed portions relative to the exposed portions. The developer unit 326 may include a heated chamber for post-exposure baking and use different dissolution rates for the exposed and unexposed portions of the photoresist layer to selectively dissolve the exposed portions relative to the unexposed portions, or vice versa. The developer unit 326 may include a heated chamber for evaporating the remaining solvent and for chemically modifying the developed resist layer, e.g., to harden the developed resist layer or to improve adhesion of the developed resist layer on the wafer surface. The developed resist layer forms a resist pattern including a plurality of resist features.
Metrology unit 330 can measure feature characteristics (features) of key resist features of the resist pattern at the sampling points. The metrology unit 330 may be an integral part of the exposure tool assembly 320 or the wafer 401 may be transferred to a remote metrology unit 330. The feature characteristics include the physical dimensions of the critical resist features. The sampling points are locations on the wafer defined in the sampling plan. For example, the metrology unit 330 may obtain information about feature characteristics by OCD (optical critical dimension) scatterometry, examining images obtained by SEM (scanning electron microscopy), and examining images obtained by optical microscopy.
For example, the feature characteristics of a critical resist feature may include physical dimensions such as the diameter of a circular resist feature, the length of the minor and major axes of a non-circular resist feature, the line width of a stripe-shaped resist feature, the width of the spaces between resist features, the sidewall angle of a resist feature, the area of a resist feature, and other properties such as line edge roughness of a resist feature. Hereinafter, the abbreviation "CD" includes all kinds of feature characteristics and is not limited to the line width and space width of the key resist features, and the area of the key resist features.
The post-exposure process may use the resist pattern, for example, as an etching mask for forming grooves and trenches in the semiconductor substrate, as an implantation mask, or as a mask for other modification processes.
The APC unit 290 receives the measured CD of the measured wafer at the selected location defined in the sampling plan. Based on the CD measured on one or more previous wafers processed at the same exposure tool assembly 320 or at other exposure tool assemblies, the APC unit 290 individually adjusts the exposure dose and/or defocus in the exposure unit 324 for each exposure field, each wafer, and/or each wafer lot.
Fig. 2 illustrates a wafer fabrication assembly 300 that includes means for determining exposure parameters, metrology settings, and advanced process control settings for lithographically processed semiconductor devices. The wafer fabrication assembly 300 may include an exposure tool assembly 320 and a metrology unit 330 having the functionality as described with reference to fig. 1.
The APC unit 290 can determine an exposure parameter set (set) for the current exposure based on the measured CD received from the metrology unit 330. The exposure parameter set may include dose/focus correction data, e.g., a correction value for focus, a correction value for exposure dose, or a correction value for both focus and exposure dose. The APC unit 290 can further consider that the previous correction data of the previous exposure for a predetermined number of times is multiplied by a specific weight coefficient, respectively. In the absence of other information received from the outside, the APC unit 290 outputs new dose/focus correction data to the exposure tool assembly 320.
The wafer fabrication component 300 further includes a computing unit 200 that receives information regarding the particular characteristic features of the wafer being measured. For example, the metrology unit 330 or a MES (manufacturing execution System) receiving and managing measurement data obtained by a plurality of metrology units may pass a CD as defined above to the computing unit 200. In addition, the calculation unit 200 may receive wafer context (context) information WCI identifying the wafer 401 from which the CD is obtained. For example, the wafer context information WCI may include: parameters that identify the source, type, and parameters of the wafer 401, the processing tool and processing unit (e.g., reticle used in the exposure tool assembly 320) that the wafer 401 is being processed, the process conditions that the wafer of interest has experienced, identifiers of the process gases and process fluids to which the wafer of interest has been exposed, and temporal information (temporal information) including the date and time of the previous process.
The computing unit 200 also receives and/or maintains exposure information that may be used for process corrections in the exposure tool assembly 320, such as a previously applied exposure dose, focus, previous dose/focus correction data, and/or a temperature profile of a post-exposure bake. The exposure information that is available for process correction may be included in the wafer context information WCI or may be transmitted directly from the exposure tool assembly 320 to the computing unit 200.
The primary (primary stage) of the calculation unit 200 may determine the dose error and focus error for the current exposure based on the measured CD, and exposure information received from the metrology unit 330. The exposure information may include exposure parameters of one or more previous exposures, a dose error and a focus error of one or more previous exposures, and/or focus data obtained by a measurement focused on a product (on-product focus), wherein the focus error may be zero in case the calculation unit 200 receives the data obtained by the measurement focused on the product.
To determine the dose error and focus error, the primary of the calculation unit 200 may use a physical model describing the relationship between CD, exposure dose and focus. From the measured CD, a physical model (i.e., a polynomial model) that may be defined by basis functions and coefficients may obtain exposure dose and/or defocus values that are valid for the sample points from which the measured CD has been obtained.
A secondary (secondary stage) of the calculation unit 200 may calculate alternative uncorrected feature characteristics of the hypothetical resist pattern to be formed without any update to the exposure parameter set. In other words, the calculation unit 200 calculates the CD for the case where any advanced process control is omitted. According to an embodiment, the secondary stage may retrospectively (retrospectaly) calculate the optimal dose value and the optimal focus value for previously processed wafers.
By estimating hypothetical uncorrected feature characteristics that would result from an exposure without applying an update process to defocus and/or exposure dose, the calculation unit 200 can facilitate the calculation and analysis of parameters for all processes from the exposure up to at least the first post-exposure processing unit 340 while basic advanced process control of the exposure remains effective and the processed wafer 401 is able to meet typical degrees of process tolerance. The calculation unit 200 may allow for the determination of process correction values and CD uniformity using different wafer models, wafer context information, APC settings and/or adjustments in the sampling plan without temporarily bypassing the advanced process control, such that wafer yield remains unaffected and no wafer is lost due to the absence of advanced process control.
For this purpose, the results RS obtained by the secondary of the calculation unit 200 may be transmitted to the expert system 206, to the user interface 205 for visualizing the results for a human operator (user), to the post-exposure processing unit 340, or to the APC unit 290. The results of the secondary of the calculation unit 200 may be used to influence the wafer processing, for example by modifying the settings of the advanced process control or by redefining the wafer model, by controlling the post-exposure processing unit 340 in a way that compensates for parameter drift, or by changing the measurement strategy (e.g. by modifying the sampling plan used by the metrology unit 330).
For example, based on the information obtained from the calculation unit 200, the sampling plan used by the metrology unit 330 may be modified by skipping the sampling points that have the least impact on the determination of the model coefficients of the model describing the CD distribution across the complete wafer surface according to one or more polynomials.
Alternatively or additionally, the alternative defocus/dose correction parameters may be obtained in a manner that smoothes or minimizes deviations of the characteristic from the target value. To this end, uncorrected CDs may be searched for trends specific to certain parameters of wafer context information. The alternative dose/focus correction data may be transmitted to the APC unit 290 where the modified defocus/dose correction parameters may override the conventionally derived dose/focus correction values for the next exposure.
The simulation of the behavior of the wafer fabrication component 300 in combination with the simulation of the results of other parameter settings at the user interface 205 allows for distinguishing between different sources or environments of CD variation. The tendency and trend of parameter fluctuations can be evaluated more accurately and without disturbing other effects. In addition, the impact of different parameter settings on a particular feature characteristic may be evaluated to determine which feature characteristics at the original sampling point are most critical.
Fig. 3 illustrates details of a simulation performed during the course of a method of modifying the exposure dose for a current exposure based on an estimated CD predicted for the current exposure from an uncorrected CD for a previous exposure. The simulation may be performed by the computing unit 200 of fig. 2. For simplicity, simulation refers to an embodiment that only considers exposure dose. The simulation may be applied to defocus, to a combination of defocus and exposure dose, and also to further parameters and parameter combinations.
The initialization step 510 initializes the value of a counter n (which may count individual wafers or wafer lots), the corrected value CorrVal (1) for the first wafer or wafer lot, and the exposure dose ExpDos (1) for the first exposure, which may be derived from only the target CD and the device parameters. Counter step 520 may increment counter n by one. In an exposure step 530, the exposure tool exposes the one or more wafers assigned to the counter value n at an initial exposure dose. At least one critical dimension on a single wafer or multiple wafers (e.g., all wafers assigned to the same lot) is obtained by the measuring step 540. From the measured CD, an estimation step 550 estimates an uncorrected critical dimension CD (n) by adding or subtracting the fraction due to the correction dose to the measured CD, where the estimated CD (1) is equal to the measured CD for n-1.
Up to a predefined number n0For a wafer or wafer lot, the relaxed APC settings may be used in APC step 570 to calculate an exposure dose for the next individual wafer or wafer lot based on one or more previously measured critical dimensions CD (n), CD (n-1).
When the number of measurements exceeds a predefined number n0And sufficient information is contained in the estimated uncorrected critical dimension CD (1) … CD (n), the predictor step 582 can calculate the hypothetical critical dimension PCD (n +1) for the next single wafer or wafer lot from the previously estimated uncorrected CD and the alternative dose correction. To this end, predictor step 582 may interpret wafer context information for the current wafer and the previous wafer to obtain a context. The correction step 584 may determine an alternative dose correction for the next exposure based on the previously estimated CD.
The following table illustrates the embodiment of fig. 3 by way of example. At 25mJ/cm2Exposure to a given reticle yields a target CD of 30 nm. Approximately 25mJ/cm2At exposure dose of (2), +1mJ/cm2Exposure dose fluctuation of (2) leads to CD reduction1nm。
In the example of Table 1, the exposure dose is 25mJ/cm2Results in a measured CD of 32nm, which deviates from the target CD by +2 nm. Consider the additional one mJ/cm according to a model describing the relationship between dose and CD2Resulting in a 1nm reduction of the line, so that APC increases the exposure dose by +2mJ/cm2To reduce CD by 2nm to meet the target CD. But due to process variations as discussed above, the average measured CD of the second wafer lot may again deviate from the expected 30nm and may be, for example, 30.5 nm. For exposure of the next wafer lot, APC can further increase the correction dose by 0.5mJ/cm2To offset the remaining CD bias of +0.5 nm. Likewise, further process fluctuations affected the average measured CD of the third wafer lot to 29.7nm, resulting in a correction dose reduction of 0.3mJ/cm for the fourth wafer lot2。
Figure BDA0002156866420000081
TABLE 1
Table 2 relates to an example of how uncorrected CD values can be estimated based on measured CD and corrected CD due to correction dose. For the first lot, the uncorrected CD is equal to the measured CD because no correction dose was used to generate the corrected CD. For the second batch, 2mJ/cm had been used2Resulting in a reduction of the line width of 2 nm. Thus, without a correction dose, the actual line width would be 32.5nm instead of 30.0 nm. For the third batch, the CD measured was 29.7nm, but the dose was corrected (2.5 mJ/cm in total)2) The linewidth was reduced by 2.5nm, giving an uncorrected CD of 32.2 nm.
Figure BDA0002156866420000082
TABLE 2
Uncorrected CDs can be searched for trends, periodicity, or contextual dependencies (dependency), or there are no trends and periodicity or contextual dependencies.
Fig. 4 relates to a wafer manufacturing assembly 300 with a calculation unit 200 for improving correction values of exposure dose and/or defocus in an exposure tool assembly 320. The metrology unit 330 can obtain the CDs from the wafer 401 and transfer the CDs to the APC unit 290 and the calculation unit 200.
The metrology unit 330 transmits the measured CDs to the calculation unit 200. The calculation unit 200 may directly use the measured CDs for first obtaining a model describing the CD distribution across the complete wafer surface according to one or more polynomials and for calculating the uncorrected feature characteristics of the hypothetical resist pattern. According to another embodiment, the calculation unit 200 uses the relation between CD and exposure dose and defocus to obtain the dose error and focus error and thereafter uses the dose error and focus error, or dose setting and focus setting, e.g. for determining model coefficients of a model describing the focus error and dose error or the optimal dose and/or optimal focus for each point of the model, such that the model coefficients do not depend on the type of CD.
The APC unit 290 and the calculation unit 200 can be assigned to different hardware components, e.g. controllers, servers, computers connected via a data transmission interface, and/or to different software modules exchanging data via a data interface. The APC unit 290 can be connected to the calculation unit 200 through a data interface. The APC unit may be configured to update the exposure parameter set in response to information received from the calculation unit 200.
For example, the APC unit 290 can comprise a controller unit running a program for conventional focus/dose control and comprising an interface for receiving at least one of: i) alternative parameter settings for determining improved focus/dose control parameters, and ii) improved focus/dose control parameters for overriding conventionally obtained parameters prior to passing the focus/dose control parameters to the exposure tool assembly 320.
The calculation unit 200 may be an additional device, e.g. another controller or an additional software module for a computer running a program other than the advanced process control in the APC unit 290, wherein the results obtained by the calculation unit 200 may affect the variation of the parameter settings of the APC unit 290, the replacement of focus/dose correction values in the APC unit 290, or may be transmitted directly to the exposure tool assembly 320. According to another embodiment, the APC unit 290 is one of several modules or stages integrated in the computing unit 200, wherein the computing unit 200 can completely replace the conventional APC unit 290.
The APC unit 290 can perform conventional ("loose") control of exposure dose and/or focus as long as the APC unit 290 does not receive other information, e.g. from the calculation unit 200 or from the user interface 205. In the case where the APC unit 290 receives enhanced correction data for exposure dose and defocus, the APC unit 290 forwards the enhanced correction data instead of the loose correction data. According to another embodiment, the APC unit 290 can receive an alternative parameter setting (e.g., a previous weight setting or a previous correction value for a previous CD) and override the previous parameter setting with the received alternative parameter setting.
The calculation unit 200 calculates an uncorrected CD of hypothetical structures in the resist pattern that would be formed in the resist pattern without any update to the exposure parameter set, and may transmit the uncorrected CD to the user interface 205 and/or the external expert system 206. Alternatively or additionally, the computing unit 200 may evaluate the uncorrected CD at an internal expert level.
The user, expert system 206, or an expert of computing unit 200 may correlate the uncorrected CD with the contextual information for the wafer and/or wafer lot, and may search for parameters in the wafer contextual information to obtain correlations between the corresponding parameters and the uncorrected CD values. If a correlation is found between the parameter in the wafer context information and the uncorrected CD value, the user, expert system 206, or expert reminder calculation unit 200 estimates an enhanced correction value based only on such previous exposures involving the same parameter in the wafer context information.
For example, if the user, expert system 206, or expert stage identifies that a certain CD trend of the parameters identifying a particular applicator unit is significantly different from the CD trends of other applicator units, the user, expert system 206, or expert stage may prompt the calculation unit 200 to determine an enhanced CD correction value using a different parameter setting (using only the exposure history from wafers processed at the same applicator unit).
The simulation stage of the calculation unit 200 may simulate the effect of different parameter settings on the CD before actually using the different parameter settings to determine the focus/dose correction values. The results of the simulation may be transmitted to the user interface 205 where the user may approve different parameter settings.
After approving the different parameter settings, the calculation unit 200 or the user can update the parameter settings in the APC unit 290. According to another embodiment, the calculation unit 200 may transmit the focus/dose correction values obtained with the new parameter settings directly to the exposure tool assembly 320, such that the (by-pass) APC unit 290 is bypassed.
From the measured CD and from the calculated exposure dose and/or defocus of the sample points on the wafer 401, a secondary stage of the calculation unit 200 may determine coefficients of the model for estimating the dose/focus in areas on the wafer 401 not directly covered by the sample points and/or for separating possible systematic parts from random parts. The model may be or may include a wafer level model describing the dose/focus distribution across the complete wafer surface according to one or more polynomials (e.g., odd and even Zernike (Zernike) polynomials, Legendre (Legendre) polynomials, and/or according to radial basis functions determined with TPS (thin plate spline) techniques).
The measured CD delivers values only at the sampling points. The modeling algorithm calculates the model coefficients, for example, for zernike polynomials or legendre polynomials that best match the base values (i.e., measured CD at the sampling points). By identifying all the model coefficients of the polynomial, the polynomial can be evaluated to estimate the dose/focus correction data for each point on the wafer surface.
The model may also include one or more models of a single exposure field (fine-field model) or a field model that summarizes multiple exposure fields of the wafer 401 (e.g., all exposure fields of the wafer 401).
The model provides dose/defocus for dense grid points across the complete wafer surface. The order of the secondary and primary stages may be changed and the two stages may be operated in parallel or one after the other.
The new setting (setting) may involve new model coefficients for estimating the relevant CD information of the exposure field. For example, the new settings may change the order of at least one of the model polynomials, e.g., from an nth order zernike polynomial to an (n-m) th or (n + m) th order zernike polynomial. The new settings may also change the model type, for example, from a model described by zernike polynomials to a legendre model. The effect of the new model may be simulated by means of the simulation stage of the calculation unit 200 and visualized on the user interface 205.
By calculating the uncorrected CD of hypothetical structures that would be formed on the same wafer without APC, better CD correction values can be searched for while the basic advanced process control of the exposure is still valid and the processed wafer 401 meets typical degrees of process tolerance. On the other hand, knowledge about uncorrected CDs allows, for example, to distinguish between different tools or chambers in which the wafer 401 is processed in parallel.
Uncorrected CDs can be analyzed using Exploratory Data Analysis (EDA), which can use statistical models, for example, to summarize their main characteristics visually.
Additional metrology unit 350 can measure the dimensions of critical substrate features (substrate CD). The calculation unit 200 may use at least one of the substrate CD and the resist CD as the measured CD.
According to an embodiment, the calculation unit 200 and the APC unit 290 of fig. 4 may cooperate to perform the advanced process control method illustrated in fig. 5, wherein each functional block in fig. 5 corresponds to a method step performed in one of the units depicted in fig. 4, e.g. as part of a program code executed in a controller or server.
The function blocks in the right column relate to the wafer examined at a certain point in time (the current wafer) and the current wafer data obtained from the current wafer and assigned to the current wafer. The current wafer data may include a current CD measurement at the predefined measurement site and data derived from the current CD measurement, e.g., current defocus data and error data. The current wafer data may include wafer context information related to the current wafer, information about defocus corrections and error corrections applied, and the like. The measurement site may be defined in a sampling plan.
The function blocks in the left column relate to previously processed and inspected wafers (history wafers) that were inspected prior to the current wafer and history wafer data obtained from and assigned to the history wafers. The historical wafer data may include historical CD measurements at predefined measurement sites as well as historical defocus data and dose data. The historical wafer data may further include wafer context information, such as information identifying the processing units that the wafer has been processed, and the processing conditions that the wafer has experienced.
The first step 710 stores and makes available the results of historical CD measurements at the measurement site and historical exposure data for a plurality of historical wafers. A second step 720 converts the historical CD measurements into exposure errors that describe the deviation of the CD measurements from the target CD in terms of defocus and dose errors. The second step 720 may use a polynomial model that relates CD deviation from the target value to defocus and dose errors that result in CD deviation. Defocus and dose error may be defocus only, may be dose error only, or may include both defocus and dose error. Defocus and dose error describe the residual defocus and dose error of the historical wafer.
The third step 730 calculates the effect of the historical process correction at the measurement site. The historical process corrections correspond to focus corrections and dose corrections actually applied to each historical wafer, and may form another example of uncorrected feature characteristics as discussed above.
For each CD measurement site (site) on the history wafer, a fourth step 740 adds the residual defocus and dose error determined in the second step 720 to the actual applied defocus and dose for the same history wafer to obtain the optimal focus and/or the optimal dose. The optimal focus and optimal dose are retrospectively obtained values: if an exposure has used the value in the past, the exposure will result in the smallest CD bias.
A fifth step 750 may determine coefficients for a model that provides optimal focus or optimal dose for dense grid points across the complete history wafer. According to an embodiment, fifth step 750 may provide coefficients for a first model that provides optimal focus for dense grid points across the complete history wafer and coefficients for a second model that provides optimal dose for dense grid points across the complete history wafer. Steps 710 through 750 may be repeated for a plurality of history wafers.
From the historical optimal focus value and the optimal dose value, a sixth step 760 calculates an alternative dose correction and error correction derived from only the historical data. The sixth step 760 may use an EWMA (exponentially weighted moving average) method to obtain the historical optimal focus value and the optimal dose value. The EWMA method may track exponentially weighted moving averages of historical best focus and/or best dose in time, wherein the method weights the historical best focus values and best dose values in geometrically descending order such that the closest best focus value and best dose value are weighted the highest, while the farthest sample contributes only very little.
For example, the sixth step 760 may be implemented by matching the weighted prediction error of the previous history wafer n with the optimal dose z of the previous history wafer nnSummed to predict the optimal dose z for the next wafer (which may be the current wafer)n+1Wherein the prediction error is the applied dose xnWith the optimum dose znThe difference, as given in equation (1):
(1)zn+1＝zn+λ(xn-zn)
equation (2) based on historically applied dose value x1…xnThe optimum dose z for the next wafer is describedn+1：
(2)zn+1＝λxn+(1-λ)λxn-1+...+(1-λ)n-1λx1+(1-λ)nx0
In equation (1), the weighting parameter λ satisfies the condition 0 ≦ λ ≦ 1, where for λ ≦ 0, the EWMA method takes the average x of the historical optimum dose values0. λ may take any value within a range between a lower limit and an upper limit, where, for example, the lower limit may be 0.05 or 0.1 and the upper limit may be 0.2 or 0.3. λ may be close to a lower limit when the sample values are noisy and may be close to an upper limit when the sample values (at least for a number of subsequent samples) approximate a definable function.
Alternatively or additionally, the sixth step 760 may predict the optimal focus value for the next wafer, or both.
The sixth step 760 may also use the historical wafer context information and the wafer context information of the current wafer to select only a subset of the historical wafers to determine the alternative dose correction values and the error correction values. For example, sixth step 760 may only consider such historical wafers processed at the same stage of the same exposure tool as the current wafer. From the predicted optimal focus and optimal dose, a sixth step predicts an alternative defocus correction and dose error correction for the next wafer.
The seventh step 810 makes available the results of the CD measurement at the measurement site of the current wafer n + 1. An eighth step 820 converts the current CD measurement into an exposure error that describes the deviation of the CD measurement from the target CD in terms of defocus and dose error. To obtain defocus and dose errors from CD measurement deviations from the target CD, the eighth step 820 may use the same polynomial model as the second step 720. Defocus and dose error describe the residual defocus and dose error of the current wafer.
Ninth step 830 calculates the effect of the prior process correction at the measurement site. The prior process corrections correspond to focus corrections and dose corrections actually applied to the current wafer.
For each measurement site on the current wafer, a tenth step 840 adds the residual defocus and dose error obtained in the eighth step 820 with the actual defocus and dose error of the current wafer obtained in the ninth step 830 to obtain an optimal focus correction and dose correction for the current wafer, wherein the optimal focus correction and dose correction are retrospectively obtained exposure parameters: if an exposure has used this optimal exposure parameter in the past, the exposure will result in the smallest CD bias.
The eleventh step 870 calculates the effect of the alternative focus correction and dose correction obtained at the measurement site of the current wafer in the sixth step 760.
A twelfth step 880 obtains an alternative focus error and dose error by calculating the difference between the effect of the alternative focus and dose corrections obtained from the historical wafer in the eleventh step 870 and the best dose and best focus obtained for the current wafer in the tenth step 840. A thirteenth step 890 may convert the alternative focus error and dose error to an alternative CD value.
Fig. 6 illustrates the embodiment of fig. 4 by way of example involving process deviations caused by the applicator unit. Line 601 connects the measured CD deviations Δ CD of n wafers and line 602 connects the uncorrected CD deviations Δ CD of these same wafers. The uncorrected CD bias can be assigned to three different context groups 611, 612, 613, where each context group includes a number of wafers. The uncorrected CD bias assigned to the wafer of the first context group 611 shows a correlation different from the correlations between the uncorrected CD biases of the other wafers.
The user, expert system, or expert stage of the computing unit 200 may search the wafer context information for the relevant wafers to identify a common context for the wafers of the first context group 611, a common context for the wafers of the second context group 612, and a common context for the wafers of the third context group 613. If a common context for the wafers of the first context group 611 can be identified, the calculation unit can be prompted to determine a correction value for the next wafer that includes the same parameters in the wafer context information based only on previous correction values for the wafers that refer to the first context group 611.
In fig. 7, the computing unit 200 as discussed above is in data connection with the main unit 910 of an EDA (electronic design automation) system. The main unit 910 may be a computer running on a computer system or server. The calculation unit 200 transmits information on the exposure performed by the exposure tool assembly to the main unit 910. The main unit 910 further receives layout information specifying the pattern to be imaged into the photoresist layer. By convolution of the layout data with the model of the exposure beam, the main unit 910 obtains information about the energy distribution in the exposed photoresist layer so that the main unit 910 can simulate the effect of certain exposure parameters, defocus and dose offset on the size of selected layout features.
Typically, the main unit 910 uses the maximum values of defocus and dose error to identify critical layout features. By using the actual defocus and dose errors available through the calculation unit 200, critical tests become more accurate and EDA can pass layout features that would otherwise be marked as critical.
Fig. 8 relates to an embodiment that uses the results of calculations performed by the computing unit 200 to enhance the accuracy and/or efficiency of the metrology unit 330.
The wafer fabrication module 300 includes at least the exposure tool assembly 320, the APC unit 290, the metrology unit 330, and the post-exposure processing unit 340 as described above.
The sampling plan 333 is transmitted to the metrology unit 330. The sampling plan 333 may include wafer identification information for identifying a particular wafer 401 in the wafer lot 410 and further include location information identifying metrology sites on the wafer 401 that are selected for inspection. The metering location may have a circular, elliptical or rectangular shape. The size of the metering location depends on the method of measurement. The diameter or edge length of the metering site may be about 100 μm for scatterometry methods and about 1 μm, or less than 1 μm for measurements using electron microscopy.
Metrology unit 330 examines wafer 401 and obtains characteristic features for the wafer 401 of interest at the metrology site identified in sampling plan 333. The characteristic features may include geometric dimensions such as height, width and/or length of structures on the surface of the wafer 401 within the measurement area, for example, width of a line or vertical extension of a step or trench, sidewall angle of a protrusion extending from the surface of the wafer 401, or sidewall angle of a trench extending into the surface of the wafer 401. Alternatively or additionally, the feature characteristics may contain information about the thickness and/or composition of the topmost layer of the cover wafer 401, or about other physical properties or characteristics, such as line edge roughness, line width roughness, cover data, wafer shape, wafer deformation, defect density, and information about the results of defects and electrical measurements.
At the first stage, the metrology unit 330 inspects the wafer 401 according to the original sampling plan using a first number of sample points and transmits the inspection results to the APC unit 290. The APC unit 290 receives the inspection result, calculates corrected exposure parameters, and transmits the corrected exposure parameters to the exposure tool assembly 320.
The calculation unit 200 may receive the inspection results and the corrected exposure parameters and simulate CDs of the characteristic features of the plurality of subsets of sample points. Further examples may compare actual deviations with measured CD values and may modify the sampling plan according to an optimal strategy.
For example, the calculation unit 200 may pass information describing the uncorrected values to the user interface 205 and the user modifies the sampling plan in response to the information presented to him at the user interface 205, wherein the modification is intended to omit sampling points that do not improve the system performance.
According to other embodiments, the calculation unit 200 may communicate information describing the uncorrected values to an expert system, or the calculation unit 200 may include an expert stage that modifies the sampling plan according to an optimal strategy without further user interaction.
For example, the calculation unit 200, expert system, or user may compare the actual deviation of the critical dimensions to the deviation if one or more of the sample points in the original sampling plan were omitted. In case the hypothetical deviation is equal to, smaller than or only slightly worse than the actual deviation, the calculation unit 200, the expert system or the user removes the sample point(s) in question from the sampling plan, so that at least the metrology unit 330 uses only the updated sampling plan 334.
According to an embodiment, the calculation unit 200 determines first model coefficients of the wafer model based on the original sampling plan and second model coefficients of the wafer model based on a proper subset of the sampling points of the original sampling plan. If the deviation between the first and second model coefficients is below a predefined threshold, the calculation unit 200 may be controlled to replace the original sampling plan with a new sampling plan comprising a proper subset of the sampling points. According to an embodiment, the calculation unit 200 may output information describing the first model coefficients and the second model coefficients.
For the next wafer 401, the metrology unit 330 uses fewer sample points without losing the quality of the APC. The further metrology unit 350 may use the updated sampling plan 334.
Fig. 9 relates to an embodiment relating to advanced process control for a patterning process (e.g., an etching process) as described above.
The wafer 401 coated with the patterned and developed photoresist layer is transferred to a post exposure processing unit 340. The processing unit 340 may comprise an etching tool that images a resist pattern into a wafer, e.g. into a base substrate and/or into a layer or layer stack deposited on a base substrate, wherein the substrate pattern is formed in the wafer 401.
In the substrate pattern, the CD, such as pattern depth, line width, tilt angle, line roughness, etc., depends on parameters of the etching process, such as etchant concentration, etching temperature, etching time, plasma voltage, and plasma frequency. A further metrology unit 350 obtains the CD of the substrate pattern at a predefined measurement site, which may be defined in the sampling plan.
The APC unit 290 can control one or more of the parameters of the etch process in a manner as described above for the focus and exposure dose of the exposure tool.
Fig. 10 relates to an embodiment of advanced process control effective for a combination of an exposure process and a post-exposure process (e.g., an etch process).
The defocus and exposure dose used in the exposure tool assembly 320 may be controlled in the manner as described with reference to fig. 2 to 5, provided that the calculation unit 200 uses the CD of the substrate pattern obtained at the further metrology unit 350 of the inspection wafer 401 after the post-exposure process. CD drift caused by fluctuations in etch parameters can be compensated for by appropriate settings in exposure tool assembly 320.

Claims (16)

1.一种先进工艺控制方法，包括：1. An advanced process control method, comprising: 使用曝光工具组件将涂覆半导体衬底的光致抗蚀剂层曝光于曝光束，其中，对于每次曝光，使用至少包括散焦值和曝光剂量的当前曝光参数集；exposing the semiconductor substrate-coated photoresist layer to an exposure beam using an exposure tool assembly, wherein, for each exposure, a current set of exposure parameters including at least a defocus value and an exposure dose is used; 对经曝光的光致抗蚀剂层进行显影以形成抗蚀剂图案；developing the exposed photoresist layer to form a resist pattern; 测量所述抗蚀剂图案的特征特性和/或由所述抗蚀剂图案得到的衬底图案的特征特性，并响应于所测得的特征特性与目标特征特性的偏差来更新所述当前曝光参数集；measuring features of the resist pattern and/or features of the substrate pattern derived from the resist pattern, and updating the current exposure in response to deviations of the measured features from target features parameter set; 估计在不更新所述曝光参数集的情况下形成的假想抗蚀剂图案的未经校正的特征特性；以及estimating uncorrected feature characteristics of a hypothetical resist pattern formed without updating the set of exposure parameters; and 以下操作中的至少一个：(i)响应于从所述未经校正的特征特性获得的信息来改变所述特征特性的测量策略，以及(ii)响应于从所述未经校正的特征特性获得的信息来更新所述当前曝光参数集。At least one of: (i) changing the measurement strategy of the characteristic in response to information obtained from the uncorrected characteristic, and (ii) in response to obtaining the information from the uncorrected characteristic information to update the current exposure parameter set. 2.如权利要求1所述的先进工艺控制方法，进一步包括：2. The advanced process control method of claim 1, further comprising: 使用所述曝光工具组件将涂覆半导体衬底的光致抗蚀剂层曝光于曝光束，其中，使用经更新的曝光参数集。The photoresist layer coating the semiconductor substrate is exposed to an exposure beam using the exposure tool assembly, wherein an updated set of exposure parameters is used. 3.如权利要求1所述的先进工艺控制方法，包括：3. The advanced process control method of claim 1, comprising: 响应于从所述未经校正的特征特性和从晶片上下文信息获得的信息来更新所述当前曝光参数集，其中，所述晶片上下文信息包含关于所述半导体衬底的工艺历史的信息。The current set of exposure parameters is updated in response to information obtained from the uncorrected feature characteristics and from wafer context information, wherein the wafer context information includes information about a process history of the semiconductor substrate. 4.如权利要求3所述的先进工艺控制方法，其中，4. The advanced process control method of claim 3, wherein, 更新所述当前曝光参数集仅考虑被分配到衬底组的半导体衬底，其中，被分配到所述衬底组的所述半导体衬底在所述晶片上下文信息中共享至少一个公共参数，并且其中，所述衬底组包括所述半导体衬底的真子集。updating the current exposure parameter set only considers semiconductor substrates assigned to a substrate group, wherein the semiconductor substrates assigned to the substrate group share at least one common parameter in the wafer context information, and Wherein, the set of substrates includes a proper subset of the semiconductor substrates. 5.如权利要求4所述的先进工艺控制方法，其中，5. The advanced process control method of claim 4, wherein, 被分配到所述衬底组的所述半导体衬底的未经校正的特征特性显示出与所有其他半导体衬底的未经校正的特征特性之间的相关性不同的相关性。The uncorrected characteristic characteristics of the semiconductor substrates assigned to the substrate group exhibit different correlations than the correlations between the uncorrected characteristic characteristics of all other semiconductor substrates. 6.如权利要求1所述的先进工艺控制方法，包括：6. The advanced process control method of claim 1, comprising: 通过修改采样计划来改变所述测量策略，所述采样计划包括关于所述半导体衬底的表面上的采样点的位置信息，其中，所述特征特性是在所述采样点处测量的。The measurement strategy is changed by modifying a sampling plan that includes positional information about sampling points on the surface of the semiconductor substrate at which the characteristic characteristic is measured. 7.如权利要求6所述的先进工艺控制方法，包括：7. The advanced process control method of claim 6, comprising: 基于包括第一数量的采样点的原始采样计划确定晶片模型的第一模型系数；determining first model coefficients of the wafer model based on the original sampling plan including the first number of sampling points; 基于所述采样点的真子集确定所述晶片模型的第二模型系数；以及determining second model coefficients of the wafer model based on the proper subset of the sample points; and 如果所述第一模型系数与所述第二模型系数之间的偏差低于预定义阈值，则用包括所述采样点的真子集的新采样计划代替所述原始采样计划。If the deviation between the first model coefficients and the second model coefficients is below a predefined threshold, the original sampling plan is replaced with a new sampling plan comprising a proper subset of the sampling points. 8.如权利要求1所述的先进工艺控制方法，其中，8. The advanced process control method of claim 1, wherein, 所述抗蚀剂图案和/或所述衬底图案包括多个抗蚀剂特征，并且所述特征特性包括以下至少一项：圆形抗蚀剂特征的直径、抗蚀剂特征的侧壁角度、抗蚀剂特征的高度尺寸、非圆形抗蚀剂特征的短轴长度、非圆形抗蚀剂特征的长轴长度、条形抗蚀剂特征的线宽、抗蚀剂特征之间的间隔宽度、抗蚀剂特征的面积、以及抗蚀剂特征的线边缘粗糙度。The resist pattern and/or the substrate pattern includes a plurality of resist features, and the feature characteristics include at least one of the following: diameters of circular resist features, sidewall angles of resist features , height dimension of resist features, short-axis length of non-circular resist features, long-axis length of non-circular resist features, line width of striped resist features, distance between resist features Space width, area of resist features, and line edge roughness of resist features. 9.一种晶片制造组件，包括：9. A wafer fabrication assembly comprising: 曝光工具组件(320)，所述曝光工具组件被配置为i)根据当前曝光参数集将涂覆半导体衬底的光致抗蚀剂层曝光于曝光束，以及ii)通过经曝光的光致抗蚀剂层形成抗蚀剂图案；An exposure tool assembly (320) configured to i) expose a semiconductor substrate-coated photoresist layer to an exposure beam according to a current set of exposure parameters, and ii) pass the exposed photoresist The etchant layer forms a resist pattern; 计量单元(330，350)，所述计量单元被配置为测量所述抗蚀剂图案和由所述抗蚀剂图案得到的衬底图案中的至少一者的特征特性；a metrology unit (330, 350) configured to measure a characteristic characteristic of at least one of the resist pattern and a substrate pattern derived from the resist pattern; 先进工艺控制(APC)单元(290)，所述APC单元被配置为响应于所测得的特征特性与目标特征特性的偏差来更新所述曝光参数集；以及an advanced process control (APC) unit (290) configured to update the set of exposure parameters in response to a deviation of the measured characteristic from a target characteristic; and 计算单元(200)，所述计算单元被配置为估计在不更新所述曝光参数集的情况下形成的假想抗蚀剂图案的未经校正的特征特性。A computing unit (200) configured to estimate uncorrected characteristic characteristics of an imaginary resist pattern formed without updating the exposure parameter set. 10.如权利要求9所述的晶片制造组件，其中，10. The wafer fabrication assembly of claim 9, wherein, 所述计算单元(200)被配置为响应于从所述未经校正的特征特性获得的信息来进行以下至少一项：(i)改变所述特征特性的测量策略，以及(ii)更新所述当前曝光参数集。The computing unit (200) is configured to, in response to information obtained from the uncorrected characteristic characteristic, at least one of: (i) change a measurement strategy for the characteristic characteristic, and (ii) update the characteristic characteristic The current exposure parameter set. 11.如权利要求10所述的晶片制造组件，其中，11. The wafer fabrication assembly of claim 10, wherein, 所述计算单元(200)被配置为：响应于从所述未经校正的特征特性和从晶片上下文信息获得的信息来更新所述当前曝光参数集，其中，所述晶片上下文信息包含关于所述半导体衬底的工艺历史的信息。The computing unit (200) is configured to update the current exposure parameter set in response to information obtained from the uncorrected feature characteristics and from wafer context information, wherein the wafer context information contains information about the Information on the process history of semiconductor substrates. 12.如权利要求11所述的晶片制造组件，其中，12. The wafer fabrication assembly of claim 11 wherein, 所述计算单元(200)被配置为：仅基于被分配到衬底组的半导体衬底来更新所述当前曝光参数集，其中，被分配到所述衬底组的所述半导体衬底在所述晶片上下文信息中共享至少一个公共参数，并且其中，所述衬底组包括所述半导体衬底的真子集。The computing unit (200) is configured to update the current exposure parameter set based only on the semiconductor substrates assigned to the substrate group, wherein the semiconductor substrates assigned to the substrate group are at least one common parameter is shared among the wafer context information, and wherein the substrate group includes a proper subset of the semiconductor substrates. 13.如权利要求12所述的晶片制造组件，其中，13. The wafer fabrication assembly of claim 12, wherein, 被分配到所述衬底组的所述半导体衬底的未经校正的特征特性显示出与所有半导体衬底的未经校正的特征特性之间的相关性不同的相关性。The uncorrected characteristic characteristics of the semiconductor substrates assigned to the substrate group exhibit different correlations than the correlations between the uncorrected characteristic characteristics of all semiconductor substrates. 14.如权利要求9所述的晶片制造组件，进一步包括：14. The wafer fabrication assembly of claim 9, further comprising: 数据接口，所述数据接口连接所述计算单元(200)和所述APC单元(290)，其中，所述APC单元(290)被配置为响应于从所述计算单元(200)接收的信息来更新所述曝光参数集。a data interface connecting the computing unit (200) and the APC unit (290), wherein the APC unit (290) is configured to respond to information received from the computing unit (200) Update the exposure parameter set. 15.如权利要求9所述的晶片制造组件，其中，15. The wafer fabrication assembly of claim 9, wherein: 所述计算单元(200)被配置为：基于包括第一数量的采样点的原始采样计划来确定晶片模型的第一模型系数，基于所述原始采样计划的所述采样点的真子集来确定所述晶片模型的第二模型系数，以及输出描述所述第一模型系数和所述第二模型系数的信息。The computing unit (200) is configured to determine first model coefficients of the wafer model based on an original sampling plan including a first number of sampling points, and to determine the first model coefficients of the wafer model based on a proper subset of the sampling points of the original sampling plan. second model coefficients of the wafer model, and outputting information describing the first model coefficients and the second model coefficients. 16.如权利要求9所述的晶片制造组件，其中，16. The wafer fabrication assembly of claim 9, wherein, 所述计算单元(200)被配置为：针对采样计划、自动化工艺控制和晶片模型中的至少一项的替代性设置，模拟假想抗蚀剂图案的未经校正的特征特性。The computing unit (200) is configured to simulate uncorrected characteristic characteristics of a hypothetical resist pattern for alternative settings of at least one of a sampling plan, automated process control, and a wafer model.
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