CN112311378B - Single-port mode selection circuit and multi-working mode integrated circuit - Google Patents
Single-port mode selection circuit and multi-working mode integrated circuit Download PDFInfo
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- CN112311378B CN112311378B CN201910969231.6A CN201910969231A CN112311378B CN 112311378 B CN112311378 B CN 112311378B CN 201910969231 A CN201910969231 A CN 201910969231A CN 112311378 B CN112311378 B CN 112311378B
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- H03—ELECTRONIC CIRCUITRY
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- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
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- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
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Abstract
本发明涉及集成电路领域，特别涉及用于工作模式选择的单端口模式选择电路及包含该电路的多工作模式集成电路。本发明引入了由恒流源、模式设定电阻RMODE、分压电阻网络、多路选择器、比较器和逻辑控制电路组成的控制回路，将由MODE引脚连接的外部不同的模式设定电阻RMODE产生的不同模式识别电压VMODE转换成译码器的输入数字码Q1Q2…Qn，不同的模式设定电阻RMODE对应不同的数字码Q1Q2…Qn，用来代替传统译码器结构的输入信号，有效降低端口数量，实现单端口模式选择，有效地节省PCB布板面积和减少外部器件数量，实现产品小型化和低成本。
The present invention relates to the field of integrated circuits, and in particular, to a single-port mode selection circuit for working mode selection and a multi-working mode integrated circuit including the same. The invention introduces a control loop composed of a constant current source, a mode setting resistor R MODE , a voltage dividing resistor network, a multiplexer, a comparator and a logic control circuit, and the external different mode setting resistors connected by the MODE pin are Different mode identification voltages V MODE generated by R MODE are converted into input digital codes Q 1 Q 2 ... Q n of the decoder, and different mode setting resistors R MODE correspond to different digital codes Q 1 Q 2 ... Q n , which are used to Instead of the input signal of the traditional decoder structure, it can effectively reduce the number of ports, realize single-port mode selection, effectively save the PCB layout area and reduce the number of external devices, and achieve product miniaturization and low cost.
Description
Technical Field
The present invention relates to the field of integrated circuits, and more particularly, to a single-port mode selection circuit for selecting a working mode and a multi-working mode integrated circuit including the same.
Background
The mode selection circuit is widely applied to integrated circuits with multiple working modes, and is mainly used for configuring the working modes of a chip through an external mode selection pin, for example, a monolithic integrated DC-DC converter is required to have a tracking mode and a non-tracking mode, each mode has different working frequency configurations, in order to meet different application environments, the external pin is required to configure the working modes of the chip, and the working modes can be more than eight, so the mode selection circuit is widely applied to the integrated circuits with the multi-mode working.
In order to flexibly configure the operation mode of the integrated circuit through the external pins, the conventional structure adopts a decoder mode to save the number of pins, and the mode selection circuit of the conventional decoder structure is shown in fig. 1. For a circuit with eight working modes, a three-eight decoder pair is generally adopted for realization, the three-eight decoder requires three pins for realizing mode selection, the packaging volume of a chip and the pin number of the chip are increased, the application cost is increased, if more modes need to be selected, more packaging pin expenses need to be increased to meet the requirements, and2 needs to be realizednThe working mode needs n configuration pins, is limited by the trend of miniaturization and low cost of the current portable product, and provides a new mode selection circuitThe requirement of (3) requires the number of external pins to be minimized to save the PCB layout area and the peripheral control cost, so that a new circuit structure needs to be adopted to replace the conventional decoder structure to reduce the number of package pins.
Disclosure of Invention
In view of the above, the main objective of the present invention is to minimize the number of ports required for mode selection of an integrated circuit, and to reduce the number of external ports, thereby saving the PCB layout area and reducing the number of external devices, and achieving miniaturization and low cost of products.
In order to achieve the above object, the present invention provides a single port mode selection circuit, which is characterized by comprising a constant current source, a comparator, a logic control circuit, a divider resistance network, a multiplexer and a decoder; the input of the constant current source circuit is connected with a reference voltage VREFThe output is connected with an external MODE setting resistor R through a MODE pinMODEIs connected to the positive input terminal of the comparator, and a mode setting resistor RMODEThe other end of the first and second electrodes is grounded; one end of the divider resistor network is connected with a reference voltage VREFThe other end of the voltage divider is connected with the ground, the voltage division values of the voltage division resistance network are respectively connected with the input end of the multi-path selector, and the output end of the multi-path selector is connected with the negative input end of the comparator; the output end of the comparator is connected with the holding control end of the logic control circuit, the clock signal CLK is connected with the CLK port of the logic control circuit, and the output signal of the logic control circuit is connected with the selection control end of the multiplexer and is simultaneously connected with the input end of the decoder;
during operation, the logic control circuit performs binary sequential counting under the control of a clock signal CLK, selects a voltage division value through the multiplexer in each clock period, and is connected with an external MODE setting resistor R connected with a MODE pinMODEThe generated pattern recognition voltage VMODEMaking a comparison at the comparator if VMODEThe comparator controls the logic control circuit to continue counting through the holding control end of the logic control circuit, if the mode identification voltage V is different from the selected voltage division valueMODEThe comparator controls the logic control circuit to keep the current count value through the holding control end of the logic control circuit, and the count value is decoded by the decoder to select the working mode.
The invention also provides a multi-working mode integrated circuit which is characterized in that the single-port mode selection circuit is adopted to select the working mode.
The single-port mode selection circuit has the advantages that compared with the traditional decoder circuit structure, the single-port mode selection circuit introduces the constant current source and the mode setting resistor RMODEA control loop consisting of a divider resistor network, a multiplexer, a comparator and a logic control circuit, and a MODE setting resistor R connected with the MODE pinMODEThe generated different pattern recognition voltages VMODEConversion to input digital code Q of decoder1、Q2……QnDifferent mode setting resistor RMODECorresponding to different digital codes Q1、Q2……QnThe decoder is used for replacing input signals of a traditional decoder structure, effectively reducing the number of ports, realizing single-port mode selection, effectively saving the PCB layout area, reducing the number of external devices and realizing product miniaturization and low cost.
Drawings
Fig. 1 is a schematic diagram of a conventional decoder structure mode selection circuit.
FIG. 2 is a schematic diagram of a single port mode selection circuit according to the present invention.
Fig. 3 is a schematic diagram of a constant current source circuit of the present invention.
Fig. 4 is a schematic diagram of a single-port eight-mode selection circuit according to an embodiment of the invention.
FIG. 5 is a diagram illustrating a mode state mapping of a single-port eight-mode selection circuit according to an embodiment of the present invention.
Detailed Description
A single-port mode selection circuit for integrated circuit operation mode selection and an integrated circuit including the same according to the present invention will be described in detail with reference to the accompanying drawings.
Fig. 2 shows a schematic diagram of the single port mode selection circuit of the present invention. As shown in the figure, the single-port mode selection circuit provided by the invention comprises a decoder, and a constant current source and a mode setting resistor RMODEA control loop consisting of a divider resistor network, a multiplexer, a comparator and a logic control circuit, and a setting resistor R for setting different external MODEs connected with the MODE pinMODEThe generated different pattern recognition voltages VMODEConversion to input digital code Q of decoder1Q2…QnDifferent mode setting resistor RMODECorresponding to different digital codes Q1Q2...QnThe method is used for replacing input signals of a traditional decoder structure, effectively reduces the number of ports, realizes single-port mode selection, and is a natural number more than or equal to 2.
The specific connection relationship of the single-port mode selection circuit is as follows: the input of the constant current source circuit is connected with a reference voltage VREFThe output is connected with an external MODE setting resistor R through a MODE pinMODEAnd is connected with the positive input end of the comparator, and one end of the divider resistor network is connected with a reference voltage VREFThe other end is connected with ground, the voltage division value of the voltage division resistance network is connected with the input end of the multiplexer, and the output end V of the multiplexerOThe negative input end of the comparator is connected, and the output end of the comparator is connected with the holding control end of the logic control circuit
The clock signal CLK is connected with the CLK port of the logic control circuit, and the output signal Q of the logic control circuit1Q2…QnThe selection control end of the multiplexer is connected, and the input end of the decoder is connected.
Fig. 3 is a schematic diagram of a constant current source circuit of the present invention. As shown in the figure, the constant current source comprises an error amplifier, an NMOS tube MN1, a PMOS tube MP1, a PMOS tube MP2 and a resistor R, and the reference voltage VREFThe positive input end of the error amplifier is connected, the output end of the error amplifier is connected with the grid electrode of an NMOS (N-channel metal oxide semiconductor) tube MN1, the source electrode of an NMOS tube MN1 is connected with a resistor R and the negative input end of the error amplifier, the drain electrode of an NMOS tube MN1 is connected with the grid electrode and the drain electrode of a PMOS tube MP1 and simultaneously connected with the grid electrode of a PMOS tube MP2, and the source electrodes of the PMOS tube MP1 and the PMOS tube MP2 are connected with a power supply voltage VINForming a current mirror structure, connecting the drain of the PMOS transistor MP2 with the MODE pin, the error amplifier andthe NMOS transistor MN1 forms a unit feedback control loop, and the voltage of the source end of the NMOS transistor MN1 is ensured to be equal to the reference voltage V through the feedback control loopREFThus, it can be determined that the current through R is VREFThe current is mirrored to the drain end of the PMOS tube MP2, namely a MODE port through a 1:1 current mirror consisting of the PMOS tube MP1 and the PMOS tube MP2, so that the output current of the constant current source can be determined to be IMODE＝VREF/R。
The voltage-dividing resistance network is composed of 2nThe equal resistors are connected in series to divide the voltage into 2nEqual parts of, wherein V1＝VREF/2n，V2＝2×VREF/2n，…，Vi＝i×VREF/2n…V2n＝2n×VREF/2n＝VREF。
The logic control circuit has two input ports, n output ports, the input ports are respectively clock input CLK and hold signal input
The output port is Q1、Q2…QnThe main function of the logic control circuit is that when the signal is kept, the n-bit digital code is output
At high level, output port data Q1Q2…QnGradually increasing in binary from the least significant bit (all 0) to the most significant bit (all 1) according to the number of clock cycles of the clock signal CLK while holding the signal
At low level, output port data Q1Q2…QnThe hold state is entered and no longer changes with the clock signal CLK. It is also contemplated that the circuit may be modified such that the logic control circuit performs a binary count by gradually decrementing the binary count when the logic control circuit enters the hold state when the hold signal is high.
The multiplexer has2nOne input signal, n bit selection control signal, 1 output signal VOThe main function that the multiplexer implements is to be 2nThe input signals are respectively connected with the output signal strobe V according to the decoding mode of the n-bit selection control signalOI.e. when Q1、Q2…QnWhen all 0 is set to V1And VOGating VO＝V1When Q is1、Q2…QnWhen all 1 is reached, V is2nAnd VOGating VO＝V2n。
The decoder has an n-bit input signal, 2nAn output signal, the decoder performing the main function of translating an n-bit input signal to 2nThe output control signals corresponding to each n-bit input signal are only one, namely D1, D2, … and D2 are output at each timenOnly one bit being active, i.e. when Q1、Q2…QnD1 is valid for all 0 s, and the remaining bits are all invalid when Q is equal1、Q2…QnTime D2 of all 1nValid, the remaining bits are all invalid.
Examples
Fig. 4 is a schematic diagram of a single-port eight-mode selection circuit according to an embodiment of the invention. As shown in the figure, the single-port mode selection circuit comprises a constant current source and a mode setting resistor R in an eight-mode selection circuitMODEA comparator, a three-bit output logic control circuit, an eight-equal-division resistor network, an eight-out-of-one multiplexer and a three-eight decoder, wherein the input of the constant current source circuit is connected with a reference voltage VREFThe output is connected with an external MODE setting resistor R through a MODE pinMODEAnd connected to the positive input end of the comparator, and an eight-equal-division resistor network consisting of resistors R1、R2、R3、R4、R5、R6、R7、R8Are connected in series, one end of the resistor network is connected with VREFThe other end is connected with the output end V of the voltage-dividing resistor network1、V2、V3、V4、V5、V6、V7、V8The input end of the one-out-of-eight selector is connected,output end V of one-out-of-eight selector0The negative input end of the comparator is connected, and the output end of the comparator is connected with the holding signal input end of the first-stage trigger D1
The positive output end Q1 AND the comparator output end of the first stage flip-flop D1 are respectively connected with two input ends of a first AND gate AND1, AND the output end of the first AND gate AND1 is connected with the holding signal input end of the second stage flip-flop D2
The positive output end Q2 AND the output end of the first AND gate AND1 of the second stage flip-flop D2 are respectively connected with two input ends of a second AND gate AND2, AND the output end of the second AND gate AND2 is connected with a holding signal input end of a third stage flip-flop D3
The D end of each stage of trigger is connected with the reverse output end
The terminals C l k of each stage of flip-flop are connected to a clock input signal CLK and a positive output terminal signal Q of the three-stage flip-flop1、Q2、Q3Respectively connected with the selection control end of the one-out-of-eight selector and the input end of the three-eight decoder.
The present embodiment employs a constant current source as shown in fig. 3.
The single-port eight-MODE selection circuit provided by the embodiment of the invention sets the resistor R by changing the MODE connected to the MODE portMODETo determine the working mode, the constant current source outputs a current IMODEFlow-through mode setting resistor RMODEGenerating a mode setting voltage VMODEMode setting voltage VMODE＝VREF/R*RMODEDue to IMODEConstant, so that the resistance R can be set by changing the peripheral modeMODETo set different pattern recognition voltages VMODE。
In the single-port eight-mode selection circuit of the embodiment of the invention, an eight-equal-division resistor network is composed of resistors R1、R2、R3、R4、R5、R6、R7、R8Are connected in series to form1＝R2＝R3＝R4＝R5＝R6＝R7＝R8The divider resistor network will divide VREFIs divided into V1、V2、V3、V4、V5、V6、V7、V8Eight different reference voltages, eight reference voltages obtained by voltage division are connected with the input end of an eight-to-one selector, and the eight-to-one selector enables the eight input reference voltages to be controlled according to three selection control signals Q1、Q2、Q3The decoding mode is respectively compared with the output end V of the one-out-of-eight selectorOGating, when Q1、Q2、Q3When is 000, V is1And VOStrobes, i.e. VO＝V1When Q is1、Q2、Q3When it is 100, V2And VOStrobes, i.e. VO＝V2And so on, when Q1、Q2、Q3When it is 111, V8And VOStrobing strobe, i.e. VO＝V8＝VREF。
The comparator circuit of the single-port eight-mode selection circuit of the embodiment of the invention sets the resistor R from the external modeMODESet pattern recognition voltage VMODEAnd one-out-of-eight selector based on control signal Q1、Q2、Q3Gated reference voltage VOThe comparison is carried out under the control of a logic control circuit consisting of D1, D2, D3, AND1 AND AND2, AND Q is obtained in the first clock cycle1、Q2、Q3An initial value of 000, i.e. VO＝V1If V isMODEGreater than V1If yes, the comparator output is high, the flip-flop D1 is in a trigger state, and the flip-flops D2 and D3 are in a hold state; second clock cycle, Q1、Q2、Q3Becomes 100, i.e. has VO＝V2If V isMODEIs still greater than V2Then the comparator output is still highFlip-flops D1 and D2 are in the on state, flip-flop D3 is in the hold state, and the third clock cycle, Q1、Q2、Q3To 010, i.e. having VO＝V3If V isMODEIs still greater than V3Then the comparator output remains high, flip-flop D1 is in the toggle state, flip-flops D2, D3 are in the hold state, and the fourth clock cycle, Q1、Q2、Q3Becomes 110, i.e. has VO＝V4If V isMODEIs still greater than V4Then the comparator output remains high, flip-flops D1, D2, D3 are all in the toggle state, and the fifth clock cycle, Q1、Q2、Q3Become 001, i.e. having VO＝V5If V isMODEIs still greater than V5Then the comparator output remains high, flip-flop D1 is in the toggle state, flip-flops D2, D3 are in the hold state, and the sixth clock cycle, Q1、Q2、Q3Becomes 101, i.e. has VO＝V6If V isMODEIs still greater than V6Then the comparator output remains high, flip-flops D1, D2 are in the toggle state, flip-flop D3 is in the hold state, and the seventh clock cycle, Q1、Q2、Q3Becomes 011, i.e. has VO＝V7If V isMODEIs still greater than V7Then the comparator output remains high, flip-flop D1 is toggle, flip-flops D2, D3 are hold, and the eighth clock cycle, Q1、Q2、Q3Becomes 111, i.e. has VO＝V8In the comparison process, if V appearsMODELess than VOThen the comparator output is low, flip-flops D1, D2, D3 enter hold state at the same time, Q1、Q2、Q3The output value no longer varies with the input clock, at which point Q1、Q2、Q3The output value is the control code corresponding to the working mode, and the mode identification voltage V is obtained by the comparator and the logic control circuitMODEAnd Q1、Q2、Q3Output digital code one-to-one correspondence, specific mode state correspondenceIs shown in FIG. 5, Q1、Q2、Q3And finally, converting the output value into eight specific working modes through a three-eight decoder, thereby realizing single-port eight-mode selection.
The single-port mode selection circuit can be integrated into an integrated circuit, so that the single-port mode selection of the integrated circuit with multiple working modes is realized.
The above embodiments show the specific implementation principle of the single-port eight-mode selection circuit in detail, and more embodiments based on the architecture, such as the single-port four-mode selection circuit, the single-port sixteen-mode selection circuit, and the single-port 2nThe mode selection circuit is within the scope of the present invention.
Claims (7)
1. A single-port mode selection circuit is characterized by comprising a constant current source, a comparator, a logic control circuit, a divider resistance network, a multiplexer and a decoder;
the input of the constant current source circuit is connected with a reference voltage VREFThe output is connected with an external MODE setting resistor R through a MODE pinMODEIs connected to the positive input terminal of the comparator, and a mode setting resistor RMODEThe other end of the first and second electrodes is grounded; one end of the divider resistor network is connected with a reference voltage VREFThe other end of the voltage divider resistor network is connected with the ground, the voltage division values of the voltage division resistor network are respectively connected with the input ends of the multi-path selectors, and the output ends of the multi-path selectors are connected with the negative input end of the comparator; the output end of the comparator is connected with the holding control end of the logic control circuit, the clock signal CLK is connected with the CLK port of the logic control circuit, and the output signal of the logic control circuit is connected with the selection control end of the multiplexer and is simultaneously connected with the input end of the decoder;
when the circuit works, the logic control circuit carries out binary sequential counting under the control of a clock signal CLK, each clock period selects a voltage division value through the multiplexer, and the logic control circuit is connected with an external MODE setting resistor R connected with a MODE pinMODEThe generated pattern recognition voltage VMODEMaking a comparison at the comparator if VMODEThe comparator is controlled by the holding control end of the logic control circuit, different from the selected voltage division valueMake it continue counting if VMODEThe comparator controls the logic control circuit to keep the current count value through the keeping control end of the logic control circuit, and the count value is decoded by the decoder to select the working mode.
2. The single-port mode selection circuit as claimed in claim 1, wherein the constant current source comprises an error amplifier, an NMOS transistor MN1, a PMOS transistor MP1, a PMOS transistor MP2 and a resistor R, a reference voltage VREFThe positive input end of the error amplifier is connected, the output end of the error amplifier is connected with the grid electrode of an NMOS (N-channel metal oxide semiconductor) tube MN1, the source electrode of the NMOS tube MN1 is connected with one end of a resistor R and the negative input end of the error amplifier, the other end of the resistor R is connected with the ground, the drain electrode of the NMOS tube MN1 is connected with the grid electrode and the drain electrode of a PMOS tube MP1 and the grid electrode of a PMOS tube MP2, and the source electrodes of the PMOS tube MP1 and the PMOS tube MP2 are connected with a power supply voltage VINAnd a current mirror structure is formed, and the drain of the PMOS pipe MP2 is connected with a MODE pin.
3. The single-port mode selection circuit of claim 1, wherein said voltage divider resistor network consists of 2nThe equal resistors are connected in series to divide the voltage into 2nEqually dividing; said multiplexer has 2nAn input signal, an n-bit selection control signal and1 output signal, the logic control circuit outputs the n-bit output signal as the n-bit selection control signal of the multiplexer and the n-bit input signal of the decoder, and the multiplexer selects 2 according to the n-bit selection control signal output by the logic control circuitnOne of the input signals is output; the decoder has an n-bit input signal and2nAn output signal, a decoder for decoding the n-bit input signal to 2nAn output mode control signal; n is a natural number of 2 or more.
4. The single-port mode selection circuit of claim 1, wherein the logic control circuit performs the binary count in binary increments or in binary decrements.
5. The single-port mode selection circuit of claim 3, wherein said voltage divider resistor network is formed by connecting 8 resistors in series, connecting VREFIs divided into V1、V2、V3、V4、V5、V6、V7、V8Eight different reference voltages; the multi-path selector is an eight-to-one selector, and eight reference voltages obtained by voltage division are connected with the input end of the eight-to-one selector; the eight-to-one selector selects one of the eight input reference voltages to output according to a 3-bit selection control signal output by the logic control circuit; the decoder is a three eight decoder.
6. The single-port mode selection circuit as claimed in claim 5, wherein the logic control circuit comprises three D flip-flops AND two AND gates, the output terminal of the comparator is connected to the holding signal input terminal of the first stage D flip-flop D1, the forward output terminal Q1 AND the comparator output terminal of the first stage D flip-flop D1 are respectively connected to the two input terminals of the first AND gate AND1, the output terminal of the first AND gate AND1 is connected to the holding signal input terminal of the second stage D flip-flop D2, the forward output terminal Q2 AND the output terminal of the first AND gate AND1 of the second stage D flip-flop D2 are respectively connected to the two input terminals of the second AND gate AND2, the output terminal of the second AND gate AND2 is connected to the holding signal input terminal of the third stage D flip-flop D3, AND D terminal of each stage flip-flop is connected to the reverse output terminal
The clock input end Clk of each stage of flip-flop is connected to a clock signal CLK, and the positive output end signals Q of the first, second and third stages of D flip-flops1、Q2、Q3The selection control end of the one-out-of-eight selector and the input end of the three-eight decoder are respectively connected.
7. A multi-operating-mode integrated circuit, characterized in that the operating mode selection is performed using the single-port mode selection circuit according to one of claims 1 to 6.
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