CN112310278A

CN112310278A - Variable resistive memory and method of manufacturing the same

Info

Publication number: CN112310278A
Application number: CN201910698899.1A
Authority: CN
Inventors: 白昌宗; 林铭哲; 刘奇青; 赵鹤轩; 郑嘉文
Original assignee: Winbond Electronics Corp
Current assignee: Winbond Electronics Corp
Priority date: 2019-07-31
Filing date: 2019-07-31
Publication date: 2021-02-02
Anticipated expiration: 2039-07-31
Also published as: CN112310278B

Abstract

The invention provides a variable resistance type memory and a manufacturing method thereof. The variable resistive memory includes: a lower electrode; a metal oxide layer formed on the lower electrode, wherein the metal oxide layer comprises a plurality of conductive wire regions, each conductive wire region has a bottom and a top, and the width of the bottom is greater than that of the top, wherein the conductive wire region comprises oxygen vacancies, and the region of the metal oxide layer outside the conductive wire region is a nitrogen-containing region; and a plurality of upper electrodes formed on the metal oxide layer and respectively corresponding to the conductive wire regions.

Description

Variable resistive memory and method of manufacturing the same

Technical Field

The present invention relates to a variable resistive memory, and more particularly, to a variable resistive memory capable of enhancing a local electric field.

Background

The variable Resistance Random Access Memory (RRAM) has the advantages of fast instruction cycle, low power consumption and the like, and is an ideal choice for the next generation of non-volatile memories. A Transition Metal Oxide (TMO) layer is disposed between the two metal electrodes in the variable resistance type, and the state of the conductive wire (filament) in the TMO layer is manipulated to electrically switch between a High Resistance State (HRS) and a Low Resistance State (LRS).

However, in the operation process of the variable resistive memory, since the conductive wires are sensitive to the surrounding environment, the formation and breaking control of the conductive wires are not easy, and the reliability of the variable resistive memory, such as the repeated read/write capability (endiance) and the memory retention (retentivity), is reduced.

Disclosure of Invention

According to an embodiment of the present invention, a variable resistive memory is provided. The variable resistive memory includes: a lower electrode; a metal oxide layer formed on the lower electrode, wherein the metal oxide layer comprises a plurality of conductive wire regions, each conductive wire region has a bottom and a top, and the width of the bottom is greater than that of the top; and a plurality of upper electrodes formed on the metal oxide layer and respectively corresponding to the conductive wire regions, wherein the bottom of each conductive wire region is adjacent to the lower electrode, and the top is adjacent to the upper electrode.

According to an embodiment of the present invention, a method for manufacturing a variable resistive memory is provided, including the steps of: providing a substrate; forming a plurality of trenches in the substrate; forming a plurality of lower electrodes in the grooves; forming a plurality of metal oxide layers on the lower electrode and surrounded by the lower electrode; performing a nitrogen ion process on the metal oxide layer to form a plurality of conductive wire areas and nitrogen-containing areas outside the conductive wire areas in the metal oxide layer; and forming a plurality of upper electrodes on the metal oxide layer.

The invention defines and limits the distribution area of the conductive wire (film) in the Transition Metal Oxide (TMO) layer (i.e. the conduction path formed by the migration of oxygen ions) through the related process of nitrogen ion implantation (e.g. ion implantation, plasma, annealing, etc.), and effectively enhances the local electric field in the component (i.e. the electric field in the conductive wire area). The variable resistance type memory (RRAM) with the specific conductive wire distribution pattern can effectively control the formation and the breakage of a single conductive wire, avoid the formation of multiple conductive wires, promote the memory to maintain the reliability thereof, such as good repeated read-write capability (end) and memory retention (retention), reduce the forming/operating voltage, and inhibit the fluctuation between a High Resistance State (HRS) and a Low Resistance State (LRS), so that the assembly can maintain a good operating window.

Drawings

Fig. 1 is a schematic cross-sectional view according to an embodiment of the present invention.

Fig. 2 is a schematic cross-sectional view according to an embodiment of the present invention.

Fig. 3 is a schematic cross-sectional view according to an embodiment of the present invention.

Fig. 4 is a schematic cross-sectional view according to an embodiment of the present invention.

Fig. 5 is a schematic cross-sectional view according to an embodiment of the invention.

Fig. 6A to 6H illustrate a manufacturing method according to an embodiment of the invention.

Fig. 7A to 7H illustrate a manufacturing method according to an embodiment of the invention.

Fig. 8A to 8I illustrate a manufacturing method according to an embodiment of the invention.

Reference numerals

10 variable resistive memory

10' variable resistive memory cell

12 substrate

14 (patterned) bottom electrode (layer)

14a, 14b, 14c lower electrode separation part

Major part of 14m lower electrode

Upper surface of main portion of 14m

14e extension of the lower electrode

16 (patterned) metal oxide layer

Bottom of 16' metal oxide layer

Side wall of 16' metal oxide layer

16a, 16b, 16c metal oxide layer separation

18 (patterned) upper electrode (layer)

68 through hole

22 conductive material

24-via gasket

26 conductive filament region

28 bottom of conductive filament area

30 top of the conductive filament region

32 area

34. 60, 74, 82 (patterned) covering layer

36 dielectric material layer

38 groove

40 bottom of the trench

42 side wall of trench

44 sidewalls of metal oxide layer

46. 56, 66, 70, 72, 76, 78, 80, 84 patterned photoresist layer

48N ion implantation process

50N ion plasma process

52 annealing process

54 hard mask layer

58 photo-etching process

62 first hard mask layer

64 second hard mask layer

Side wall of the upper electrode layer 86

A_BProjection area of bottom of conductive wire area to lower electrode

A_TProjected area of top of conductive wire area to lower electrode

W_BWidth of bottom of conductive filament area

W_TWidth of top of conductive filament area

Detailed Description

Referring to fig. 1, the variable resistive memory 10 includes a substrate 12, a lower electrode 14, a metal oxide layer 16, and a plurality of upper electrodes 18. A plurality of through holes (via) are formed in the substrate 12 and filled with a conductive materialAn electrical material 22. The conductive material 22 may comprise tungsten or copper, for example. A via liner (via liner)24 is further formed between the sidewall of the via and the conductive material 22. The via liner 24 may be formed of multiple layers of tantalum nitride/tantalum or titanium/titanium nitride. The lower electrode 14 is formed on the substrate 12 and electrically connected to the conductive material 22 in the substrate 12. The bottom electrode 14 is a continuous bottom electrode, that is, the bottom electrode 14 is formed on the substrate 12 entirely. The metal oxide layer 16 is formed on the bottom electrode 14 and is a continuous metal oxide layer, that is, the metal oxide layer 16 is formed on the bottom electrode 14 globally. It is noted that the metal oxide layer 16 includes a plurality of conductive filament regions 26 adjacent to each other, wherein each conductive filament region 26 has a bottom 28 and a top 30, and a width W of the bottom 28_BGreater than width W of the top 30_TIt can also be seen as the projected area A of the bottom 28 of the conductive filament region 26 to the lower electrode 14_BIs larger than the projection area A of the top part 30 to the lower electrode 14_T. In some embodiments, the width W of the bottom 28 of the conductive filament region 26_BWidth W of the top 30_TIn a ratio of about 1:1 to about 50: 1. In some embodiments, the bottoms 28 of two adjacent conductive filament regions 26 may or may not be substantially in contact. In addition, a plurality of upper electrodes 18 are formed on the metal oxide layer 16 separately from each other, respectively corresponding to the conductive wire regions 26. The bottom electrode 14 and the top electrode 18 may be made of titanium, titanium nitride, tantalum nitride, platinum, or gold, for example. In some embodiments, the metal oxide layer 16 may be formed of any suitable Transition Metal Oxide (TMO), such as hafnium oxide, titanium oxide, tantalum oxide, zirconium oxide, or nickel oxide. It is noted that, in the metal oxide layer 16, the region 32 outside the conductive filament region 26 is a nitrogen (ion) containing region corresponding to the region between two adjacent upper electrodes 18 above the conductive filament region. In some embodiments, the nitrogen-containing concentration of region 32 is approximately 1 × 10¹⁴-1×10¹⁶cm^-2. As shown in fig. 1, the bottom electrode 14, the metal oxide layer 16 (including the conductive filament region 26), and the top electrode 18 form a plurality of variable resistance memory cells 10'. That is, a plurality of mutually connected lower electrodes 14 and metal oxide layers 16 are formed on the substrate 12Followed by a variable resistance memory cell 10'.

The variable resistive memory 10 further includes a capping layer 34 formed on the metal oxide layer 16 and covering the upper electrode 18. In some embodiments, capping layer 34 may be formed of any suitable metal or metal oxide, such as aluminum oxide, hafnium, or tantalum oxide. The variable resistive memory 10 further includes a dielectric material layer 36 formed on the capping layer 34 and filling the area between the adjacent upper electrodes 18. In some embodiments, the dielectric material layer 36 may be made of silicon oxide, silicon nitride, or silicon oxynitride. In addition, the dielectric material layer 36 may be formed by, for example, high density plasma chemical vapor deposition (HDP-CVD).

Referring to fig. 2, the embodiment in the figure is different from the embodiment in fig. 1 in structure, and only the differences will be described below, and the description of the differences is omitted. In the present embodiment, the bottom electrode 14 includes a plurality of separated portions (14a, 14b, 14c) respectively formed on the substrate 12 and electrically connected to the through holes in the substrate 12. The metal oxide layer 16 includes a plurality of separated portions (16a, 16b, 16c) formed on the separated portions (14a, 14b, 14c) of the lower electrode 14, respectively. It is noted that each of the separated portions (16a, 16b, 16c) of the metal oxide layer 16 includes a conductive filament region 26. It is noted that in the metal oxide layer 16, the region 32 outside the conductive wire region 26 is a nitrogen (ion) containing region. In some embodiments, the nitrogen-containing concentration of region 32 is approximately 1 × 10¹⁴-1×10¹⁶cm^-2. As shown in fig. 2, a separate portion (14a, 14b, 14c) of the bottom electrode 14, a separate portion (16a, 16b, 16c) of the metal oxide layer 16 (including the conductive wire region 26), and a top electrode 18 form a variable resistance memory cell 10'. That is, a plurality of variable resistance memory cells 10' are formed on the substrate 12 to be separated from each other.

The variable resistive memory 10 further includes a capping layer (capping layer)34 formed on the substrate 12 and covering each of the variable resistive memory cells 10'. The variable resistance memory 10 further includes a dielectric material layer 36 formed on the capping layer 34 and filling the area between adjacent variable resistance memory cells 10'. As shown in fig. 2, adjacent variable resistance memory cells 10' are separated from each other by a layer of dielectric material 36.

Referring to fig. 3, the embodiment in the figure is different from the embodiment in fig. 1 in structure, and only the differences will be described below, and the description of the differences is omitted. In the present embodiment, the substrate 12 further includes a plurality of trenches 38 formed above the through holes and isolated from each other, and the trenches correspond to the through holes below the through holes respectively. The bottom electrode 14 includes a plurality of separated portions (14a, 14b, 14c) respectively formed in the trench 38 of the substrate 12, for example, respectively formed on the bottom 40 and the sidewall 42 of the trench 38, and respectively electrically connected to the via holes therebelow. The metal oxide layer 16 includes a plurality of isolation portions (16a, 16b, 16c) formed on the isolation portions (14a, 14b, 14c) of the lower electrode 14 in the trench 38 and surrounded by the isolation portions (14a, 14b, 14c) of the lower electrode 14. It is noted that each of the separated portions (16a, 16b, 16c) of the metal oxide layer 16 includes a conductive filament region 26. It is noted that in the metal oxide layer 16, the region 32 outside the conductive wire region 26 is a nitrogen (ion) containing region. In some embodiments, the nitrogen-containing concentration of region 32 is approximately 1 × 10¹⁴-1×10¹⁶cm^-2. As shown in fig. 3, a separate portion (14a, 14b, 14c) of the bottom electrode 14, a separate portion (16a, 16b, 16c) of the metal oxide layer 16 (including the conductive wire region 26), and a top electrode 18 form a variable resistance memory cell 10'. That is, a plurality of isolated variable resistance memory cells 10' are formed in the trench 38 of the substrate 12.

The variable resistive memory 10 further includes a capping layer 34 formed on the substrate 12, the lower electrode 14, and the metal oxide layer 16 and covering the upper electrode 18. The variable resistive memory 10 further includes a dielectric material layer 36 formed on the capping layer 34 and filling the area between the adjacent upper electrodes 18.

Referring to fig. 4, the embodiment in the figure is different from the embodiment in fig. 1 in structure, and only the differences will be described below, and the description of the differences is omitted. In the present embodiment, the lower electrode 14 includes a plurality of separated portions (14a, 14b, 14c) formed on the substrate, respectively12 and are electrically connected to the through holes in the substrate 12, respectively. The metal oxide layer 16 is formed on the bottom electrode 14 and is a continuous metal oxide layer, that is, the metal oxide layer 16 is formed on the substrate 12 and the bottom electrode 14 globally and covers the bottom electrode 14. Notably, the metal oxide layer 16 includes a plurality of conductive filament regions 26 separated from one another. It is noted that in the metal oxide layer 16, the region 32 outside the conductive wire region 26 is a nitrogen (ion) containing region. In some embodiments, the nitrogen-containing concentration of region 32 is approximately 1 × 10¹⁴-1×10¹⁶cm^-2. As shown in fig. 4, a separate portion (14a, 14b, 14c) of the bottom electrode 14, the metal oxide layer 16 (including the conductive wire region 26), and a top electrode 18 form a variable resistance memory cell 10'. That is, a plurality of variable resistance memory cells 10' connected to each other by a metal oxide layer 16 are formed on a substrate 12.

The variable resistive memory 10 further includes a capping layer 34 formed on the metal oxide layer 16 and covering the upper electrode 18. The variable resistive memory 10 further includes a dielectric material layer 36 formed on the capping layer 34 and filling the area between the adjacent upper electrodes 18.

Referring to fig. 5, the embodiment in the figure is different from the embodiment in fig. 1 in structure, and only the differences will be described below, and the descriptions of the differences are omitted. In the present embodiment, the bottom electrode 14 includes a plurality of separated portions (14a, 14b, 14c) respectively formed on the substrate 12 and electrically connected to the through holes in the substrate 12. The metal oxide layer 16 is formed on the bottom electrode 14 and is a continuous metal oxide layer, that is, the metal oxide layer 16 is formed on the substrate 12 and the bottom electrode 14 globally and covers the bottom electrode 14. Notably, the metal oxide layer 16 includes a plurality of conductive filament regions 26 separated from one another. It is noted that in the metal oxide layer 16, the region 32 outside the conductive wire region 26 is a nitrogen (ion) containing region. In some embodiments, the nitrogen-containing concentration of region 32 is approximately 1 × 10¹⁴-1×10¹⁶cm^-2. In addition, each top electrode 18 further includes sidewalls 44 that extend over the metal oxide layer 16. As shown in fig. 5, a separation of the lower electrode 14The portions (14a, 14b, 14c), the metal oxide layer 16 (including the conductive wire region 26), and an upper electrode 18 form a variable resistance memory cell 10'. That is, a plurality of variable resistance memory cells 10' connected to each other by a metal oxide layer 16 are formed on a substrate 12.

Referring to fig. 6A, which is a cross-sectional view illustrating a method for manufacturing a variable resistive memory according to an embodiment of the present invention, a substrate 12 is provided. A plurality of through holes are formed in the substrate 12. A conductive material 22 and a via liner 24 surrounding the conductive material 22 are formed within the via. The bottom electrode layer 14 and the metal oxide layer 16 are sequentially formed on the substrate 12.

Referring to fig. 6B, a patterned photoresist layer 46 is formed on the metal oxide layer 16. Thereafter, a nitrogen ion process, such as a nitrogen ion implantation (nitrogen ion implantation) process 48, is performed on the metal oxide layer 16 using the patterned photoresist layer 46 as a mask. In some embodiments, the implantation angle of the nitrogen ion implantation process 48 is between about 0 degrees and about 45 degrees, and the rotation angle is between about 45 degrees and about 90 degrees for 4-8 times. The implantation energy of the nitrogen ion implantation process 48 is approximately between 0.2keV and 1.0 keV. The implantation concentration of the nitrogen ion implantation process 48 is approximately 2 x 10¹⁵-1×10¹⁶In the meantime. In some embodiments, the implantation regions of different ranges may be obtained by adjusting parameters of the nitrogen ion implantation process 48, for example, by adjusting implantation energies (high, medium, and low) of the nitrogen ion implantation process 48, for example, when performing the implantation process with a high implantation energy, since most of the implanted nitrogen ions are located near the bottom of the metal oxide layer 16, the implantation region formed has a narrow-width-down (similar to a trapezoid), i.e., the wider the implantation region is, the closer the implantation region is, the lower the region is, the wider the region is, and the closer the region is, the higher the region is, the wider the region is, the more the region is, the upper the region is, the lower the region isThe narrower the width. When the implantation process is performed with implantation energy, most of the implanted nitrogen ions are located in the upper half of the metal oxide layer 16, so that the implantation region is formed in a shape of a narrow bottom and a wide top (similar to an inverted triangle shape), i.e., the narrower the region of the implantation region is, the closer the bottom of the metal oxide layer 16 is, the wider the region is, the closer the top of the metal oxide layer 16 is. When the implantation process is performed with low implantation energy, most of the implanted nitrogen ions are also located in the upper half of the metal oxide layer 16 but closer to the top of the metal oxide layer 16, so that the implantation region formed not only exhibits a narrow-bottom and wide-top pattern (similar to an inverted triangle pattern), but also is narrower in the implantation region formed with low implantation energy than in the implantation region formed with implantation energy, and is wider in the implantation region formed with low implantation energy. In some embodiments, nitrogen ions may also be implanted into the metal oxide layer 16 by other nitrogen ion processes, such as nitrogen ion plasma (nitrogen plasma) implantation of the metal oxide layer 16 by a nitrogen ion plasma (nitrogen plasma) process 50. In some embodiments, the RF power of the nitrogen plasma process 50 is between about 100 w and about 1000 w. In some embodiments, the nitrogen flow rate of the nitrogen ion plasma process 50 is approximately between 10 sccm and 300 sccm.

Referring to fig. 6C, an annealing process 52 is performed on the metal oxide layer 16 to form a plurality of conductive filament regions 26 and nitrogen (ion) -containing regions 32 outside the conductive filament regions 26 in the metal oxide layer 16. In some embodiments, the annealing temperature of the annealing process 52 is approximately between 200 degrees and 500 degrees. The nitrogen-containing region 32 may be defined by a nitrogen ion implantation process 48, i.e., the nitrogen-containing region 32 may be used to confine the conductive filament to a distribution region (conductive filament region 26) in the metal oxide layer 16.

Referring to fig. 6D, a capping layer 34, an upper electrode layer 18, and a hard mask layer 54 are sequentially formed on the metal oxide layer 16. Thereafter, a patterned photoresist layer 56 is formed on the hard mask layer 54. In some embodiments, the hard mask layer 54 may be made of silicon nitride, silicon carbonitride (SiCN), or silicon oxynitride.

Referring to fig. 6E, a photolithography and etching process 58 is then performed using the patterned photoresist layer 56 as a mask to form a stacked patterned cap layer 34 and a patterned top electrode layer (top electrode) 18, exposing a portion of the metal oxide layer 16. It is noted that the conductive filament regions 26 in the metal oxide layer 16 are very susceptible to damage during etching. In the present embodiment, since the exposed portion of the metal oxide layer is the region 32 and not the conductive wire region 26, the variable resistive memory manufactured by the method can further ensure the quality of the conductive wire region 26 in the metal oxide layer 16.

Referring to fig. 6F, a cap layer 60 is formed on the metal oxide layer 16 and covers the upper electrode 18. Thereafter, a dielectric material layer 36 is formed on the capping layer 60 and fills the region between the adjacent upper electrodes 18. At this point, the fabrication of the variable resistive memory 10 shown in fig. 1 is completed.

It is noted that the variable resistive memory 10 shown in fig. 1 includes a plurality of variable resistive memory cells 10' connected to each other by the lower electrode 14 and the metal oxide layer 16. The structural mode and the manufacturing method thereof can effectively avoid the damage of the side wall of the component in the etching process.

In some embodiments, the etching range of the photolithography process 58 may also be adjusted, for example, referring to fig. 6G, the lower electrode layer 14, the metal oxide layer 16, the capping layers (60, 34), and the upper electrode layer 18 are simultaneously etched to form a plurality of variable resistance memory cells 10' formed by a stack of the patterned lower electrode layer (lower electrode) 14, the patterned metal oxide layer 16, the patterned capping layer 34, and the patterned upper electrode layer (upper electrode) 18, exposing a portion of the substrate 12.

Referring to fig. 6H, a capping layer 60 is formed on the substrate 12 and covers the resistance variable memory cell 10'. Thereafter, a dielectric material layer 36 is formed on the capping layer 60 and fills the region between the adjacent variable resistance memory cells 10'. At this point, the fabrication of the variable resistive memory 10 shown in fig. 2 is completed.

It is noted that the variable resistive memory 10 shown in fig. 2 includes a plurality of variable resistive memory cells 10' formed on a substrate 12 and separated from each other. The structural pattern and the manufacturing method thereof can effectively avoid the mutual interference of the lower electrodes among different components.

Referring to fig. 7A, which is a cross-sectional view illustrating a method for manufacturing a variable resistive memory according to an embodiment of the present invention, a substrate 12 is provided. A plurality of through holes are formed in the substrate 12. A conductive material 22 and a via liner 24 surrounding the conductive material 22 are formed in the via. A first hard mask layer 62 is formed in the substrate 12 over the via. A second hard mask layer 64 is formed in the substrate 12 over the first hard mask layer 62. In some embodiments, the first hard mask layer 62 and the second hard mask layer 64 may be formed of any suitable silicide, such as silicon nitride, silicon carbon nitride (SiCN), or silicon oxynitride.

Referring to fig. 7B, a patterned photoresist layer 66 is then formed on the substrate 12. Then, the substrate 12 is etched to the second hard mask layer 64 by using the patterned photoresist layer 66 as a mask, so as to form a plurality of through holes (via)68 corresponding to the through holes therebelow.

Referring to FIG. 7C, patterned photoresist layer 66 is removed and patterned photoresist layer 70 is formed on substrate 12. Then, the substrate 12 is etched using the patterned photoresist layer 70 as a mask until the through holes are exposed, so as to form a plurality of trenches 38 corresponding to the through holes thereunder.

Referring to fig. 7D, the bottom electrode 14 is formed on the bottom 40 and the sidewall 42 of the trench 38, and is electrically connected to the via hole therebelow. Each lower electrode 14 includes a main portion 14m and an extension portion 14e, wherein the extension portion 14e extends from an upper surface 14 m' of the main portion 14m in a direction away from the through hole. The main portion 14m is formed on the bottom 40 and a portion of the sidewall 42 of the trench 38 and contacts the via hole therebelow, and the extension portion 14e is formed in a zigzag pattern extending on the sidewall 42 of the trench 38 except the main portion 14 m. Then, a metal oxide layer 16 is formed on the lower electrode 14 in the trench 38 and surrounded by the lower electrode 14. The metal oxide layer 16 is conformally formed on the lower electrode 14, i.e., the bottom 16' of the metal oxide layer 16 contacts the main portion 14m of the lower electrode 14, and the sidewall 16 ″ of the metal oxide layer 16 contacts the extension 14e of the lower electrode 14.

Referring to fig. 7E, a nitrogen ion process, such as a nitrogen ion implantation (implantation) process 48, is then performed on the left and right sides of the metal oxide layer 16. In some embodiments, the implantation angle of the nitrogen ion implantation process 48 is about 10 to 80 degrees, and the rotation angle is about 45 to 90 degrees for 4 to 8 times. In some embodiments, the implantation energy of the nitrogen ion implantation process 48 is approximately between 0.2keV and 10 keV. In some embodiments, the implantation concentration of the nitrogen ion implantation process 48 is approximately 1 × 10¹⁴-1×10¹⁶cm^-2In the meantime. In some embodiments, nitrogen ions may also be implanted into the metal oxide layer 16 by other nitrogen ion processes, such as nitrogen ion plasma (nitrogen plasma) implantation of the metal oxide layer 16 by a nitrogen ion plasma (nitrogen plasma) process 50. In some embodiments, the RF power of the nitrogen plasma process 50 is between about 100 w and about 1000 w. In some embodiments, the nitrogen flow rate of the nitrogen ion plasma process 50 is approximately between 10 sccm and 300 sccm. Then, an annealing process 52 is performed on the metal oxide layer 16 to form a conductive wire region 26 in the central region of the metal oxide layer 16 and nitrogen (ion) containing regions 32 outside the conductive wire region 26 on both sides of the metal oxide layer 16. In some embodiments, the annealing temperature of the annealing process 52 is approximately between 200 degrees and 500 degrees.

Referring to fig. 7F, a capping layer 34 and an upper electrode layer 18 are sequentially formed on the substrate 12, the lower electrode 14, and the metal oxide layer 16. Thereafter, a patterned photoresist layer 72 is formed on the upper electrode layer 18.

Referring to fig. 7G, the upper electrode layer 18 is then etched using the patterned photoresist layer 72 as a mask to form a patterned upper electrode layer (upper electrode) 18, exposing a portion of the substrate 12.

Referring to fig. 7H, a cap layer 74 is formed on the substrate 12, the bottom electrode 14, and the metal oxide layer 16, and covers the top electrode 18. Thereafter, a dielectric material layer 36 is formed on the capping layer 74 and fills the region between adjacent upper electrodes 18. At this point, the fabrication of the variable resistive memory 10 shown in fig. 3 is completed.

It is noted that the variable resistance memory 10 shown in fig. 3 includes a plurality of variable resistance memory cells 10' formed in the trench 38 of the substrate 12 and isolated from each other. The structural pattern and the manufacturing method thereof not only can effectively avoid the mutual interference of the lower electrodes among different components, but also can achieve the self-alignment effect through the arrangement of the through holes and the grooves.

Referring to fig. 8A, a cross-sectional view of a method for manufacturing a variable resistive memory according to an embodiment of the invention is shown, first, a substrate 12 is provided. A plurality of through holes are formed in the substrate 12. A conductive material 22 and a via liner 24 surrounding the conductive material 22 are formed in the via. The lower electrode layer 14 is formed on the substrate 12. A patterned photoresist layer 76 is formed on the lower electrode layer 14.

Referring to fig. 8B, the lower electrode layer 14 is then etched using the patterned photoresist layer 76 as a mask to form a patterned lower electrode layer (lower electrode) 14. Then, a metal oxide layer 16 is formed on the substrate 12 and the bottom electrode 14 globally, and covers the bottom electrode 14.

Referring to fig. 8C, a patterned photoresist layer 78 is then formed on the metal oxide layer 16. Thereafter, the metal oxide layer 16 is subjected to a nitrogen ion process, such as a nitrogen ion implantation (nitrogen ion implantation) process 48. In some embodiments, the implantation angle of the nitrogen ion implantation process 48 is between about 0 degrees and about 45 degrees, and the rotation angle is between about 45 degrees and about 90 degrees for 4-8 times. In some embodiments, the implantation energy of the nitrogen ion implantation process 48 is approximately between 0.2keV and 10 keV. In some embodiments, the implantation concentration of the nitrogen ion implantation process 48 is approximately 1 × 10¹⁴-1×10¹⁶cm^-2In the meantime. In some embodiments, nitrogen ions may also be implanted into the metal oxide layer 16 by other nitrogen ion processes, such as nitrogen ion plasma (nitrogen plasma) implantation of the metal oxide layer 16 by a nitrogen ion plasma (nitrogen plasma) process 50. In some embodiments, the RF power of the nitrogen plasma process 50 is between about 100 w and about 1000 w. In some embodiments, the nitrogen flow rate of the nitrogen ion plasma process 50 is approximately between 10 sccm and 300 sccm. Then, to metal oxygenThe layer 16 is annealed 52 to form a plurality of conductive filament regions 26 in the metal oxide layer 16 and nitrogen (ion) containing regions 32 outside the conductive filament regions 26. In some embodiments, the annealing temperature of the annealing process 52 is approximately between 200 degrees and 500 degrees.

Referring to fig. 8D, the patterned photoresist layer 78 is removed, and the capping layer 34 and the upper electrode layer 18 are sequentially formed on the metal oxide layer 16. Thereafter, a patterned photoresist layer 80 is formed on the upper electrode layer 18.

Referring to fig. 8E, the upper electrode layer 18 is then etched using the patterned photoresist layer 80 as a mask to form a patterned upper electrode layer (upper electrode) 18. Thereafter, the patterned photoresist layer 80 is removed.

Referring to fig. 8F, a capping layer 82 is then formed to cover the upper electrode 18. A layer of dielectric material 36 is then formed over the capping layers (34, 82) and fills the area between adjacent top electrodes 18. At this point, the fabrication of the variable resistive memory 10 shown in fig. 4 is completed.

It is noted that the variable resistive memory 10 shown in fig. 4 includes a plurality of variable resistive memory cells 10' connected to each other by metal oxide layers 16. The structural mode and the manufacturing method thereof can effectively avoid the damage of the side wall of the component in the etching process.

In some embodiments, the top electrode layer 18 may be etched with a different type of photomask layer, for example, referring to fig. 8G, forming a patterned photoresist layer 84 on the top electrode layer 18. It is noted that the patterned photoresist layer 84 further includes sidewalls 86 extending over the upper electrode layer 18.

Referring to fig. 8H, the upper electrode layer 18 is then etched using the patterned photoresist layer 84 as a mask to form a patterned upper electrode layer (upper electrode) 18. Then, the patterned photoresist layer 84 is removed. At this point, the upper electrode 18 is formed to extend over the sidewalls 44 of the metal oxide layer 16.

Referring to fig. 8I, a capping layer 82 is then formed to cover the upper electrode 18. A layer of dielectric material 36 is then formed over the capping layers (34, 82) and fills the area between adjacent top electrodes 18. At this point, the fabrication of the variable resistive memory 10 shown in fig. 5 is completed.

It is noted that the variable resistive memory 10 shown in fig. 5 includes a plurality of variable resistive memory cells 10' having upper electrodes 18 further extending to cover the sidewalls 44 of the metal oxide layer 16. The structural pattern and the manufacturing method thereof for increasing the size of the upper electrode can make the electric field on the side wall of the component more uniform.

The features of the above-described embodiments are helpful to those skilled in the art in understanding the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced above. It should also be understood by those skilled in the art that such equivalent substitutions may be made without departing from the spirit and scope of the present invention, and that changes, substitutions, or alterations may be made without departing from the spirit and scope of the present invention.

Claims

1. A variable resistive memory, comprising:

a lower electrode;

a metal oxide layer formed on the lower electrode, wherein the metal oxide layer comprises a plurality of conductive wire regions, each conductive wire region has a bottom and a top, and the width of the bottom is greater than that of the top, wherein the conductive wire region comprises oxygen vacancies, and the region of the metal oxide layer outside the conductive wire region comprises a nitrogen-containing region; and

and the upper electrodes are formed on the metal oxide layer and respectively correspond to the conductive wire areas.

2. The variable resistive memory of claim 1, wherein the metal oxide layer is a continuous metal oxide layer and the conductive wire regions are adjacent to each other.

3. The variable resistive memory of claim 1, wherein the lower electrode comprises a plurality of separated portions.

4. The variable resistive memory of claim 3, wherein the metal oxide layer comprises a plurality of separate portions, and each separate portion of the metal oxide layer comprises one of the conductive wire regions.

5. The variable resistive memory of claim 4, further comprising a substrate having a plurality of trenches, wherein the separated portions of the bottom electrode are formed in the trenches, respectively.

6. The variable resistive memory of claim 5, wherein each of the separated portions of the bottom electrode comprises a main portion and a plurality of extension portions extending from an upper surface of the main portion in a meander pattern.

7. The variable resistive memory of claim 6, wherein the separate portions of the metal oxide layer are formed on the main portion of the lower electrode and are surrounded by the extended portion of the lower electrode.

8. The resistance variable memory according to claim 3, wherein the metal oxide layer is a continuous metal oxide layer, and the metal oxide layer covers sidewalls of the separation portion of the bottom electrode.

9. The variable resistive memory of claim 3, wherein the metal oxide layer is a continuous metal oxide layer and the top electrode covers sidewalls of the metal oxide layer.

10. A method of manufacturing a variable resistive memory, the method comprising:

providing a substrate;

forming a plurality of trenches in the substrate;

forming a plurality of lower electrodes in the grooves;

forming a plurality of metal oxide layers on the lower electrode and surrounded by the lower electrode;

performing a nitrogen ion process on the metal oxide layer to form a plurality of conductive wire areas and nitrogen-containing areas outside the conductive wire areas in the metal oxide layer; and

and forming a plurality of upper electrodes on the metal oxide layer.

11. The method of claim 10, wherein the nitrogen ion implantation process comprises a nitrogen ion implantation process with an implantation angle of about 10 to 80 degrees and 4 to 8 rotations, each rotation angle being about 45 to 90 degrees.

12. The method as claimed in claim 10, further comprising performing an annealing process on the metal oxide layer after the nitrogen ion process.