CN112310072A - Semiconductor chip and intelligent power module - Google Patents

Abstract

The invention discloses a semiconductor chip, which comprises a first semiconductor layer, an insulating layer and a second semiconductor layer which are sequentially stacked; wherein a first electronic component is formed on the first semiconductor layer; forming a second electronic component on the second semiconductor layer; and a hollow area is arranged in the insulating layer below the second electronic component so as to isolate the electrical influence and/or the temperature influence of the first electronic component on the second electronic component.

Description

A semiconductor chip and intelligent power module

technical field

The present invention relates to the field of semiconductors, in particular to a semiconductor chip and an intelligent power module.

Background technique

IPM (Intelligent Power Module, intelligent power module) is widely used in AC motor frequency conversion speed regulation and DC motor chopper speed regulation and various high-performance power supplies, industrial electrical automation, new energy and other fields, and has a broad market application. IPM is an advanced power switching device, which is essentially a module that integrates power devices and their driving circuits; IPM plays an important role in the field of energy management that other integrated circuits cannot match, and device performance directly affects the utilization efficiency of energy systems.

The existing IPM usually contains a variety of electronic components, and each electronic component may require multiple pieces; therefore, the total number of electronic components in the IPM is large, the packaged module size is large, and the inductance effect is obvious. Improving the degree of integration has become one of the technical problems that need to be solved urgently at this stage.

SUMMARY OF THE INVENTION

In view of this, the main purpose of the present invention is to provide a semiconductor chip and an intelligent power module.

In order to achieve the above object, the technical scheme of the present invention is achieved in this way:

An embodiment of the present invention provides a semiconductor chip, including a first semiconductor layer, an insulating layer, and a second semiconductor layer stacked in sequence; wherein,

A first electronic component is formed on the first semiconductor layer;

A second electronic component is formed on the second semiconductor layer;

A void region is formed in the insulating layer below the second electronic component to isolate the electrical influence and/or temperature influence of the first electronic component on the second electronic component.

In the above solution, the thickness of the first semiconductor layer is greater than the thickness of the second semiconductor layer.

In the above solution, the first electronic component includes a power device, and the second electronic component includes a control device.

In the above solution, the power device includes an insulated gate bipolar transistor IGBT and/or a fast recovery diode FRD; the control device includes at least one of a micro-control unit MCU, a driver integrated circuit, a resistor, and a capacitor.

In the above solution, the insulating layer below the second electronic component has a cavity area, including:

A void region is formed in the insulating layer below the channel region of the second electronic component.

In the above solution, the cavity area is filled with nitrogen gas.

In the above solution, the semiconductor chip further has a through hole, and the first electronic component and the second electronic component are electrically connected through the through hole.

In the above solution, the insulating layer includes a first insulating layer and a second insulating layer, the first insulating layer is close to the first semiconductor layer, the second insulating layer is close to the second semiconductor layer, and the voids a region is located in the second insulating layer below the second electronic component;

The semiconductor chip further includes an isolation layer disposed between the first insulating layer and the second insulating layer; along the stacking direction, the vertical projection of the first electronic component and the vertical projection of the second electronic component At least covered by the isolation layer, the isolation layer is connected to the first preset potential to isolate the electrical interference between the first electronic component and the second electronic component.

In the above solution, the isolation layer is a semiconductor layer.

Embodiments of the present invention further provide an intelligent power module IPM, including at least one semiconductor chip according to any one of the above solutions.

In the semiconductor chip and the intelligent power module provided by the embodiments of the present invention, the electrical influence and/or temperature influence of the first electronic component on the second electronic component is isolated by the isolation area, thereby realizing the separation of the first electronic component and the second electronic component. The second electronic component is integrated into the two semiconductor layers of a semiconductor chip, which not only improves the integration of the semiconductor chip, reduces the number of semiconductor chips in the intelligent power module, but also realizes the full utilization of the semiconductor layer, and achieves The effective layered processing simplifies the circuit layout, reduces the inductance effect, and ensures the stability of each electronic component in the semiconductor chip.

Description of drawings

1 is a schematic cross-sectional view of a semiconductor chip provided by an embodiment of the present invention;

2 is a schematic cross-sectional view of a semiconductor chip provided by another embodiment of the present invention;

FIG. 3 is a schematic structural diagram of an intelligent power module provided by an embodiment of the present invention.

Detailed ways

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention may be embodied in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that the present invention will be more thoroughly understood, and will fully convey the scope of the present disclosure to those skilled in the art.

In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced without one or more of these details. In other instances, some technical features that are well known in the art have not been described in order to avoid obscuring the present invention; that is, not all features of an actual embodiment are described herein, and well-known functions and constructions are not described in detail.

In the drawings, the sizes of layers, regions, elements, and their relative sizes may be exaggerated for clarity. The same reference numbers refer to the same elements throughout.

It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on the other elements or layers , adjacent thereto, connected or coupled to other elements or layers, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention. The discussion of a second element, component, region, layer or section does not imply that the first element, component, region, layer or section is necessarily present of the invention.

Spatial relational terms such as "under", "below", "under", "under", "above", "above", etc., are used herein for convenience Description is used to describe the relationship of one element or feature to other elements or features shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation shown in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "below" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a," "an," and "the/the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. It should also be understood that the terms "compose" and/or "include", when used in this specification, identify the presence of stated features, integers, steps, operations, elements and/or components, but do not exclude one or more other The presence or addition of features, integers, steps, operations, elements, parts and/or groups. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

For a thorough understanding of the present invention, detailed steps and detailed structures will be presented in the following description in order to explain the technical solution of the present invention. Preferred embodiments of the present invention are described in detail below, however, the present invention may have other embodiments in addition to these detailed descriptions.

Embodiments of the present invention provide a semiconductor chip. 1 is a schematic cross-sectional view of a semiconductor chip provided by an embodiment of the present invention. As shown in the figure, the semiconductor chip includes a first semiconductor layer 110, an insulating layer 120, and a second semiconductor layer 130 stacked in sequence; A first electronic component (not shown in the figure) is formed on the first semiconductor layer 110 ; a second electronic component 131 is formed on the second semiconductor layer 130 ; The insulating layer 120 has a void region 121 to isolate the electrical influence and/or temperature influence of the first electronic component on the second electronic component 131 .

Here, the first semiconductor layer 110, the insulating layer 120, and the second semiconductor layer 130 constitute a SOI (Silicon On Insulator, silicon on insulator) structure; further, SON (Silicon On Nothing, voids) is used. In the SOI structure, a cavity region 121 is formed in the insulating layer 120, and the second electronic component is isolated from the first electronic component by the cavity, which effectively inhibits the effect of the first electronic component on the second electronic component. The electrical influence and/or temperature influence of the components, so as to realize the integration of the first electronic component and the second electronic component on the two semiconductor layers of a semiconductor chip, which not only improves the integration degree of the semiconductor chip, but also reduces the The number of semiconductor chips in the intelligent power module is increased, and the full utilization of the semiconductor layer is realized, effective layered processing is achieved, the circuit layout is simplified, the inductance effect is reduced, and the stability of the electronic components in the semiconductor chip is guaranteed. sex.

It can be understood that the semiconductor chip structure provided in the embodiments of the present invention is easier to implement than a single SON. In a specific embodiment, on the one hand, a first semiconductor layer 110 is provided first, and an insulating layer 120 is formed on the first semiconductor layer 110; the insulating layer 120 is etched to form a cavity region 121; The second semiconductor layer 130 is formed, for example, on a temporary support substrate; then, the two are bonded together, that is, the side of the second semiconductor layer 130 facing away from the temporary support substrate is The exposed surfaces of the insulating layer 120 on the first semiconductor layer 110 are bonded together to form the structure of the semiconductor chip shown in FIG. 1 . In addition, the step of removing the temporary support substrate may also be included. The first electronic component and the second electronic component may be respectively formed on the first semiconductor layer 110 and the second semiconductor layer 130 before bonding, or may be formed on the first semiconductor layer 110 and the second semiconductor layer 130 after bonding. After the SOI structure is formed, it is formed on the first semiconductor layer 110 and the second semiconductor layer 130 .

In a specific embodiment, the first semiconductor layer 110 and the second semiconductor layer 130 may be silicon layers, that is, two wafers. The insulating layer 120 may be a buried oxide layer, such as a SiO ₂ layer.

In a specific embodiment, the thickness of the first semiconductor layer 110 is greater than the thickness of the second semiconductor layer 130 . At this time, the first semiconductor layer 110 can be used as a substrate to play a role of mechanical support; the quality of the first semiconductor layer 110 needs to meet the quality requirements for manufacturing components; the second semiconductor layer 130 can be thinned Floor.

As shown in FIG. 1 , the second electronic component 131 only occupies a partial area on the second semiconductor layer 130 , and other areas on the second semiconductor layer 130 except the second electronic component 131 also It may include structures such as through silicon vias, oxide layers, and the like. The first electronic component may also only occupy a partial area on the first semiconductor layer 110 ; the first electronic component may be located on the first semiconductor layer 110 at the position of the second electronic component 131 . Directly below, it may also be located below the side of the second electronic component 131 .

In a specific embodiment, the semiconductor chip further has a through hole, and the first electronic component and the second electronic component 131 are electrically connected through the through hole. In this way, the problem of poor reliability of wire connection is avoided, the structure size is reduced, and the possibility of integrating more complex functions is provided.

In a specific embodiment, the first electronic component includes a power device, and the second electronic component 131 includes a control device.

Further, the power device includes, for example, IGBT (Insulated Gate Bipolar Transistor, insulated gate bipolar transistor) and/or FRD (Fast Recovery Diode, fast recovery diode). When the power device includes an IGBT and an FRD, the IGBT and the FRD form the power device in the form of, for example, an RC-IGBT (Reverse Conducting-IGBT, reverse conducting insulated gate bipolar transistor). When the first electronic component includes an IGBT/RC-IGBT, the IGBT/RC-IGBT is a vertical structure; that is, the collector (anode) of the IGBT/RC-IGBT is located on the side of the first semiconductor layer 110 . On the lower surface (the surface facing away from the second semiconductor layer 130 ), the gate electrode and the emitter electrode (cathode) are located under the insulating layer 120 and are led out by through holes.

The control device includes, for example, at least one of an MCU (Micro-controller Unit, micro-control unit), a driving integrated circuit, a resistor, and a capacitor. In some embodiments, the driver integrated circuit is a single-channel driver IC. The resistors and capacitors are formed on the second semiconductor layer 130 as required, and the forming steps thereof may be compatible with the fabrication processes of other devices (eg, devices such as driver integrated circuits) on the second semiconductor layer 130 .

In a specific embodiment, the insulating layer 120 under the second electronic component 131 has a cavity region 121 , including: all the holes under the channel region 1311 of the second electronic component 131 . The insulating layer 120 has a cavity region 121 therein. In this way, the key parts of the circuit transistors in the second electronic component 131 are isolated from the first semiconductor layer 110 by the void region 121 , thereby effectively suppressing the influence of the first semiconductor layer 110 on the chip circuit portion. In the second electronic component 131 , a cavity region is also preferably formed in the insulating layer 120 below the elements such as resistors and capacitors.

In a specific embodiment, the second electronic component 131 includes a transistor element; the transistor element is formed by a fully depleted MOSFET process; each element is isolated by an oxide layer, and there is no Latch Up effect (latch up effect). ), fast switching speed, low power consumption and good temperature tolerance. In this way, the driving integrated circuit portion of the second electronic component 131 in this embodiment can achieve better driving capability.

In a specific embodiment, the cavity region 121 is filled with nitrogen gas. In other embodiments, the hollow area 121 may also be filled with air; in this case, the air needs to be dried to remove the water vapor therein. It can be understood that filling nitrogen gas in the cavity region 121 is more conducive to compatibility with other fabrication processes of the chip, and thus is easier to implement.

Next, please refer to Figure 2. 2 shows a schematic cross-sectional view of a semiconductor chip provided by another embodiment of the present invention. As shown in the figure, in this embodiment, the insulating layer 120 includes a first insulating layer 1201 and a second insulating layer 1202. The first insulating layer 1201 is close to the first semiconductor layer 110 , the second insulating layer 1202 is close to the second semiconductor layer 130 , and the void region 121 is located at the second place below the second electronic component 131 . In the insulating layer 1202; the semiconductor chip further includes an isolation layer 140 disposed between the first insulating layer 1201 and the second insulating layer 1202; along the stacking direction, the vertical projection of the first electronic component is the same as the The vertical projection of the second electronic component 131 is at least covered by the isolation layer 140 , and the isolation layer 140 is connected to a first preset potential to isolate the first electronic component and the second electronic component 131 electrical interference.

In this way, the electrical isolation effect between the first electronic component and the second electronic component is further enhanced, and it provides for integrating the first electronic component and the second electronic component on the two semiconductor layers of a semiconductor chip. more stable and reliable formation conditions.

The first insulating layer 1201 and the second insulating layer 1202 may both be buried oxide layers, for example, both are SiO ₂ layers. The thicknesses of the first insulating layer 1201 and the second insulating layer 1202 are in the range of 200-400 nm; in some embodiments, the first insulating layer 1201 and the second insulating layer 1202 have the same thickness; in In other embodiments, the thickness of the first insulating layer 1201 is greater than the thickness of the second insulating layer 1202 to improve the voltage resistance of the device.

The isolation layer 140 may be a semiconductor layer. In one embodiment, the isolation layer 140 may be the same as the material of the first semiconductor layer 110 and/or the material of the second semiconductor layer 130 . The isolation layer 140 is, for example, a silicon layer.

In some embodiments, the isolation layer 140 contains dopant ions, so as to improve the conductivity and improve the isolation effect.

The thickness of the isolation layer 140 is in the range of 40-200 nm.

The isolation layer 140 is connected to a first preset potential to form an electrostatic shield between the first electronic component and the second electronic component 131 . The first preset potential is 0 volts, for example, the isolation layer 140 is AC grounded; in addition, the isolation layer 140 can also be connected to other controllable potentials, which can be adjusted within the withstand voltage range in principle.

In addition, an embodiment of the present invention further provides an IPM, where the IPM includes at least one semiconductor chip described in any one of the foregoing embodiments.

3 is a schematic cross-sectional view of an IPM provided by an embodiment of the present invention. As shown in the figure, the IPM further includes a lead frame 200, and the lead frame 200 has an upper bridge chip mounting position 220 and a lower bridge chip mounting position 210, so The semiconductor chip 100 is mounted on at least one of the upper bridge chip mounting position 220 and the lower bridge chip mounting position 210 ; the semiconductor chip 100 is the semiconductor chip described in any one of the above embodiments of the present invention.

In one embodiment, the IPM is a 6-channel three-phase drive IPM; by integrating 6 semiconductor chips 100 described in any one of the above embodiments of the present invention, it is equivalent to integrating 6 IGBT chips and 6 FRD chips and the corresponding drive circuit.

The upper bridge chip mounting positions 220 and the lower bridge chip mounting positions 210 may respectively have three, that is, a total of six chip mounting positions; all or part of the six chip mounting positions are installed with any one of the embodiments of the present invention. the semiconductor chip.

The IPM provided by the embodiment of the present invention is applied to, for example, an inverter air conditioner.

In this way, the smart power module provided by the embodiment of the present invention includes at least one semiconductor chip according to the embodiment of the present invention, which improves the integration degree of the smart power module and reduces the size of the module; The chip provides electrical connection, and the layout is simple and convenient; after packaging, the overall size of the module is small and the stability is strong.

It should be noted that, the technical features in the technical solutions described in the embodiments of the present invention may be combined arbitrarily if there is no conflict.

The above are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention. Any modifications, equivalent replacements and improvements made within the spirit and principles of the present invention shall be included in the within the protection scope of the present invention.

Claims (10)

1. A semiconductor chip, characterized in that it comprises a first semiconductor layer, an insulating layer, and a second semiconductor layer stacked in sequence; wherein, A first electronic component is formed on the first semiconductor layer; A second electronic component is formed on the second semiconductor layer; A void region is formed in the insulating layer below the second electronic component to isolate the electrical influence and/or temperature influence of the first electronic component on the second electronic component. 2 . The semiconductor chip of claim 1 , wherein the thickness of the first semiconductor layer is greater than the thickness of the second semiconductor layer. 3 . 3 . The semiconductor chip of claim 1 , wherein the first electronic component includes a power device, and the second electronic component includes a control device. 4 . 4. The semiconductor chip according to claim 3, wherein the power device comprises an insulated gate bipolar transistor IGBT and/or a fast recovery diode FRD; the control device comprises a micro-control unit MCU, a driver integrated circuit, At least one of resistance and capacitance. 5 . The semiconductor chip according to claim 1 , wherein the insulating layer under the second electronic component has a cavity region, comprising: 5 . A void region is formed in the insulating layer below the channel region of the second electronic component. 6 . The semiconductor chip of claim 1 , wherein the cavity region is filled with nitrogen gas. 7 . 7 . The semiconductor chip according to claim 1 , wherein the semiconductor chip further has through holes, and the through holes are electrically connected between the first electronic component and the second electronic component. 8 . connect. 8. The semiconductor chip of claim 1, wherein the insulating layer comprises a first insulating layer and a second insulating layer, the first insulating layer is close to the first semiconductor layer, and the second insulating layer The layer is close to the second semiconductor layer, and the void region is located in the second insulating layer below the second electronic component; The semiconductor chip further includes an isolation layer disposed between the first insulating layer and the second insulating layer; along the stacking direction, the vertical projection of the first electronic component and the vertical projection of the second electronic component At least covered by the isolation layer, the isolation layer is connected to the first preset potential to isolate the electrical interference between the first electronic component and the second electronic component. 9. The semiconductor chip of claim 8, wherein the isolation layer is a semiconductor layer. 10 . An intelligent power module IPM, characterized by comprising at least one semiconductor chip according to any one of claims 1 to 9 .

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