CN112309872A - Packaging process of multi-chip module - Google Patents
Packaging process of multi-chip module Download PDFInfo
- Publication number
- CN112309872A CN112309872A CN201910692565.3A CN201910692565A CN112309872A CN 112309872 A CN112309872 A CN 112309872A CN 201910692565 A CN201910692565 A CN 201910692565A CN 112309872 A CN112309872 A CN 112309872A
- Authority
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- China
- Prior art keywords
- protective cover
- hole
- lead frame
- chip module
- cavity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
本发明公开了一种多芯片模块的封装工艺，包括：将晶片附着在引线框架上；将设有空腔的保护盖设置贯穿的通孔，将设置有贯穿的通孔的保护盖经在引线框架的周边的胶加温密封在引线框架上；在加温的流程中通过通孔降低腔内的压力，使其不变形，并在降温后填塞通孔。可以使得保护盖的密闭保护效果更佳，由于除去了保护盖密封腔内的大量介质，可以大大增加射频功放产品的功率和效率，此外还可以增加射频功放产品的散热效果，同时产品的一致性更好。
The invention discloses a packaging process for a multi-chip module, which includes: attaching a chip on a lead frame; setting a protective cover provided with a cavity with a through hole, and placing the protective cover provided with the through hole on a lead The glue on the periphery of the frame is heated and sealed on the lead frame; in the heating process, the pressure in the cavity is reduced through the through hole to make it not deformed, and the through hole is filled after cooling. It can make the sealing protection effect of the protective cover better. Since a large amount of medium in the sealing cavity of the protective cover is removed, the power and efficiency of the RF power amplifier product can be greatly increased, and the heat dissipation effect of the RF power amplifier product can also be increased, and the consistency of the product can be increased. better.
Description
Technical Field
The invention relates to a packaging process of a multi-chip module, in particular to a packaging process of a protective cover of the multi-chip module.
Background
In order to solve the problems of low integration level and incomplete functions of single chip packaging, a plurality of chips with high integration level, high performance and high reliability are combined into various electronic module systems on a high-density multilayer interconnection substrate, so that the multi-chip module system is developed. A plurality of bare IC chips are mounted on a multi-layer high-density interconnection substrate and assembled in the same package.
The multi-chip module has the following characteristics: the packaging density is higher, and the electrical performance is better, and the volume is littleer with equivalent single-chip encapsulation. If the traditional single chip packaging mode is adopted and respectively welded on a printed circuit board, the signal transmission delay caused by the wiring between the chips is very serious, especially in a high-frequency circuit, and the packaging has the greatest advantage of shortening the wiring length between the chips, thereby achieving the purposes of shortening the delay time and easily realizing the high speed of a module.
Accordingly, conventional MCM integrated circuit package structures are typically produced using one level packaging. The primary package refers to a single chip package or a package in which multiple chips are mounted on a metal lead frame, the chips are mounted on the lead frame through silver paste, and a protective cover is fixed on the lead frame in order to protect internal circuit structures from entering impurities and avoid mechanical scratches or high temperature damage, for example, a multi-chip module package structure disclosed in chinese patent CN 108074885. The traditional assembly process of the protective cover is an integrally formed all-plastic package. However, the integrally formed all-plastic package often has a medium inside, and the medium may affect the lead and the chip, and further affect the power of the rf power amplifier product.
Disclosure of Invention
In view of the above-mentioned technical problems, an object of the present invention is to provide a multi-chip module packaging process, which can make the sealing protection effect of the protection cover better, and can greatly increase the power and efficiency of the rf power amplifier product and increase the heat dissipation effect of the rf power amplifier product due to the removal of a large amount of media in the sealing cavity of the protection cover.
In order to solve the problems in the prior art, the technical scheme provided by the invention is as follows:
a packaging process of a multi-chip module comprises the following steps:
s01: attaching a die to the lead frame;
s02: arranging a through hole in the protective cover provided with the cavity, and sealing the protective cover provided with the through hole at the edge of the lead frame;
s03: and exhausting air in the sealed cavity through the through hole and filling the through hole.
In a preferred embodiment, in step S01, the die and the lead frame are connected by wire bonding.
In a preferred embodiment, the step S02 of sealing the protective cover with the through hole on the edge of the lead frame includes adhering glue on the edge of the upper surface of the lead frame, adhering the protective cover with the through hole on the edge of the lead frame through the glue, and heating to seal the protective cover on the lead frame.
In a preferred technical solution, the method for exhausting the air in the sealed cavity in the step S03 includes heating the product obtained in the step S02 at 100-200 ℃ for 15-45 min.
Compared with the scheme in the prior art, the invention has the advantages that:
1. the invention can make the airtight protection effect of the protective cover better, because a large amount of media in the sealed cavity of the protective cover are removed, the influence of the media on the wafer and the lead wire is greatly reduced, thereby reducing the parasitic capacitance and the parasitic inductance, and greatly increasing the consistency of indexes of the radio frequency power amplifier product such as power, efficiency and the like and the product. In addition, the heat dissipation space can be optimized, and the heat dissipation effect of the radio frequency power amplifier product is improved.
2. The lead frame is a pure metal base, and can effectively dissipate heat.
3. The glue is attached to the edge of the lead frame, and is suitable for mass production. The protective cover with the cavity cannot extrude the position of the lead, and the consistency of the product is better.
Drawings
The invention is further described with reference to the following figures and examples:
FIG. 1 is a flow chart of a multi-chip module packaging process of the present invention;
FIG. 2 is a block diagram of a process flow for packaging a multi-chip module according to the present invention.
Detailed Description
The above-described scheme is further illustrated below with reference to specific examples. It should be understood that these examples are for illustrative purposes and are not intended to limit the scope of the present invention. The conditions used in the examples may be further adjusted according to the conditions of the particular manufacturer, and the conditions not specified are generally the conditions in routine experiments.
Example (b):
as shown in fig. 1 and 2, a multi-chip module packaging process includes the following steps:
s01: attaching a die to the lead frame;
s02: arranging a through hole in the protective cover provided with the cavity, and sealing the protective cover provided with the through hole at the edge of the lead frame;
s03: the hot air in the sealed cavity is exhausted through the through hole and the through hole is filled.
In step S01, the die 1 is firmly soldered to the base of the lead frame 2 by the metal solder, and then heated and cured, and then the surface of the die pad is plasma etched, and then the die 1 and the lead frame 2 are bonded by the wire 5. The wafers may also be coated after the bond attachment by a coating dispenser 7.
The through holes 4 penetrating through the protective cover 3 with the cavities are formed, the through holes 4 are preferably one and can be arranged at the upper portions of the upper surface or the two side faces, the protective cover 3 is provided with the cavities, the positions of leads can be prevented from being extruded, the lead can be extruded when the lead is packaged in a traditional all-plastic packaging integrated structure, and the leads can be extruded when the lead is packaged, so that the leads are dislocated to influence the consistency of products.
The size of the protective cover 3 corresponds to the size of the lead frame 1. Dispensing 6 is carried out on the edge of the upper surface of the lead frame 1 by using a dispenser, the glue can be epoxy resin or other glue, and the protective cover provided with the through hole 4 is attached to the edge of the lead frame by the glue. Then placing into an oven for heating at 150 deg.C for 30 min. The heating temperature can be 100-. Of course, the method of exhausting air may be vacuum pumping or the like. The heating method of the oven is preferentially adopted, so that the process steps can be saved.
And then, filling the through holes after cooling, marking unqualified products, and sawing the products produced in batch to obtain qualified products.
And finally, testing the qualified product, wherein the testing comprises direct current testing, S parameter testing and the like, and the final product is obtained after the testing is passed.
It is to be understood that the above-described embodiments of the present invention are merely illustrative of or explaining the principles of the invention and are not to be construed as limiting the invention. Therefore, any modification, equivalent replacement, improvement and the like made without departing from the spirit and scope of the present invention should be included in the protection scope of the present invention. Further, it is intended that the appended claims cover all such variations and modifications as fall within the scope and boundaries of the appended claims or the equivalents of such scope and boundaries.
Claims (4)
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910692565.3A CN112309872A (en) | 2019-07-30 | 2019-07-30 | Packaging process of multi-chip module |
| PCT/CN2020/099850 WO2021017744A1 (en) | 2019-07-30 | 2020-07-02 | Packaging process for multi-chip module |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910692565.3A CN112309872A (en) | 2019-07-30 | 2019-07-30 | Packaging process of multi-chip module |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN112309872A true CN112309872A (en) | 2021-02-02 |
Family
ID=74229393
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910692565.3A Pending CN112309872A (en) | 2019-07-30 | 2019-07-30 | Packaging process of multi-chip module |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN112309872A (en) |
| WO (1) | WO2021017744A1 (en) |
Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5992551A (en) * | 1982-11-19 | 1984-05-28 | Hitachi Ltd | Package for semiconductor device |
| US6291263B1 (en) * | 2000-06-13 | 2001-09-18 | Siliconware Precision Industries Co., Ltd. | Method of fabricating an integrated circuit package having a core-hollowed encapsulation body |
| JP2002118126A (en) * | 2000-10-06 | 2002-04-19 | Sony Corp | Curing device and curing method |
| US20020130398A1 (en) * | 2000-05-19 | 2002-09-19 | Siliconware Precision Industries Co., Ltd. | Semiconductor package which has no resinous flash formed on lead frame and method for manufacturing the same |
| US20030045024A1 (en) * | 2001-09-03 | 2003-03-06 | Tadanori Shimoto | Interconnecting substrate for carrying semiconductor device, method of producing thereof and package of semiconductor device |
| US7732914B1 (en) * | 2002-09-03 | 2010-06-08 | Mclellan Neil | Cavity-type integrated circuit package |
| CN201829476U (en) * | 2010-06-22 | 2011-05-11 | 宇芯（成都）集成电路封装测试有限公司 | Straight-side metal cover semiconductor package |
| JP2013110492A (en) * | 2011-11-18 | 2013-06-06 | Seiko Epson Corp | Package for electronic device, electronic device, electronic apparatus, and manufacturing method of electronic device |
| CN103700635A (en) * | 2013-12-25 | 2014-04-02 | 北京必创科技有限公司 | Chip packaging structure with cavity and packaging method thereof |
| CN104934380A (en) * | 2015-05-11 | 2015-09-23 | 清华大学 | Chip packaging structure |
| CN108074885A (en) * | 2016-11-10 | 2018-05-25 | 北京万应科技有限公司 | A kind of multi-chip module encapsulating structure |
| KR20180100792A (en) * | 2017-03-02 | 2018-09-12 | 앰코 테크놀로지 인코포레이티드 | Cavity sensor package having plugged vent hole and method for manufacturing the same |
| CN108962762A (en) * | 2018-07-13 | 2018-12-07 | 江苏长电科技股份有限公司 | Monomer bimetallic plates encapsulating structure and its packaging method |
-
2019
- 2019-07-30 CN CN201910692565.3A patent/CN112309872A/en active Pending
-
2020
- 2020-07-02 WO PCT/CN2020/099850 patent/WO2021017744A1/en active Application Filing
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5992551A (en) * | 1982-11-19 | 1984-05-28 | Hitachi Ltd | Package for semiconductor device |
| US20020130398A1 (en) * | 2000-05-19 | 2002-09-19 | Siliconware Precision Industries Co., Ltd. | Semiconductor package which has no resinous flash formed on lead frame and method for manufacturing the same |
| US6291263B1 (en) * | 2000-06-13 | 2001-09-18 | Siliconware Precision Industries Co., Ltd. | Method of fabricating an integrated circuit package having a core-hollowed encapsulation body |
| JP2002118126A (en) * | 2000-10-06 | 2002-04-19 | Sony Corp | Curing device and curing method |
| US20030045024A1 (en) * | 2001-09-03 | 2003-03-06 | Tadanori Shimoto | Interconnecting substrate for carrying semiconductor device, method of producing thereof and package of semiconductor device |
| US7732914B1 (en) * | 2002-09-03 | 2010-06-08 | Mclellan Neil | Cavity-type integrated circuit package |
| CN201829476U (en) * | 2010-06-22 | 2011-05-11 | 宇芯（成都）集成电路封装测试有限公司 | Straight-side metal cover semiconductor package |
| JP2013110492A (en) * | 2011-11-18 | 2013-06-06 | Seiko Epson Corp | Package for electronic device, electronic device, electronic apparatus, and manufacturing method of electronic device |
| CN103700635A (en) * | 2013-12-25 | 2014-04-02 | 北京必创科技有限公司 | Chip packaging structure with cavity and packaging method thereof |
| CN104934380A (en) * | 2015-05-11 | 2015-09-23 | 清华大学 | Chip packaging structure |
| CN108074885A (en) * | 2016-11-10 | 2018-05-25 | 北京万应科技有限公司 | A kind of multi-chip module encapsulating structure |
| KR20180100792A (en) * | 2017-03-02 | 2018-09-12 | 앰코 테크놀로지 인코포레이티드 | Cavity sensor package having plugged vent hole and method for manufacturing the same |
| CN108962762A (en) * | 2018-07-13 | 2018-12-07 | 江苏长电科技股份有限公司 | Monomer bimetallic plates encapsulating structure and its packaging method |
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| Publication number | Publication date |
|---|---|
| WO2021017744A1 (en) | 2021-02-04 |
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Application publication date: 20210202 |
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