CN112289793A

CN112289793A - Semiconductor device for battery protection

Info

Publication number: CN112289793A
Application number: CN202010963596.0A
Authority: CN
Inventors: 周号
Original assignee: Zhuhai Maiju Microelectronics Co Ltd
Current assignee: Zhuhai Maiju Microelectronics Co Ltd
Priority date: 2020-09-14
Filing date: 2020-09-14
Publication date: 2021-01-29
Also published as: CN216054706U; CN113725217A; CN113725217B

Abstract

The present disclosure provides a semiconductor device, comprising: a first cell region, in which a first field effect transistor is formed; a second cell region, in which a second field effect transistor is formed, and a second cell region The field effect transistor is used as a first switch, and the first switch is used to control the connection and disconnection between the source electrode of the first field effect transistor and the substrate; and a third cell area, the third cell area is formed with a second switch , the second switch is used to control the connection and disconnection between the gate and the drain of the first field effect transistor; wherein, the first cell region, the second cell region and the third cell region are formed in sequence, and the second cell region is formed in turn. The cell region is formed between the first cell region and the third cell region.

Description

Semiconductor device for battery protection

Technical Field

The present disclosure belongs to the field of semiconductor technology, and particularly relates to a semiconductor device for battery protection.

Background

In the battery system, overcharge and overdischarge of the battery not only reduce the lifespan of the battery, but also cause safety accidents of explosion and fire when serious. The battery is, for example, a lithium battery pack or the like.

In the prior art, a device for protecting a battery in a battery system often cannot completely turn off a charging current or a discharging circuit under the condition of overcharge or overdischarge of the battery, so that potential safety hazards exist.

Disclosure of Invention

In order to solve one of the above technical problems, the present disclosure provides a semiconductor device for battery protection.

The semiconductor device for battery protection of the present disclosure is realized by the following technical solutions.

The semiconductor device of the present disclosure includes: a first cell region having a first field effect transistor formed therein; the second cell area is provided with a second field effect transistor which is used as a first switch, and the first switch is used for controlling the connection and disconnection between the source electrode of the first field effect transistor and the substrate; the third cell area is provided with a second switch, and the second switch is used for controlling the connection and disconnection between the grid electrode and the drain electrode of the first field effect transistor; the first cell area, the second cell area and the third cell area are formed in sequence, and the second cell area is formed between the first cell area and the third cell area.

According to the semiconductor device of at least one embodiment of the present disclosure, the first cell region includes a source region, a substrate electrode region, a gate region, and a drain region, the first cell region has a first parasitic diode and a second parasitic diode formed therein, the first parasitic diode and the second parasitic diode constitute an anti-series structure, the first parasitic diode and the second parasitic diode are formed between the source region and the drain region, and a junction region of the first parasitic diode and the second parasitic diode formed in the first cell region is formed at least on the substrate electrode region.

According to the semiconductor device of at least one embodiment of the present disclosure, the second cell region includes a source region, a substrate electrode region, a gate region, and a drain region, the second cell region forms a second field effect transistor having a fourth parasitic diode (D4) formed between the source region and the substrate electrode region of the second field effect transistor.

According to the semiconductor device of at least one embodiment of the present disclosure, the third cell region includes a gate region and a drain region, a third parasitic diode and a resistor are formed between the drain region and the gate region of the third cell region, and the third parasitic diode and the resistor constitute a series structure.

According to a semiconductor device of at least one embodiment of the present disclosure, a substrate is shared by a first cell region, a second cell region, and a third cell region.

According to the semiconductor device of at least one embodiment of the present disclosure, the first field effect transistor is an NMOS transistor; the first unit cell region comprises a source region, a substrate electrode region, a gate region and a drain region, and the substrate electrode region comprises a first substrate electrode region and a second substrate electrode region; the first unit cell region comprises a P-type substrate and a dielectric layer, at least an N-type drift region is formed between the P-type substrate and the dielectric layer, a P-type well region is formed in the N-type drift region, at least a first P-type high doping region is formed in the P-type well region, a second P-type high doping region is formed in the P-type substrate, the first substrate electrode region is formed in the dielectric layer, the first substrate electrode region is contacted with the first P-type high doping region, the second substrate electrode region is formed on the dielectric layer, at least one part of the second substrate electrode region passes through the dielectric layer to be contacted with the second P-type high doping region, the P-type well region is separated from the P-type substrate through the N-type drift region, an N-type well region is formed in the P-type well region, a first N-type high doping region is formed in the N-type well region, the first N-type high doping region is separated from the P-type well region through the N-type well region, a second N-type high doping region is, at least one part of the source region penetrates through the dielectric layer to be in contact with the first N-type high-doping region, the drain region is formed on the dielectric layer, at least one part of the drain region penetrates through the dielectric layer to be in contact with the second N-type high-doping region, and the gate region is formed in the dielectric layer.

According to the semiconductor device of at least one embodiment of the present disclosure, the first field effect transistor is an NMOS transistor; the first unit cell region comprises a source region, a substrate electrode region, a gate region and a drain region, and the substrate electrode region comprises a first substrate electrode region and a second substrate electrode region; the first unit cell region comprises a P-type substrate and a dielectric layer, at least an N-type drift region is formed between the P-type substrate and the dielectric layer, a P-type well region is formed in the N-type drift region, at least a first P-type high doping region is formed in the P-type well region, a second P-type high doping region is formed in the P-type substrate, the first substrate electrode region is formed in the dielectric layer, the first substrate electrode region is contacted with the first P-type high doping region, the second substrate electrode region is formed on the dielectric layer, at least one part of the second substrate electrode region passes through the dielectric layer to be contacted with the second P-type high doping region, the P-type well region is separated from the P-type substrate through the N-type drift region, an N-type well region is formed in the P-type well region, a first N-type high doping region is formed in the N-type well region, the first N-type high doping region is separated from the P-type well region through the N-type well region, a second N-type high doping region is, at least one part of the source region penetrates through the dielectric layer to be contacted with the first N-type high-doping region, the drain region is formed on the dielectric layer, at least one part of the drain region penetrates through the dielectric layer to be contacted with the second N-type high-doping region, the gate region is formed in the dielectric layer, a first isolation medium is formed between at least one part of the gate region and at least one part of the first N-type high-doping region, and a first isolation medium is also formed between at least the other part of the gate region and at least one part of the second N-type high-doping region.

According to the semiconductor device of at least one embodiment of the present disclosure, the first field effect transistor is an NMOS transistor; the first unit cell region comprises a source region, a substrate electrode region, a gate region and a drain region, and the substrate electrode region comprises a first substrate electrode region and a second substrate electrode region; the first unit cell region comprises a P-type substrate and a dielectric layer, at least an N-type drift region is formed between the P-type substrate and the dielectric layer, a P-type well region is formed in the N-type drift region, at least a first P-type high doping region is formed in the P-type well region, a second P-type high doping region is formed in the P-type substrate, the first substrate electrode region is formed in the dielectric layer, the first substrate electrode region is contacted with the first P-type high doping region, the second substrate electrode region is formed on the dielectric layer, at least one part of the second substrate electrode region passes through the dielectric layer to be contacted with the second P-type high doping region, the P-type well region is separated from the P-type substrate through the N-type drift region, an N-type well region is formed in the P-type well region, a first N-type high doping region is formed in the N-type well region, the first N-type high doping region is separated from the P-type well region through the N-type well region, a second N-type high doping region is, at least one part of the source region penetrates through the dielectric layer to be contacted with the first N-type high-doping region, the drain region is formed on the dielectric layer, at least one part of the drain region penetrates through the dielectric layer to be contacted with the second N-type high-doping region, the gate region is formed in the dielectric layer, a second isolation medium is formed at least between the first P-type high-doping region and the second P-type high-doping region, and a second isolation medium is also formed at the outer side of the second N-type high-doping region and between the dielectric layer and the P-type substrate.

According to the semiconductor device of at least one embodiment of the present disclosure, the first field effect transistor is an NMOS transistor; the first unit cell region comprises a source region, a substrate electrode region, a gate region and a drain region, and the substrate electrode region comprises a first substrate electrode region and a second substrate electrode region; the first unit cell region comprises a P-type substrate and a dielectric layer, at least an N-type drift region is formed between the P-type substrate and the dielectric layer, a P-type well region is formed in the N-type drift region, at least a first P-type high doping region is formed in the P-type well region, a second P-type high doping region is formed in the P-type substrate, the first substrate electrode region is formed in the dielectric layer, the first substrate electrode region is contacted with the first P-type high doping region, the second substrate electrode region is formed on the dielectric layer, at least one part of the second substrate electrode region passes through the dielectric layer to be contacted with the second P-type high doping region, the P-type well region is separated from the P-type substrate through the N-type drift region, an N-type well region is formed in the P-type well region, a first N-type high doping region is formed in the N-type well region, the first N-type high doping region is separated from the P-type well region through the N-type well region, a second N-type high doping region is, at least one part of the source region penetrates through the dielectric layer to be contacted with the first N-type high-doping region, the drain region is formed on the dielectric layer, at least one part of the drain region penetrates through the dielectric layer to be contacted with the second N-type high-doping region, the gate region is formed in the dielectric layer, a first isolation medium is formed between at least one part of the gate region and at least one part of the first N-type high-doping region, a first isolation medium is also formed between at least the other part of the gate region and at least one part of the second N-type high-doping region, a second isolation medium is formed at least between the first P-type high-doping region and the second P-type high-doping region, and a second isolation medium is also formed between the dielectric layer and the P-type substrate and outside the second N-type high-doping region.

According to the semiconductor device of at least one embodiment of the present disclosure, the first field effect transistor is a PMOS transistor; the first unit cell region comprises a source region, a substrate electrode region, a gate region and a drain region, and the substrate electrode region comprises a first substrate electrode region and a second substrate electrode region; the first unit cell region comprises an N-type substrate and a dielectric layer, at least a P-type drift region is formed between the N-type substrate and the dielectric layer, an N-type well region is formed in the P-type drift region, at least a first N-type high doped region is formed in the N-type well region, a second N-type high doped region is formed in the N-type substrate, the first substrate electrode region is formed in the dielectric layer, the first substrate electrode region is contacted with the first N-type high doped region, the second substrate electrode region is formed on the dielectric layer, at least one part of the second substrate electrode region passes through the dielectric layer to be contacted with the second N-type high doped region, the N-type well region is separated from the N-type substrate through the P-type drift region, a P-type well region is formed in the N-type well region, a first P-type high doped region is formed in the P-type well region, the first P-type high doped region is separated from the N-type well region through the P-type well region, a second P-type high doped region is formed, at least one part of the source region penetrates through the dielectric layer to be in contact with the first P-type high-doping region, the drain region is formed on the dielectric layer, at least one part of the drain region penetrates through the dielectric layer to be in contact with the second P-type high-doping region, and the gate region is formed in the dielectric layer.

According to the semiconductor device of at least one embodiment of the present disclosure, the first field effect transistor is a PMOS transistor; the first unit cell region comprises a source region, a substrate electrode region, a gate region and a drain region, and the substrate electrode region comprises a first substrate electrode region and a second substrate electrode region; the first unit cell region comprises an N-type substrate and a dielectric layer, at least a P-type drift region is formed between the N-type substrate and the dielectric layer, an N-type well region is formed in the P-type drift region, at least a first N-type high doped region is formed in the N-type well region, a second N-type high doped region is formed in the N-type substrate, the first substrate electrode region is formed in the dielectric layer, the first substrate electrode region is contacted with the first N-type high doped region, the second substrate electrode region is formed on the dielectric layer, at least one part of the second substrate electrode region passes through the dielectric layer to be contacted with the second N-type high doped region, the N-type well region is separated from the N-type substrate through the P-type drift region, a P-type well region is formed in the N-type well region, a first P-type high doped region is formed in the P-type well region, the first P-type high doped region is separated from the N-type well region through the P-type well region, a second P-type high doped region is formed, at least one part of the source region penetrates through the dielectric layer to be contacted with the first P-type high-doping region, the drain region is formed on the dielectric layer, at least one part of the drain region penetrates through the dielectric layer to be contacted with the second P-type high-doping region, the gate region is formed in the dielectric layer, a first isolation medium is formed between at least one part of the gate region and at least one part of the first P-type high-doping region, and a first isolation medium is also formed between at least the other part of the gate region and at least one part of the second P-type high-doping region.

According to the semiconductor device of at least one embodiment of the present disclosure, the first field effect transistor is a PMOS transistor; the first unit cell region comprises a source region, a substrate electrode region, a gate region and a drain region, and the substrate electrode region comprises a first substrate electrode region and a second substrate electrode region; the first unit cell region comprises an N-type substrate and a dielectric layer, at least a P-type drift region is formed between the N-type substrate and the dielectric layer, an N-type well region is formed in the P-type drift region, at least a first N-type high doped region is formed in the N-type well region, a second N-type high doped region is formed in the N-type substrate, the first substrate electrode region is formed in the dielectric layer, the first substrate electrode region is contacted with the first N-type high doped region, the second substrate electrode region is formed on the dielectric layer, at least one part of the second substrate electrode region passes through the dielectric layer to be contacted with the second N-type high doped region, the N-type well region is separated from the N-type substrate through the P-type drift region, a P-type well region is formed in the N-type well region, a first P-type high doped region is formed in the P-type well region, the first P-type high doped region is separated from the N-type well region through the P-type well region, a second P-type high doped region is formed, at least one part of the source region penetrates through the dielectric layer to be contacted with the first P-type high-doping region, the drain region is formed on the dielectric layer, at least one part of the drain region penetrates through the dielectric layer to be contacted with the second P-type high-doping region, the gate region is formed in the dielectric layer, a second isolation medium is formed at least between the first N-type high-doping region and the second N-type high-doping region, and a second isolation medium is also formed at the outer side of the second P-type high-doping region and between the dielectric layer and the N-type substrate.

According to the semiconductor device of at least one embodiment of the present disclosure, the first field effect transistor is a PMOS transistor; the first unit cell region comprises a source region, a substrate electrode region, a gate region and a drain region, and the substrate electrode region comprises a first substrate electrode region and a second substrate electrode region; the first unit cell region comprises an N-type substrate and a dielectric layer, at least a P-type drift region is formed between the N-type substrate and the dielectric layer, an N-type well region is formed in the P-type drift region, at least a first N-type high doped region is formed in the N-type well region, a second N-type high doped region is formed in the N-type substrate, the first substrate electrode region is formed in the dielectric layer, the first substrate electrode region is contacted with the first N-type high doped region, the second substrate electrode region is formed on the dielectric layer, at least one part of the second substrate electrode region passes through the dielectric layer to be contacted with the second N-type high doped region, the N-type well region is separated from the N-type substrate through the P-type drift region, a P-type well region is formed in the N-type well region, a first P-type high doped region is formed in the P-type well region, the first P-type high doped region is separated from the N-type well region through the P-type well region, a second P-type high doped region is formed, at least one part of the source region penetrates through the dielectric layer to be contacted with the first P-type high-doping region, the drain region is formed on the dielectric layer, at least one part of the drain region penetrates through the dielectric layer to be contacted with the second P-type high-doping region, the gate region is formed in the dielectric layer, a first isolation medium is formed between at least one part of the gate region and at least one part of the first P-type high-doping region, a first isolation medium is also formed between at least one other part of the gate region and at least one part of the second P-type high-doping region, a second isolation medium is formed at least between the first N-type high-doping region and the second N-type high-doping region, and a second isolation medium is also formed between the dielectric layer and the N-type substrate and outside the second P-type high-doping region.

According to the semiconductor device of at least one embodiment of the present disclosure, the second field effect transistor is an NMOS transistor; the second cell region comprises a source region, a substrate electrode region, a gate region and a P-type substrate, wherein an N-type drift region is formed on the P-type substrate, a first P-type well region, a second P-type well region, an N-type well region, a P-type high-doping region, a first N-type high-doping region and a second N-type high-doping region are formed in the N-type drift region, the N-type well region is formed between the first P-type well region and the second P-type well region, the first N-type high-doping region is formed in the N-type well region, the second N-type high-doping region and the P-type high-doping region are formed in the second P-type well region and are formed adjacently, and therefore the first N-type high-doping region is isolated from the second N-type high-doping region through a PN; the second cell area also comprises a dielectric layer, and a substrate electrode area is formed in the dielectric layer and is contacted with the second N-type high-doping area and the P-type high-doping area; the gate region is formed in the dielectric layer, the source region is formed on the dielectric layer, and at least a portion of the source region passes through the dielectric layer to be in contact with the first N-type highly doped region.

According to the semiconductor device of at least one embodiment of the present disclosure, the second field effect transistor is an NMOS transistor; the second cell region comprises a source region, a substrate electrode region, a gate region and a P-type substrate, wherein an N-type drift region is formed on the P-type substrate, a first P-type well region, a second P-type well region, an N-type well region, a first P-type high doped region, a second P-type high doped region, a first N-type high doped region, a second N-type high doped region and a third N-type high doped region are formed in the N-type drift region, the N-type well region is formed between the first P-type well region and the second P-type well region, the first N-type high doped region is formed in the N-type well region, the second N-type high doped region, the third N-type high doped region, the first P-type high doped region and the second P-type high doped region are formed in the second P-type well region, the first P-type high doped region and the second N-type high doped region are arranged adjacently, a dielectric region is formed between the second N-type high doped region and the third N-type high doped region, a gate region is formed in the medium region, a medium region is formed between the first N-type high-doping region and the first P-type high-doping region, a metal floating region is formed in the medium region, a medium region is formed on one side of the second P-type high-doping region, which is opposite to the third N-type high-doping region, the medium region is formed between the first P-type well region and the second P-type well region, and the metal floating region is formed in the medium region; the second cell region also comprises a dielectric layer, the substrate electrode region is formed in the dielectric layer, one end part region of the substrate electrode region is contacted with the second N-type high-doping region and the first P-type high-doping region, and the other end part region of the substrate electrode region is contacted with the third N-type high-doping region and the second P-type high-doping region; the source region is formed on the dielectric layer, and at least a part of the source region penetrates through the dielectric layer to be in contact with the first N-type high-doping region.

According to the semiconductor device of at least one embodiment of the present disclosure, the second field effect transistor is a PMOS transistor; the second cell region comprises a source region, a substrate electrode region, a gate region and an N-type substrate, wherein a P-type drift region is formed on the N-type substrate, a first N-type well region, a second N-type well region, a P-type well region, an N-type high-doping region, a first P-type high-doping region and a second P-type high-doping region are formed in the P-type drift region, the P-type well region is formed between the first N-type well region and the second N-type well region, the first P-type high-doping region is formed in the P-type well region, the second P-type high-doping region and the N-type high-doping region are formed in the second N-type well region and are formed adjacently, and the first P-type high-doping region and the second P-type high-doping region are isolated through NP junctions; the second cell area also comprises a dielectric layer, and a substrate electrode area is formed in the dielectric layer and is contacted with the second P-type high-doping area and the N-type high-doping area; the gate region is formed in the dielectric layer, the source region is formed on the dielectric layer, and at least a portion of the source region passes through the dielectric layer to be in contact with the first P-type highly doped region.

According to the semiconductor device of at least one embodiment of the present disclosure, the second field effect transistor is a PMOS transistor; the second cell region comprises a source region, a substrate electrode region, a gate region and an N-type substrate, wherein a P-type drift region is formed on the N-type substrate, a first N-type well region, a second N-type well region, a P-type well region, a first N-type high-doped region, a second N-type high-doped region, a first P-type high-doped region, a second P-type high-doped region and a third P-type high-doped region are formed in the P-type drift region, the P-type well region is formed between the first N-type well region and the second N-type well region, the first P-type high-doped region is formed in the P-type well region, the second P-type high-doped region, the third P-type high-doped region, the first N-type high-doped region and the second N-type high-doped region are formed in the second N-type well region, the first N-type high-doped region and the second P-type high-doped region are adjacently arranged, the second N-type high-doped region and the third P-doped region are adjacently arranged, and a dielectric region is formed between the second P-type, a gate region is formed in the medium region, a medium region is formed between the first P-type high-doping region and the first N-type high-doping region, a metal floating region is formed in the medium region, a medium region is formed on one side of the second N-type high-doping region, which is opposite to the third P-type high-doping region, the medium region is formed between the first N-type well region and the second N-type well region, and the metal floating region is formed in the medium region; the second cell region also comprises a dielectric layer, the substrate electrode region is formed in the dielectric layer, one end part region of the substrate electrode region is contacted with the second P-type high-doping region and the first N-type high-doping region, and the other end part region of the substrate electrode region is contacted with the third P-type high-doping region and the second N-type high-doping region; the source region is formed on the dielectric layer, and at least a part of the source region penetrates through the dielectric layer to be in contact with the first P-type high-doping region.

According to the semiconductor device of at least one embodiment of the present disclosure, the third cell region includes a gate region, a drain region and a P-type substrate, an N-type drift region is formed on the P-type substrate, a first P-type well region and a second P-type well region are formed in the N-type drift region, an N-type well region is formed between the first P-type well region and the second P-type well region, an N-type highly doped region is formed in the N-type well region, a P-type highly doped region is formed in the second P-type well region, a dielectric layer is formed on the N-type drift region, the gate region is formed on the dielectric layer, at least a portion of the gate region penetrates through the dielectric layer to be in contact with the P-type highly doped region, the drain region is formed on the dielectric layer, and at least a portion of the drain.

According to the semiconductor device of at least one embodiment of the present disclosure, the third cell region includes a gate region, a drain region and a P-type substrate, an N-type drift region is formed on the P-type substrate, a first P-type well region and a second P-type well region are formed in the N-type drift region, an N-type well region is formed between the first P-type well region and the second P-type well region, an N-type highly doped region is formed in the N-type well region, a P-type highly doped region is formed in the second P-type well region, a dielectric layer is formed on the N-type drift region, the gate region is formed on the dielectric layer, at least a portion of the gate region penetrates through the dielectric layer to be in contact with the P-type highly doped region, the drain region is formed on the dielectric layer, at least a portion of the drain region penetrates through the dielectric layer to be in contact with the N-type highly doped region, and isolation media.

According to the semiconductor device of at least one embodiment of the present disclosure, the third cell region includes a gate region, a drain region and a P-type substrate, an N-type drift region is formed on the P-type substrate, a first P-type well region and a second P-type well region are formed in the N-type drift region, an N-type well region is formed between the first P-type well region and the second P-type well region, an N-type highly doped region is formed in the N-type well region, a P-type highly doped region is formed in the second P-type well region, a dielectric layer is formed on the P-type substrate and the N-type drift region, the gate region is formed on the dielectric layer, at least a portion of the gate region contacts the P-type highly doped region through the dielectric layer, a first portion of the drain region is formed on the dielectric layer, and a second portion and a third portion of the drain, a Poly resistor is formed between the second part and the third part, and the third part of the drain region is in contact with the N-type high-doped region.

According to the semiconductor device of at least one embodiment of the present disclosure, the third cell region includes a gate region, a drain region and a P-type substrate, an N-type drift region is formed on the P-type substrate, a first P-type well region and a second P-type well region are formed in the N-type drift region, an N-type well region is formed between the first P-type well region and the second P-type well region, an N-type highly doped region is formed in the N-type well region, a P-type highly doped region is formed in the second P-type well region, a dielectric layer is formed on the P-type substrate and the N-type drift region, the gate region is formed on the dielectric layer, at least a portion of the gate region passes through the dielectric layer to be in contact with the P-type highly doped region, a first portion of the drain region is formed on the dielectric layer, a second portion and a third portion of the drain region are formed in the dielectric layer, a Poly resistor is formed between the second portion and the third portion, and, an isolation dielectric is partially formed between the dielectric layer and the P-type substrate.

According to the semiconductor device of at least one embodiment of the present disclosure, the third cell region includes a gate region, a drain region and an N-type substrate, a P-type drift region is formed on the N-type substrate, a first N-type well region and a second N-type well region are formed in the P-type drift region, a P-type well region is formed between the first N-type well region and the second N-type well region, a P-type highly doped region is formed in the P-type well region, a N-type highly doped region is formed in the second N-type well region, a dielectric layer is formed on the N-type substrate and the P-type drift region, the gate region is formed on the dielectric layer, at least a portion of the gate region contacts the N-type highly doped region through the dielectric layer, a first portion of the drain region is formed on the dielectric layer, and a second portion and a third portion of the drain, a Poly resistor is formed between the second portion and the third portion, and the third portion of the drain region is in contact with the P-type highly doped region.

According to the semiconductor device of at least one embodiment of the present disclosure, the third cell region includes a gate region, a drain region and an N-type substrate, a P-type drift region is formed on the N-type substrate, a first N-type well region and a second N-type well region are formed in the P-type drift region, a P-type well region is formed between the first N-type well region and the second N-type well region, a P-type highly doped region is formed in the P-type well region, an N-type highly doped region is formed in the second N-type well region, a dielectric layer is formed on the N-type substrate and the P-type drift region, the gate region is formed on the dielectric layer, at least a portion of the gate region passes through the dielectric layer to be in contact with the N-type highly doped region, a first portion of the drain region is formed on the dielectric layer, a second portion and a third portion of the drain region are formed in the dielectric layer, a Poly resistor is formed between the second portion and the third portion, and, an isolation dielectric is partially formed between the dielectric layer and the N-type substrate.

According to the semiconductor device of at least one embodiment of the present disclosure, the first cell region, the second cell region, and the third cell region share the dielectric layer.

According to the semiconductor device of at least one embodiment of the present disclosure, the first cell region and the second cell region are spaced by an isolation medium therebetween, and the second cell region and the third cell region are also spaced by an isolation medium therebetween.

Drawings

The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the disclosure and together with the description serve to explain the principles of the disclosure.

Fig. 1 is a schematic circuit diagram of a semiconductor device for battery protection according to an embodiment of the present disclosure.

Fig. 2 is a schematic circuit diagram of a first cell region (MN1) of a semiconductor device for battery protection according to an embodiment of the present disclosure.

Fig. 3 is a schematic circuit diagram corresponding to a second cell region (MNB) of the semiconductor device for battery protection according to an embodiment of the present disclosure.

Fig. 4 is a schematic structural diagram of a first cell region of a semiconductor device for battery protection according to an embodiment of the present disclosure.

Fig. 5 is a schematic structural view of a first cell region of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

Fig. 6 is a schematic structural view of a first cell region of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

Fig. 7 is a schematic structural view of a first cell region of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

Fig. 8 is a schematic structural view of a second cell region of a semiconductor device for battery protection according to an embodiment of the present disclosure.

Fig. 9 is a schematic structural view of a second cell region of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

Fig. 10 is a schematic structural view of a third cell region of the semiconductor device for battery protection according to one embodiment of the present disclosure.

Fig. 11 is a schematic structural view of a third cell region of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

Fig. 12 is a schematic structural view of a third cell region of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

Fig. 13 is a schematic structural view of a third cell region of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

Fig. 14 is an overall structural schematic diagram of a semiconductor device for battery protection according to an embodiment of the present disclosure.

Fig. 15 is an overall structural schematic diagram of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

Fig. 16 is an overall structural schematic diagram of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

Fig. 17 is an overall structural schematic diagram of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

Fig. 18 is an overall structural schematic diagram of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

Fig. 19 is an overall structural schematic diagram of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

Fig. 20 is an overall structural schematic diagram of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

Detailed Description

The present disclosure will be described in further detail with reference to the drawings and embodiments. It is to be understood that the specific embodiments described herein are for purposes of illustration only and are not to be construed as limitations of the present disclosure. It should be further noted that, for the convenience of description, only the portions relevant to the present disclosure are shown in the drawings.

It should be noted that the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. Technical solutions of the present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.

Unless otherwise indicated, the illustrated exemplary embodiments/examples are to be understood as providing exemplary features of various details of some ways in which the technical concepts of the present disclosure may be practiced. Accordingly, unless otherwise indicated, features of the various embodiments may be additionally combined, separated, interchanged, and/or rearranged without departing from the technical concept of the present disclosure.

The use of cross-hatching and/or shading in the drawings is generally used to clarify the boundaries between adjacent components. As such, unless otherwise noted, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, proportion, commonality between the illustrated components and/or any other characteristic, attribute, property, etc., of a component. Further, in the drawings, the size and relative sizes of components may be exaggerated for clarity and/or descriptive purposes. While example embodiments may be practiced differently, the specific process sequence may be performed in a different order than that described. For example, two processes described consecutively may be performed substantially simultaneously or in reverse order to that described. In addition, like reference numerals denote like parts.

When an element is referred to as being "on" or "on," "connected to" or "coupled to" another element, it can be directly on, connected or coupled to the other element or intervening elements may be present. However, when an element is referred to as being "directly on," "directly connected to" or "directly coupled to" another element, there are no intervening elements present. For purposes of this disclosure, the term "connected" may refer to physically, electrically, etc., and may or may not have intermediate components.

For descriptive purposes, the present disclosure may use spatially relative terms such as "below … …," below … …, "" below … …, "" below, "" above … …, "" above, "" … …, "" higher, "and" side (e.g., as in "side wall") to describe one component's relationship to another (other) component as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and/or manufacture in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below … …" can encompass both an orientation of "above" and "below". Further, the devices may be otherwise positioned (e.g., rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, when the terms "comprises" and/or "comprising" and variations thereof are used in this specification, the presence of stated features, integers, steps, operations, elements, components and/or groups thereof are stated but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof. It is also noted that, as used herein, the terms "substantially," "about," and other similar terms are used as approximate terms and not as degree terms, and as such, are used to interpret inherent deviations in measured values, calculated values, and/or provided values that would be recognized by one of ordinary skill in the art.

As shown in fig. 1 to 3, a semiconductor device includes: a first cell region 100, the first cell region 100 being formed with a first field effect transistor MN 1; a second cell area 200, wherein a second field effect transistor MNB is formed in the second cell area 200, and the second field effect transistor MNB is used as a first switch for controlling the connection and disconnection between the source S of the first field effect transistor MN1 and the substrate; and a third cell area 300, the third cell area 300 being formed with a second switch for controlling connection and disconnection between the gate G and the drain D of the first field effect transistor MN 1; the first cell area 100, the second cell area 200, and the third cell area 300 are sequentially formed, and the second cell area 200 is formed between the first cell area 100 and the third cell area 300.

As shown in fig. 1 and 4 to 7, the first cell region 100 includes a source region 104(S), a substrate electrode region 101(B1, B2), a gate region 105(G), and a drain region 106(D), a first parasitic diode D1 and a second parasitic diode D2 are formed in the first cell region 100, the first parasitic diode D1 and the second parasitic diode D2 form an anti-series structure, the first parasitic diode D1 and the second parasitic diode D2 are formed between the source region 104(S) and the drain region 106(D), and a junction region of the first parasitic diode D1 and the second parasitic diode D2 formed in the first cell region 100 is formed at least on the substrate electrode region 101 (B1).

As shown in fig. 1, 8 and 9, the second cell region 200 includes a source region S, a substrate electrode region B1, a gate region G and a drain region D, the second field effect transistor formed by the second cell region 200 has a fourth parasitic diode D4, and the fourth parasitic diode D4 is formed between the source region S and the substrate electrode region B1 of the second field effect transistor.

As shown in fig. 1 and 10 to 13, the third cell region 300 includes a gate region G and a drain region D, a third parasitic diode D3 and a resistor R1 are formed between the drain region D of the third cell region 300 and the gate region G, and the third parasitic diode D3 and the resistor R1 form a series structure.

According to a preferred embodiment of the present disclosure, the first cell region 100, the second cell region 200, and the third cell region 300 of the semiconductor device share a substrate (e.g., a PSub, i.e., a P-type substrate).

Fig. 4 is a schematic structural diagram of a first cell region 100 of a semiconductor device for battery protection according to an embodiment of the present disclosure.

As shown in fig. 4, the first field effect transistor is an NMOS transistor; the first cell region 100 includes a source region 104(S), a substrate electrode region 101(B1\ B2), a gate region 105(G), and a drain region 106(D), the substrate electrode region 101 includes a first substrate electrode region (B1) and a second substrate electrode region (B2); the first unit cell region 100 comprises a P-type substrate 112(Psub) and a dielectric layer 103, at least an N-type drift region 111(ND) is formed between the P-type substrate 112 and the dielectric layer 103, a P-type well region 110(PW) is formed in the N-type drift region 111(ND), at least a first P-type highly doped region 107(P +) is formed in the P-type well region 110(PW), a second P-type highly doped region 107(P +) is formed in the P-type substrate 112, a first substrate electrode region (B1) is formed in the dielectric layer 103, the first substrate electrode region (B1) is in contact with the first P-type highly doped region 107(P +), a second substrate electrode region (B2) is formed on the dielectric layer 103, at least a portion of the second substrate electrode region (B2) passes through the dielectric layer 103 to be in contact with the second P-type highly doped region (P +), the P-type well region 110(PW) is spaced from the P-type substrate by the N-type drift region 111(ND), and an N-type well region 109 (PW) is formed in the P-type drift region 110(PW, a first N-type highly doped region 108(N +) is formed in the N-type well region 109(N), the first N-type highly doped region 108(N +) is separated from the P-type well region 110(PW) by the N-type well region 109(N), a second N-type highly doped region 108(N +) is formed in the N-type drift region 111(ND), a source region 104(S) is formed on the dielectric layer 103, at least a portion of the source region 104(S) passes through the dielectric layer 103 and contacts the first N-type highly doped region 108(N +), a drain region 106(D) is formed on the dielectric layer 103, at least a portion of the drain region 106(D) passes through the dielectric layer 103 and contacts the second N-type highly doped region 108(N +), and a gate region 105(G) is formed in the dielectric layer 103.

The doping concentration of the N + region is greater than that of the N region, and the doping concentration of the P + region is greater than that of the PW region.

The source region S may be made of a metal material, the dielectric layer 103 is an oxide layer, the substrate electrode region 101 is made of a metal material, the gate region G may be made of polysilicon, the P-type highly doped region P + is made of P-type doped silicon, the P-type well region PW is made of P-type doped silicon, the first N-type highly doped region N + is made of N-type doped silicon, the N-type well region N is made of N-type doped silicon, the N-type drift region ND is made of N-type doped silicon, and the drain region D may be made of a metal material.

As shown in fig. 4, the N region and the PW region form a parasitic diode D2 (also shown as D2 in fig. 1), the PW region and the ND region form a parasitic diode D1 (also shown as D1 in fig. 1), and the P + region and the N + region are isolated from each other by a PN junction.

Fig. 5 is a schematic structural diagram of a first cell region 100 of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

As shown in fig. 5, the first field effect transistor is an NMOS transistor; the first cell region 100 includes a source region 104, a substrate electrode region 101, a gate region 105, and a drain region 106, the substrate electrode region 101 includes a first substrate electrode region and a second substrate electrode region; the first unit cell region 100 comprises a P-type substrate 112 and a dielectric layer 103, at least an N-type drift region 111 is formed between the P-type substrate 112 and the dielectric layer 103, a P-type well region 110 is formed in the N-type drift region 111, at least a first P-type high doping region 107 is formed in the P-type well region 110, a second P-type high doping region 107 is formed in the P-type substrate 112, a first substrate electrode region is formed in the dielectric layer 103, the first substrate electrode region is in contact with the first P-type high doping region 107, a second substrate electrode region is formed on the dielectric layer, at least a part of the second substrate electrode region passes through the dielectric layer 103 and is in contact with the second P-type high doping region, the P-type well region 110 and the P-type substrate are separated by the N-type drift region 111, an N-type well region 109 is formed in the P-type well region 110, a first N-type high doping region 108 is formed in the N-type well region 109, the first N-type high doping region 108 and the P, a second N-type highly doped region 108 is formed in the N-type drift region 111, the source region 104 is formed on the dielectric layer, at least a portion of the source region 104 contacts the first N-type highly doped region 108 through the dielectric layer 103, the drain region 106 is formed on the dielectric layer, at least a portion of the drain region 106 contacts the second N-type highly doped region 108 through the dielectric layer 103, the gate region 105 is formed in the dielectric layer, a first isolation dielectric 113 is formed between at least a portion of the gate region 105 and at least a portion of the first N-type highly doped region 108, and a first isolation dielectric 113 is also formed between at least another portion of the gate region 105 and at least a portion of the second N-type highly doped region 108.

The first isolation dielectric 113 may be an oxide layer. The G-N voltage resistance is improved by the first isolation medium 113.

Fig. 6 is a schematic structural diagram of a first cell region 100 of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

As shown in fig. 6, the first field effect transistor is an NMOS transistor; the first cell region 100 includes a source region 104, a substrate electrode region 101, a gate region 105, and a drain region 106, the substrate electrode region 101 includes a first substrate electrode region and a second substrate electrode region; the first unit cell region 100 comprises a P-type substrate 112 and a dielectric layer 103, at least an N-type drift region 111 is formed between the P-type substrate 112 and the dielectric layer 103, a P-type well region 110 is formed in the N-type drift region 111, at least a first P-type high doping region 107 is formed in the P-type well region 110, a second P-type high doping region 107 is formed in the P-type substrate 112, a first substrate electrode region is formed in the dielectric layer 103, the first substrate electrode region is in contact with the first P-type high doping region 107, a second substrate electrode region is formed on the dielectric layer, at least a part of the second substrate electrode region passes through the dielectric layer 103 and is in contact with the second P-type high doping region, the P-type well region 110 and the P-type substrate are separated by the N-type drift region 111, an N-type well region 109 is formed in the P-type well region 110, a first N-type high doping region 108 is formed in the N-type well region 109, the first N-type high doping region 108 and the P, a second N-type highly doped region 108 is formed in the N-type drift region 111, the source region 104 is formed on the dielectric layer, at least a portion of the source region 104 passes through the dielectric layer 103 to contact with the first N-type highly doped region 108, the drain region 106 is formed on the dielectric layer, at least a portion of the drain region 106 passes through the dielectric layer 103 to contact with the second N-type highly doped region 108, the gate region 105 is formed in the dielectric layer 103, a second isolation dielectric 114 is formed at least between the first P-type highly doped region and the second P-type highly doped region, and a second isolation dielectric 114 is also formed outside the second N-type highly doped region 108 and between the dielectric layer 103 and the P-type substrate 112.

The second isolation dielectric 114 may be an oxide layer, and the first P + region is isolated from the second P + region by a second isolation dielectric (trench dielectric).

Fig. 7 is a schematic structural diagram of a first cell region 100 of a semiconductor device for battery protection according to still another embodiment of the present disclosure.

As shown in fig. 7, the first field effect transistor is an NMOS transistor; the first cell region 100 includes a source region 104, a substrate electrode region 101, a gate region 105, and a drain region 106, the substrate electrode region 101 includes a first substrate electrode region and a second substrate electrode region; the first unit cell region 100 comprises a P-type substrate 112 and a dielectric layer 103, at least an N-type drift region 111 is formed between the P-type substrate 112 and the dielectric layer 103, a P-type well region 110 is formed in the N-type drift region 111, at least a first P-type high doping region 107 is formed in the P-type well region 110, a second P-type high doping region 107 is formed in the P-type substrate 112, a first substrate electrode region is formed in the dielectric layer 103, the first substrate electrode region is in contact with the first P-type high doping region 107, a second substrate electrode region is formed on the dielectric layer, at least a part of the second substrate electrode region passes through the dielectric layer 103 and is in contact with the second P-type high doping region, the P-type well region 110 and the P-type substrate are separated by the N-type drift region 111, an N-type well region 109 is formed in the P-type well region 110, a first N-type high doping region 108 is formed in the N-type well region 109, the first N-type high doping region 108 and the P, a second N-type highly doped region 108 is formed in the N-type drift region 111, the source region 104 is formed on the dielectric layer, at least a portion of the source region 104 contacts the first N-type highly doped region 108 through the dielectric layer 103, the drain region 106 is formed on the dielectric layer, at least a portion of the drain region 106 contacts the second N-type highly doped region 108 through the dielectric layer 103, the gate region 105 is formed in the dielectric layer 103, a first isolation medium 113 is formed between at least one portion of the gate region 105 and at least one portion of the first N-type highly doped region 108, a first isolation medium 113 is also formed between at least another portion of the gate region 105 and at least one portion of the second N-type highly doped region 108, a second isolation medium 114 is formed at least between the first P-type highly doped region and the second P-type highly doped region, a second isolation dielectric 114 is also formed between the dielectric layer 103 and the P-type substrate 112 outside the second N-type highly doped region 108.

In the above embodiments, the first field effect transistor MN1 of the semiconductor device is an NMOS transistor, and it should be understood by those skilled in the art that the first field effect transistor MN1 may also be designed as a PMOS transistor, and if the first field effect transistor MN1 is designed as a PMOS transistor, the "P type" and the "N type" in the first cell region 100 of the above embodiments are interchanged, so that a plurality of first cell regions forming PMOS transistors of the above embodiments can be formed.

The MN1 circuit structure in fig. 1 and 2 can be implemented by using the first cell region in the above embodiments.

Fig. 8 is a schematic structural diagram of a second cell region 200 of a semiconductor device for battery protection according to an embodiment of the present disclosure.

As shown in fig. 8, the second field effect transistor MNB formed in the second cell region 200 is an NMOS transistor; the second cell region 200 comprises a source region S, a substrate electrode region B1, a gate region G and a P-type substrate Psub, an N-type drift region ND is formed on the P-type substrate Psub, a first P-type well region PW, a second P-type well region, an N-type well region N, P-type highly doped region P +, a first N-type highly doped region N + and a second N-type highly doped region N + are formed in the N-type drift region ND, the N-type well region N is formed between the first P-type well region PW and the second P-type well region, the first N-type highly doped region N + is formed in the N-type well region N, the second N-type highly doped region N + and the P-type highly doped region P + are formed in the second P-type well region and are formed adjacently, so that the first N-type highly doped region N + and the second N-type highly doped region N + are isolated by a PN junction; the second cell region 200 further comprises a dielectric layer, a substrate electrode region B1 is formed in the dielectric layer, and the substrate electrode region B1 is in contact with the second N-type high-doping region N + and the P-type high-doping region P +; the gate region G is formed in the dielectric layer, the source region S is formed on the dielectric layer, and at least one part of the source region S penetrates through the dielectric layer to be in contact with the first N-type high-doping region N +.

In fig. 8, the gate region G is a planar gate structure, and the PN structure between the first N-type highly doped region N + and the second N-type highly doped region N + is a parasitic diode D4 (D4 is shown in fig. 1 and 3).

Fig. 9 is a schematic structural diagram of a second cell region 200 of a semiconductor device for battery protection according to an embodiment of the present disclosure.

As shown in fig. 9, the second field effect transistor is an NMOS transistor; the second cell region 200 includes a source region, a substrate electrode region, a gate region, and a P-type substrate, wherein an N-type drift region is formed on the P-type substrate, a first P-type well region, a second P-type well region, an N-type well region, a first P-type highly doped region, a second P-type highly doped region, a first N-type highly doped region, a second N-type highly doped region, and a third N-type highly doped region are formed in the N-type drift region, the N-type well region is formed between the first P-type well region and the second P-type well region, the first N-type highly doped region is formed in the N-type well region, the second N-type highly doped region, the third N-type highly doped region, the first P-type highly doped region, and the second P-type highly doped region are formed in the second P-type well region, the first P-type highly doped region is disposed adjacent to the second N-type highly doped region, the second P-type highly doped region is disposed adjacent to the third N-type highly doped region, and a dielectric region is formed between the second N-type highly doped region and the third N-, a gate region is formed in the medium region, a medium region is formed between the first N-type high-doping region and the first P-type high-doping region, a metal floating region is formed in the medium region, a medium region is formed on one side of the second P-type high-doping region, which is opposite to the third N-type high-doping region, the medium region is formed between the first P-type well region and the second P-type well region, and the metal floating region is formed in the medium region; the second cell region 200 further includes a dielectric layer, a substrate electrode region is formed in the dielectric layer, one end region of the substrate electrode region is in contact with the second N-type highly doped region and the first P-type highly doped region, and the other end region of the substrate electrode region is in contact with the third N-type highly doped region and the second P-type highly doped region; the source region is formed on the dielectric layer, and at least a part of the source region penetrates through the dielectric layer to be in contact with the first N-type high-doping region.

As shown in fig. 9, in this embodiment, the gate region G is a trench gate structure.

As shown in fig. 9, the N-well region N and the second P-well region form a parasitic diode D4 (D4 is shown in fig. 1 and 3).

In the above embodiments, the second field effect transistors MNB of the semiconductor device are all NMOS transistors, and it should be understood by those skilled in the art that the second field effect transistors may also be designed as PMOS transistors, and if the second field effect transistors are designed as PMOS transistors, the "P type" and the "N type" in the second cell region 200 of the above embodiments are interchanged, so that a plurality of second cell regions forming PMOS transistors of the above embodiments can be formed.

The MNB circuit structure in fig. 1 and 3 can be implemented by using the second cell area 200 of each of the above embodiments.

Fig. 10 is a schematic structural view of a third cell region 300 of a semiconductor device for battery protection according to an embodiment of the present disclosure.

As shown in fig. 10, the third cell region 300 includes a gate region G, a drain region D and a P-type substrate Psub, an N-type drift region ND is formed on the P-type substrate Psub, a first P-type well region PW and a second P-type well region are formed in the N-type drift region ND, an N-type well region N is formed between the first P-type well region PW and the second P-type well region, an N-type highly doped region N + is formed in the N-type well region N, a P-type highly doped region P + is formed in the second P-type well region, a dielectric layer is formed on the N-type drift region ND, the gate region G is formed on the dielectric layer, at least a portion of the gate region G passes through the dielectric layer to be in contact with the P-type highly doped region P +, the drain region D is formed on the dielectric layer, and at least a portion of the drain region D passes through the dielectric layer to.

The second P-type well region and the N-type well region N form a second switch, i.e., a third parasitic diode D3, i.e., a voltage-withstanding diode D3 (a voltage-withstanding diode D3 is shown in fig. 1), and the N-type well region N serves as a resistor R1 in fig. 1. The resistance of R1 can be adjusted by adjusting the thickness and/or doping concentration of the N-well region.

Fig. 11 is a schematic structural diagram of a third cell region 300 of a semiconductor device for battery protection according to an embodiment of the present disclosure.

As shown in fig. 11, the third cell region 300 includes a gate region, a drain region and a P-type substrate, an N-type drift region is formed on the P-type substrate, a first P-type well region and a second P-type well region are formed in the N-type drift region, an N-type well region is formed between the first P-type well region and the second P-type well region, an N-type highly doped region is formed in the N-type well region, a P-type highly doped region is formed in the second P-type well region, a dielectric layer is formed on the N-type drift region, the gate region is formed on the dielectric layer, at least a portion of the gate region passes through the dielectric layer and contacts with the P-type highly doped region, the drain region is formed on the dielectric layer, at least a portion of the drain region passes through the dielectric layer and contacts with the N-type highly doped region, and isolation dielectrics are formed between the dielectric layer.

Fig. 12 is a schematic structural diagram of a third cell region 300 of a semiconductor device for battery protection according to an embodiment of the present disclosure.

As shown in fig. 12, the third cell region 300 includes a gate region, a drain region and a P-type substrate, an N-type drift region is formed on the P-type substrate, a first P-type well region and a second P-type well region are formed in the N-type drift region, an N-type well region is formed between the first P-type well region and the second P-type well region, an N-type highly doped region is formed in the N-type well region, a P-type highly doped region is formed in the second P-type well region, a dielectric layer is formed on the P-type substrate and the N-type drift region, the gate region is formed on the dielectric layer, at least a portion of the gate region passes through the dielectric layer and contacts the P-type highly doped region, a first portion of the drain region is formed on the dielectric layer, a second portion and a third portion of the drain region are formed in the dielectric layer, a Poly resistor is formed between the second portion and the third portion of the drain region and contacts the.

As shown in fig. 12, the first portion and the second portion of the drain region D are continuous structures, and the second portion and the third portion are discontinuous structures.

Fig. 13 is a schematic structural view of a third cell region 300 of a semiconductor device for battery protection according to an embodiment of the present disclosure.

As shown in fig. 13, the third cell region 300 includes a gate region, a drain region and a P-type substrate, an N-type drift region is formed on the P-type substrate, a first P-type well region and a second P-type well region are formed in the N-type drift region, an N-type well region is formed between the first P-type well region and the second P-type well region, an N-type highly doped region is formed in the N-type well region, a P-type highly doped region is formed in the second P-type well region, a dielectric layer is formed on the P-type substrate and the N-type drift region, the gate region is formed on the dielectric layer, at least a portion of the gate region contacts the P-type highly doped region through the dielectric layer, a first portion of the drain region is formed on the dielectric layer, and a second portion and a third portion of the drain region are, a Poly resistor is formed between the second portion and the third portion, the third portion of the drain region is in contact with the N-type high-doping region, and an isolation medium is partially formed between the medium layer and the P-type substrate.

The D3& R1 circuit structure in fig. 1 may be implemented using the third cell area 300 of the above-described embodiments.

It should be understood by those skilled in the art that the sizes and shapes of the D region, the N + region, the ND region, the PW region, the G region, the S region, the B region, the N + region, the P + region, the dielectric layer, the isolation dielectric, etc. in the above embodiments are all exemplary, and those skilled in the art can appropriately adjust the sizes and shapes, and fall within the protection scope of the present disclosure.

According to a preferred embodiment of the present disclosure, the first cell region, the second cell region, and the third cell region share a dielectric layer.

According to a preferred embodiment of the present disclosure, the first cell region and the second cell region are separated by a separation medium, and the second cell region and the third cell region are also separated by a separation medium.

Fig. 14 to 20 are overall structural schematic views of a semiconductor device for battery protection according to a preferred embodiment of the present disclosure.

Fig. 14 shows an overall structure of a semiconductor device in which the first cell region and the second cell region and the third cell region are each separated by an isolation medium.

Fig. 15 shows that the first cell region and the second cell region and the third cell region in the overall structure of the semiconductor device are all separated by PN junctions, and fig. 15 adopts a planar gate LDMOS structure.

Fig. 16 shows a semiconductor device in which the first cell region and the second cell region and the third cell region are all separated by PN junctions in the entire structure, and fig. 16 adopts a planar gate LDMOS/gate field plate structure.

Fig. 17 shows a semiconductor device in which a first cell region and a second cell region and a third cell region are separated by a trench isolation dielectric, and fig. 17 employs a planar gate LDMOS and trench dielectric isolation structure.

Fig. 18 shows a semiconductor device in which the first cell region and the second cell region and the third cell region are separated by a trench isolation dielectric in the entire structure, and fig. 18 employs a planar gate LDMOS and plate and trench isolation structure.

Fig. 19 shows that the first cell region and the second cell region and the third cell region in the overall structure of the semiconductor device are all separated by PN junctions, and fig. 19 adopts a planar gate LDMOS structure.

Fig. 20 shows the semiconductor device in which the first cell region and the second cell region and the third cell region are all separated by PN junctions in the entire structure, and fig. 20 employs a planar gate LDMOS and a trench gate integrating structure.

The overall structure shown in fig. 14 to 19 is only the structure of the preferred embodiment of the present disclosure, and modifications and changes made by those skilled in the art within the framework of the structural idea of the semiconductor device of the present disclosure fall within the scope of the present disclosure.

It will be understood by those skilled in the art that the foregoing embodiments are merely for clarity of illustration of the disclosure and are not intended to limit the scope of the disclosure. Other variations or modifications may occur to those skilled in the art, based on the foregoing disclosure, and are still within the scope of the present disclosure.

Claims

1. a semiconductor device, is characterized in that, comprises:

a first cell area, the first cell area is formed with a first field effect transistor;

The second cell area, the second cell area is formed with a second field effect transistor, the second field effect transistor is used as a first switch, and the first switch is used to control the source of the first field effect transistor connection and disconnection between the pole and the substrate; and

a third cell area, the third cell area is formed with a second switch, and the second switch is used to control the connection and disconnection between the gate and the drain of the first field effect transistor;

Wherein, a first cell area, a second cell area and a third cell area are formed in sequence, and the second cell area is formed between the first cell area and the third cell area.

2 . The semiconductor device according to claim 1 , wherein the first cell region comprises a source region, a substrate electrode region, a gate region and a drain region, and the first cell region is formed in the a first parasitic diode and a second parasitic diode, the first parasitic diode and the second parasitic diode form a reverse series structure, the first parasitic diode and the second parasitic diode are formed in the source region and the drain Between regions, a connecting region of the first parasitic diode and the second parasitic diode formed in the first cell region is formed at least on the substrate electrode region.

3 . The semiconductor device according to claim 2 , wherein the second cell region comprises a source region, a substrate electrode region, a gate region and a drain region, and the second cell region is formed of The second field effect transistor has a fourth parasitic diode (D4) formed between the source region and the substrate electrode region of the second field effect transistor.

4 . The semiconductor device according to claim 3 , wherein the third cell region comprises a gate region and a drain region, and is between the drain region and the gate region of the third cell region. 5 . A third parasitic diode and a resistor are formed, and the third parasitic diode and the resistor form a series structure.

5 . The semiconductor device of claim 4 , wherein the first cell region, the second cell region and the third cell region share a substrate. 6 .

6. The semiconductor device according to claim 1 or 2, wherein the first field effect transistor is an NMOS transistor;

The first cell region includes a source region, a substrate electrode region, a gate region and a drain region, and the substrate electrode region includes a first substrate electrode region and a second substrate electrode region; the first substrate electrode region The cell region includes a P-type substrate and a dielectric layer, at least an N-type drift region is formed between the P-type substrate and the dielectric layer, a P-type well region is formed in the N-type drift region, and the P-type well region is formed in the N-type drift region. At least a first P-type highly doped region is formed in the well region, a second P-type highly doped region is formed in the P-type substrate, the first substrate electrode region is formed in the dielectric layer, and the first substrate is formed in the dielectric layer. A substrate electrode region is in contact with the first P-type highly doped region, the second substrate electrode region is formed on the dielectric layer, and at least a portion of the second substrate electrode region passes through the dielectric The layer is in contact with the second P-type highly doped region, the P-type well region and the P-type substrate are separated by the N-type drift region, and an N-type well region is formed in the P-type well region, A first N-type highly doped region is formed in the N-type well region, the first N-type highly doped region and the P-type well region are separated by the N-type well region, and the N-type drift region A second N-type highly doped region is formed in the middle, the source region is formed on the dielectric layer, and at least a part of the source region passes through the dielectric layer and the first N-type highly doped region contact, the drain region is formed on the dielectric layer, at least a part of the drain region is in contact with the second N-type highly doped region through the dielectric layer, and the gate region is formed on the dielectric layer in the dielectric layer.

7. The semiconductor device according to claim 1 or 2, wherein the first field effect transistor is an NMOS transistor;

The first cell region includes a source region, a substrate electrode region, a gate region and a drain region, and the substrate electrode region includes a first substrate electrode region and a second substrate electrode region; the first substrate electrode region The cell region includes a P-type substrate and a dielectric layer, at least an N-type drift region is formed between the P-type substrate and the dielectric layer, and a P-type well region is formed in the N-type drift region, and the P-type well region is formed in the N-type drift region. At least a first P-type highly doped region is formed in the well region, a second P-type highly doped region is formed in the P-type substrate, the first substrate electrode region is formed in the dielectric layer, and the second P-type highly doped region is formed in the P-type substrate. A substrate electrode region is in contact with the first P-type highly doped region, the second substrate electrode region is formed on the dielectric layer, and at least a portion of the second substrate electrode region passes through the dielectric The layer is in contact with the second P-type highly doped region, the P-type well region and the P-type substrate are separated by the N-type drift region, and an N-type well region is formed in the P-type well region, A first N-type highly doped region is formed in the N-type well region, the first N-type highly doped region and the P-type well region are separated by the N-type well region, and the N-type drift region A second N-type highly doped region is formed in the middle, the source region is formed on the dielectric layer, and at least a part of the source region passes through the dielectric layer and the first N-type highly doped region contact, the drain region is formed on the dielectric layer, at least a part of the drain region is in contact with the second N-type highly doped region through the dielectric layer, and the gate region is formed on the dielectric layer In the dielectric layer, a first isolation dielectric is formed between at least a part of the gate region and at least a part of the first N-type highly doped region, and at least another part of the gate region is connected to the second A first isolation medium is also formed between at least a portion of the N-type highly doped regions.

8. The semiconductor device according to claim 1 or 2, wherein the first field effect transistor is an NMOS transistor;

The first cell region includes a source region, a substrate electrode region, a gate region and a drain region, and the substrate electrode region includes a first substrate electrode region and a second substrate electrode region; the first substrate electrode region The cell region includes a P-type substrate and a dielectric layer, at least an N-type drift region is formed between the P-type substrate and the dielectric layer, and a P-type well region is formed in the N-type drift region, and the P-type well region is formed in the N-type drift region. At least a first P-type highly doped region is formed in the well region, a second P-type highly doped region is formed in the P-type substrate, the first substrate electrode region is formed in the dielectric layer, and the second P-type highly doped region is formed in the P-type substrate. A substrate electrode region is in contact with the first P-type highly doped region, the second substrate electrode region is formed on the dielectric layer, and at least a portion of the second substrate electrode region passes through the dielectric The layer is in contact with the second P-type highly doped region, the P-type well region and the P-type substrate are separated by the N-type drift region, and an N-type well region is formed in the P-type well region, A first N-type highly doped region is formed in the N-type well region, the first N-type highly doped region and the P-type well region are separated by the N-type well region, and the N-type drift region A second N-type highly doped region is formed in the middle, the source region is formed on the dielectric layer, and at least a part of the source region passes through the dielectric layer and the first N-type highly doped region contact, the drain region is formed on the dielectric layer, at least a part of the drain region is in contact with the second N-type highly doped region through the dielectric layer, and the gate region is formed on the dielectric layer In the dielectric layer, a second isolation medium is formed at least between the first P-type highly doped region and the second P-type highly doped region, and the dielectric is outside the second N-type highly doped region. A second isolation dielectric is also formed between the layer and the P-type substrate.

9. The semiconductor device according to claim 1 or 2, wherein the first field effect transistor is an NMOS transistor;

The first cell region includes a source region, a substrate electrode region, a gate region and a drain region, and the substrate electrode region includes a first substrate electrode region and a second substrate electrode region; the first substrate electrode region The cell region includes a P-type substrate and a dielectric layer, at least an N-type drift region is formed between the P-type substrate and the dielectric layer, and a P-type well region is formed in the N-type drift region, and the P-type well region is formed in the N-type drift region. At least a first P-type highly doped region is formed in the well region, a second P-type highly doped region is formed in the P-type substrate, the first substrate electrode region is formed in the dielectric layer, and the second P-type highly doped region is formed in the P-type substrate. A substrate electrode region is in contact with the first P-type highly doped region, the second substrate electrode region is formed on the dielectric layer, and at least a portion of the second substrate electrode region passes through the dielectric The layer is in contact with the second P-type highly doped region, the P-type well region and the P-type substrate are separated by the N-type drift region, and an N-type well region is formed in the P-type well region, A first N-type highly doped region is formed in the N-type well region, the first N-type highly doped region and the P-type well region are separated by the N-type well region, and the N-type drift region A second N-type highly doped region is formed in the middle, the source region is formed on the dielectric layer, and at least a part of the source region passes through the dielectric layer and the first N-type highly doped region contact, the drain region is formed on the dielectric layer, at least a part of the drain region is in contact with the second N-type highly doped region through the dielectric layer, and the gate region is formed on the dielectric layer In the dielectric layer, a first isolation medium is formed between at least a part of the gate region and at least a part of the first N-type highly doped region, and at least another part of the gate region is connected to the second A first isolation medium is also formed between at least a part of the N-type highly doped region, and a second isolation medium is formed at least between the first P-type highly doped region and the second P-type highly doped region , a second isolation medium is also formed outside the second N-type highly doped region, between the dielectric layer and the P-type substrate.

10. The semiconductor device according to claim 1 or 2, wherein the first field effect transistor is a PMOS transistor;

The first cell region includes a source region, a substrate electrode region, a gate region and a drain region, and the substrate electrode region includes a first substrate electrode region and a second substrate electrode region; the first substrate electrode region The cell region includes an N-type substrate and a dielectric layer, at least a P-type drift region is formed between the N-type substrate and the dielectric layer, an N-type well region is formed in the P-type drift region, and the N-type drift region is formed. At least a first N-type highly doped region is formed in the well region, a second N-type highly doped region is formed in the N-type substrate, the first substrate electrode region is formed in the dielectric layer, and the first N-type highly doped region is formed. A substrate electrode region is in contact with the first N-type highly doped region, the second substrate electrode region is formed on the dielectric layer, and at least a portion of the second substrate electrode region passes through the dielectric The layer is in contact with the second N-type highly doped region, the N-type well region and the N-type substrate are separated by the P-type drift region, and a P-type well region is formed in the N-type well region, A first P-type highly doped region is formed in the P-type well region, the first P-type highly doped region and the N-type well region are separated by the P-type well region, and the P-type drift region A second P-type highly doped region is formed in the middle, the source region is formed on the dielectric layer, and at least a part of the source region passes through the dielectric layer and the first P-type highly doped region contact, the drain region is formed on the dielectric layer, at least a part of the drain region is in contact with the second P-type highly doped region through the dielectric layer, and the gate region is formed on the dielectric layer. in the dielectric layer.