CN112272043A

CN112272043A - Wireless Communication Circuits That Reduce Interference

Info

Publication number: CN112272043A
Application number: CN202011172814.5A
Authority: CN
Inventors: 颜文; 刘钊; 张书会; 张立; 施子韬; 韩洪征; 宋永华
Original assignee: Bouffalo Lab Nanjing Co ltd
Current assignee: Bouffalo Lab Nanjing Co ltd
Priority date: 2020-10-28
Filing date: 2020-10-28
Publication date: 2021-01-26
Anticipated expiration: 2040-10-28
Also published as: CN112272043B

Abstract

The invention discloses a wireless communication circuit with reduced interference. The wireless communication circuit with reduced interference includes: a circuit board, a chip and a crystal; the circuit board is provided with a first ground port and at least two second ground ports; the chip A third ground port is provided, the third ground port is connected to the first ground port of the circuit board; the chip includes a crystal oscillator; the crystal is provided with a fourth ground port, and the fourth ground port can be connected to the circuit board A second ground port of the crystal; the crystal can select different second ground ports, and selecting different second ground ports can make the external environment interfere with the crystal oscillator differently. The wireless communication circuit for reducing interference proposed by the present invention separates the ground of the chip and the ground of the crystal, selects the ground point of the crystal flexibly, and finally reduces the interference of the external environment to the crystal oscillator.

Description

Interference reducing wireless communication circuit

Technical Field

The invention belongs to the technical field of electronic circuits, relates to a wireless communication circuit, and particularly relates to a wireless communication circuit for reducing interference.

Background

With the progress of the times, the science and technology are rapidly developed and gradually integrated into the lives of people. And the pursuit of miniaturization and even miniaturization of devices therein is becoming more urgent.

Miniaturization and even miniaturization of electronic devices presents unprecedented challenges and challenges to the design of radio frequency systems. The area of the circuit board becomes smaller, and along with the shortage of routing resources and the complexity of the layout of the electronic components increase sharply, the electronic components which originally have electromagnetic interference have to be put together to improve the integration level. Typical miniaturized devices such as wireless bluetooth headsets have to put down passive components such as bluetooth chips, power management chips, and even audio chips, not to mention the resistance, capacitance, and inductance present with these chips, in an extremely narrow space. More challenging is that the number of pins of the chip is not decreased or increased in order to obtain more functions and more excellent performance, which results in more electronic components to be accommodated in a narrow space.

As the size of the printed circuit board PCB decreases, the ground layout of the entire circuit board will become less robust, which will result in greater jitter on the ground, making the chip more susceptible to interference. Furthermore, to save costs, more and more products use 2-layer boards and the ground layout will become more difficult.

In a wireless communication system, two components, namely, a crystal or a crystal oscillator and an antenna or an antenna array, which are most important and indispensable, except for a chip, mutual disturbance between the two components becomes stronger and stronger along with reduction of the size of a PCB and reduction of the number of layers, which slightly affects radio frequency performance, such as sensitivity of a receiver and error vector magnitude EVM of a transmitter, and heavily causes the whole communication system to be incapable of working normally. Of course, digital systems, such as FLASH memory devices FLASH and chip, conventional serial communication UART, etc., can also interfere with the rf communication system. It becomes important how to effectively reduce the mutual interference between them.

Due to the large voltage swing of the output signal, the power amplifier usually has a part of energy transferred to the ground of the whole PCB. The ground wires at different positions are disturbed in different sizes and different disturbing phases. As shown in FIG. 1, the region shows an internal crystal oscillator circuit of a chip, and the region shows a simplified model of an external crystal. Wherein R is_fbIs a feedback resistor of the inverter and provides a suitable dc bias voltage for the inverter. C_L1And C_L2Is the on-chip load capacitance of the crystal oscillator. L0, L1 and L2 are inductors wired from the PADs PAD inside the chip to the corresponding PIN PINs of the chip package, and the inductance values of these several inductors may be different. R1 and R2 are series resistors added on two PIN PINs of the crystal oscillator on the PCB, and the two resistors can be different in resistance value, or only one resistor or one resistor is not added. C_p1,C_p2The chip external crystal oscillator is characterized in that all capacitors on two pins of the chip external crystal oscillator include but are not limited to routing parasitic capacitors, external load capacitors, internal crystal parasitic capacitors and the like of the two pins on a PCB. Interference can often degrade the quality of the final power amplifier output signal through several scenarios.

(1) The interference enters the crystal oscillator through the ground wire GND _0 inside the chip and generates a spurious frequency related to the frequency of the power amplifier and the frequency of the local oscillator at the output of the crystal oscillator, and the spurious frequency can influence the quality of the output signal of the local oscillator, thereby influencing the final EVM

(2) The interference enters the crystal oscillator inside the chip through the ground GND _1 of the crystal, and generates a spurious frequency at the output of the crystal oscillator related to the power amplifier frequency and the local oscillator frequency, thereby affecting the final EVM

To reduce the influence of the external environment on the crystal oscillator, the crystal is usually placed as close to the chip as possible. Based on this layer of consideration, the ground lines of the crystal and the chip are usually connected together, and there will be a certain randomness in the interference of the whole system through the two ground lines, for example, the parasitic capacitances are different, the sizes of the boards are different, and the quality of the final output rf signal may be deteriorated due to the different thicknesses and lengths of the connection lines between the chip ground line and the crystal ground line.

The conventional solutions generally have the following solutions:

(1) and the multilayer PCB layout wiring is adopted, so that the ground wire of the whole chip is stable enough, and the output signal of the power amplifier is reduced from being interfered to the ground wire so as to reduce the interference of the output signal of the power amplifier on the crystal oscillator. This approach significantly increases hardware costs relative to a two-layer PCB.

(2) The size of the PCB is increased, so that the feed point of the antenna is far away from the chip and the crystal, and the crosstalk of the power amplifier to the two ground wires is reduced. This approach, limited to the size of the PCB board, is less and less suited to the general trend of miniaturized designs.

(3) By adding the resistors R1 and R2, interference is blocked from entering the crystal oscillator from the outside, and simultaneously the impedance seen by the chip internal node of the crystal oscillator to the outside of the chip is increased, so that the input and output of the illustrated inverter swing along with GND _0, and the interference is changed into common mode noise to eliminate the influence of the common mode noise. The resistor is added on the crystal pin, so that the power consumption of the circuit is increased if the resistor is light, and the crystal oscillator does not start to vibrate if the resistor is heavy, thereby causing fatal functional defects.

(4) By adding external capacitance (as C)_p1,C_p2Part of) the output signal, forcing GND _0 to be common with GND _1, can also cause the interference of the ground line to appear as common mode noise to the crystal oscillator, thereby eliminating its effect on the output signal. However, the external load capacitor increases the area of the PCB and increases the cost of the entire hardware design.

In view of the above, there is a need to design a new wireless communication circuit to overcome at least some of the above-mentioned disadvantages of the existing wireless communication circuits.

Disclosure of Invention

The invention provides a wireless communication circuit capable of reducing interference, which can flexibly select the grounding point of a crystal, finally reduce the interference of an external environment on a crystal oscillator and reduce the cost of a product.

In order to solve the technical problem, according to one aspect of the present invention, the following technical solutions are adopted:

a wireless communication circuit to reduce interference, the wireless communication circuit comprising:

the circuit board is provided with a first grounding port and at least two second grounding ports;

the chip is provided with a third grounding port, and the third grounding port is connected with the first grounding port of the circuit board; the chip comprises a crystal oscillator;

the crystal is provided with a fourth grounding port, and the fourth grounding port can be connected with a second grounding port of the circuit board; the crystal can select different second ground ports, and the selection of different second ground ports can enable the interference of the external environment to the crystal oscillator to be different.

As an embodiment of the present invention, after the fourth ground port is connected to the corresponding second ground port through a wire, the connecting wire is equivalent to an inductor and a capacitor connected in parallel;

the set second grounding port is connected with the fourth grounding port, so that the interference quantity at two ends of the crystal oscillator is the same as the interference quantity on the first grounding port in amplitude and phase.

As an embodiment of the invention, the crystal oscillator comprises an inverter, a feedback resistor; the crystal oscillator is provided with an on-chip load capacitor which comprises a first capacitor and a second capacitor; the inductor is connected with the corresponding pin of the chip package from a bonding pad inside the chip, and comprises a first inductor, a second inductor and a third inductor;

the input end of the phase inverter is respectively connected with the first end of the feedback resistor, the first end of the first capacitor and the first end of the first inductor; the output end of the phase inverter is respectively connected with the second end of the feedback resistor, the first end of the second capacitor and the first end of the third inductor;

the second end of the first capacitor and the second end of the second capacitor are respectively connected with the first end of the second inductor; and the second end of the second inductor is grounded.

As an embodiment of the present invention, all the capacitors of the two pins of the crystal are respectively a third capacitor and a fourth capacitor; the connecting lead is equivalent to a fifth capacitor and a fourth inductor;

the first end of the crystal is connected with the first end of the third capacitor, and the second end of the crystal is connected with the first end of the fourth capacitor;

the second end of the third capacitor is respectively connected with the second end of the fourth capacitor, the first end of the fifth capacitor and the first end of the fourth inductor; and the second end of the fifth capacitor and the second end of the fourth inductor are respectively grounded.

all capacitors of the two pins of the crystal are respectively a third capacitor and a fourth capacitor; the connecting lead is equivalent to a fifth capacitor and a fourth inductor;

the second end of the first capacitor and the second end of the second capacitor are respectively connected with the first end of the second inductor; the second end of the second inductor is grounded;

the second end of the first inductor is respectively connected with the first end of the crystal and the first end of the third capacitor, and the second end of the third inductor is respectively connected with the second end of the crystal and the first end of the fourth capacitor;

As an embodiment of the present invention, the wireless communication circuit includes an antenna, the chip is connected to the antenna, and one end of the antenna is grounded.

As an embodiment of the invention, the plurality of second ground ports of the circuit board have radio frequency signal components with substantially uniform amplitudes (with amplitude differences within a predetermined range) but different phases.

As an embodiment of the present invention, the chip includes a power amplifier.

The invention has the beneficial effects that: the wireless communication circuit for reducing the interference separates the ground of the chip from the ground of the crystal, flexibly selects the grounding point of the crystal, and finally reduces the interference of the external environment to the crystal oscillator.

The invention can be applied to any scene using the crystal oscillator and is not changed along with the change of the type, the layer number and the size of the PCB. The invention has extremely high flexibility, provides the maximum degree of freedom for the design of the PCB, and finally shows that the size of the PCB is reduced, the cost of the whole scheme is reduced, and the like.

Compared with the scheme of adding the resistor in the signal path, the invention has no influence on the starting oscillation of the crystal oscillator and does not increase the power consumption. Compared with the externally-hung capacitor scheme, the invention does not need additional material cost, thereby saving the wiring resource of the PCB and reducing the scheme cost.

Drawings

Fig. 1 is a simplified model diagram of a conventional crystal oscillator circuit.

Fig. 2 is a schematic diagram of a wireless communication circuit according to an embodiment of the invention.

Fig. 3 is a simplified model diagram of a wireless communication circuit according to an embodiment of the present invention.

Detailed Description

Preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

For a further understanding of the invention, reference will now be made to the preferred embodiments of the invention by way of example, and it is to be understood that the description is intended to further illustrate features and advantages of the invention, and not to limit the scope of the claims.

The description in this section is for several exemplary embodiments only, and the present invention is not limited only to the scope of the embodiments described. It is within the scope of the present disclosure and protection that the same or similar prior art means and some features of the embodiments may be interchanged.

"coupled" in this specification includes both direct and indirect connections, such as through some active device, passive device, or electrically conductive medium; but also may include connections through other active or passive devices, such as through switches, follower circuits, etc., that are known to those skilled in the art for achieving the same or similar functional objectives.

Fig. 2 is a schematic diagram of a wireless communication circuit according to an embodiment of the present invention, and fig. 3 is a simplified model of the wireless communication circuit according to an embodiment of the present invention; referring to fig. 2 and 3, the wireless communication circuit includes a circuit board (PCB)1, a chip 2 and a crystal 3. The circuit board 1 is provided with a first ground port and at least two second ground ports. The chip 2 is provided with a third ground port GND _0, and the third ground port GND _0 is connected with the first ground port of the circuit board 1; the chip 2 comprises a crystal oscillator 21. The crystal 3 is provided with a fourth ground port GND _1, and the fourth ground port GND _1 can be connected with a second ground port of the circuit board 1; the crystal 3 can select different second ground ports, and the selection of different second ground ports can cause different interference of the external environment on the crystal oscillator. In one embodiment, the external environment refers to a signal external to the crystal oscillator, such as a disturbance entering the crystal oscillator through the chip internal ground GND _0, such as a disturbance entering the crystal oscillator inside the chip through the crystal ground GND _ 1.

In an embodiment of the invention, the second ground ports of the circuit board 1 have radio frequency signal components with substantially identical amplitudes (with amplitude differences within a predetermined range) but different phases.

As shown in fig. 2, in an embodiment of the present invention, the wireless communication circuit includes an antenna 4, the chip 2 is connected to the antenna 4, and one end of the antenna 4 is grounded. Furthermore, the chip 2 may also comprise a power amplifier.

In an embodiment of the invention, after the fourth ground port GND _1 is connected to the corresponding second ground port through a conducting wire, the connecting conducting wire is equivalent to an inductor and a capacitor connected in parallel; the set second ground port is connected with the fourth ground port GND _1, so that the interference amount at two ends of the crystal oscillator 21 is the same as the interference amount on the third ground port GND _0 in amplitude and phase.

Referring to fig. 3, in an embodiment of the invention, the crystal oscillator 21 includes an inverter 210 and a feedback resistor R_fb(ii) a The crystal oscillator 21 is provided with an on-chip load capacitor including a first capacitor C_L1A second capacitor C_L2(ii) a The inductor connected to the corresponding pin of the chip package from the internal pad of the chip comprises a first inductor L1, a second inductor L0 and a third inductor L2. The input ends of the phase inverters 210 are respectively connected with feedback resistors R_fbFirst terminal, first capacitor C_L1A first terminal of a first inductor L1; the output end of the phase inverter 210 is connected with a feedback resistor R respectively_fbSecond terminal, second capacitor C_L2A first terminal of the third inductor L2. The first capacitor C_L1Second terminal, second capacitor C_L2Are respectively connected with the first end of the second inductor L0; the second end of the second inductor L0 is grounded.

Referring to fig. 3, in an embodiment, all the capacitors of the two pins of the crystal 3 are respectively the third capacitors C_p1A fourth capacitor C_p2(ii) a The connecting wire is equivalent to a fifth capacitor C_eqAnd a fourth inductance L_eq. A second end of the first inductor L1 is connected to a first end of the crystal 3 and a third capacitor C respectively_p1And second ends of the third inductors L2 are respectively connected toA second terminal of the crystal 3, and a fourth capacitor C_p2The first end of (a). The third capacitor C_p1Second ends of the first and second capacitors are respectively connected with a fourth capacitor C_p2Second terminal, fifth capacitor C_eqFirst terminal, fourth inductance C_p2A first end of (a); the fifth capacitor C_eqSecond terminal, fourth inductance L_eqRespectively, to ground.

In summary, the wireless communication circuit for reducing interference provided by the invention separates the ground of the chip from the ground of the crystal, flexibly selects the grounding point of the crystal, and finally reduces the interference of the external environment to the crystal oscillator.

The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The description and applications of the invention herein are illustrative and are not intended to limit the scope of the invention to the embodiments described above. Effects or advantages referred to in the embodiments may not be reflected in the embodiments due to interference of various factors, and the description of the effects or advantages is not intended to limit the embodiments. Variations and modifications of the embodiments disclosed herein are possible, and alternative and equivalent various components of the embodiments will be apparent to those skilled in the art. It will be clear to those skilled in the art that the present invention may be embodied in other forms, structures, arrangements, proportions, and with other components, materials, and parts, without departing from the spirit or essential characteristics thereof. Other variations and modifications of the embodiments disclosed herein may be made without departing from the scope and spirit of the invention.

Claims

1. A wireless communication circuit for reducing interference, wherein the wireless communication circuit comprises:

The circuit board is provided with a first ground port and at least two second ground ports;

The chip is provided with a third ground port, and the third ground port is connected to the first ground port of the circuit board; the chip includes a crystal oscillator;

The crystal is provided with a fourth ground port, and the fourth ground port can be connected to a second ground port of the circuit board; the crystal can select different second ground ports, and the selection of different second ground ports can make the external environment The interference of crystal oscillators is different.

2. The wireless communication circuit for reducing interference according to claim 1, wherein:

After the fourth grounding port is connected with the corresponding second grounding port through a wire, the connecting wire is equivalent to a parallel inductance and capacitance;

The set second ground port is connected to the fourth ground port, so that the interference amount at both ends of the crystal oscillator has the same amplitude and the same phase as the interference amount on the third ground port.

3. The wireless communication circuit for reducing interference according to claim 1, wherein:

The crystal oscillator includes an inverter and a feedback resistor; the crystal oscillator is provided with an on-chip load capacitor, including a first capacitor and a second capacitor; the inductance connecting the internal pad of the chip to the corresponding pin of the chip package, including a first inductor, a second inductor and a third inductor;

The input end of the inverter is respectively connected to the first end of the feedback resistor, the first end of the first capacitor and the first end of the first inductor; the output end of the inverter is respectively connected to the second end of the feedback resistor, the first end of the second capacitor and the first end of the third inductor;

The second end of the first capacitor and the second end of the second capacitor are respectively connected to the first end of the second inductor; the second end of the second inductor is grounded.

4. The wireless communication circuit for reducing interference according to claim 2, wherein:

All capacitors of the two pins of the crystal are respectively the third capacitor and the fourth capacitor; the connecting wires are equivalent to the fifth capacitor and the fourth inductor;

The first end of the crystal is connected to the first end of the third capacitor, and the second end of the crystal is connected to the first end of the fourth capacitor;

The second terminal of the third capacitor is respectively connected to the second terminal of the fourth capacitor, the first terminal of the fifth capacitor, and the first terminal of the fourth inductor; the second terminal of the fifth capacitor and the first terminal of the fourth inductor are respectively connected. The two ends are grounded respectively.

5. The wireless communication circuit for reducing interference according to claim 2, wherein:

All capacitors of the two pins of the crystal are respectively the third capacitor and the fourth capacitor; the connecting wire is equivalent to the fifth capacitor and the fourth inductance;

The second end of the first capacitor and the second end of the second capacitor are respectively connected to the first end of the second inductor; the second end of the second inductor is grounded;

The second end of the first inductor is respectively connected to the first end of the crystal and the first end of the third capacitor, and the second end of the third inductor is respectively connected to the second end of the crystal and the fourth capacitor. first end;

6. The wireless communication circuit for reducing interference according to claim 1, wherein:

The wireless communication circuit includes an antenna, the chip is connected to the antenna, and one end of the antenna is grounded.

7. The wireless communication circuit for reducing interference according to claim 1, wherein:

Several second ground ports of the circuit board have radio frequency signal components with amplitude differences within a predetermined range but different phases.

8. The wireless communication circuit for reducing interference according to claim 1, wherein:

The chip includes a power amplifier.