[go: up one dir, main page]

CN112271211B - Terminal structure of sectional type composite field plate - Google Patents

Terminal structure of sectional type composite field plate Download PDF

Info

Publication number
CN112271211B
CN112271211B CN202011201439.2A CN202011201439A CN112271211B CN 112271211 B CN112271211 B CN 112271211B CN 202011201439 A CN202011201439 A CN 202011201439A CN 112271211 B CN112271211 B CN 112271211B
Authority
CN
China
Prior art keywords
polysilicon
field plate
ring
short
injection area
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202011201439.2A
Other languages
Chinese (zh)
Other versions
CN112271211A (en
Inventor
刘琦
杨乐
刘雯娇
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Longteng Semiconductor Co ltd
Original Assignee
Longteng Semiconductor Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Longteng Semiconductor Co ltd filed Critical Longteng Semiconductor Co ltd
Priority to CN202011201439.2A priority Critical patent/CN112271211B/en
Publication of CN112271211A publication Critical patent/CN112271211A/en
Application granted granted Critical
Publication of CN112271211B publication Critical patent/CN112271211B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/111Field plates
    • H10D64/112Field plates comprising multiple field plate segments
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/124Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions

Landscapes

  • Electrodes Of Semiconductors (AREA)

Abstract

本发明提出一种分段式复合场板的终端结构,隶属于功率半导体器件技术领域。本发明包括环注入区、多晶硅、短场板、接触孔、以及截止环金属;环注入区位于栅极引线外侧,多晶硅位于环注入区外侧;环注入区和多晶硅重复排布多组;截止环金属在最后一个多晶硅外侧,是芯片最外面一圈结构;短场板在环注入区和多晶硅上面,通过接触孔实现和环注入区的连接;短场板在多晶硅的上面阵列式排列形成多晶硅和短场板的阵列区。该结构解决了在实现金属场板和场限环的连接时会遇到场限环间距太近、接触孔和金属边缘距离不够、导致金属间距不能满足金属湿法刻蚀工艺要求的问题,在有限的终端面积上实现了更高的耐压,同时还提高了器件抗热应力的能力。

The invention proposes a terminal structure of a segmented composite field plate, which belongs to the technical field of power semiconductor devices. The invention includes a ring injection area, polysilicon, a short field plate, a contact hole, and a cutoff ring metal; the ring injection area is located outside the gate lead, and the polysilicon is located outside the ring injection area; the ring injection area and the polysilicon are repeatedly arranged in multiple groups; and the cutoff ring The metal is outside the last polysilicon, which is the outermost structure of the chip; the short field plate is on the ring injection area and the polysilicon, and is connected to the ring injection area through the contact hole; the short field plate is arranged in an array on the polysilicon to form the polysilicon and Array area of short field plate. This structure solves the problem that when realizing the connection between the metal field plate and the field limiting ring, the distance between the field limiting ring is too close, the distance between the contact hole and the metal edge is not enough, resulting in the metal spacing not meeting the requirements of the metal wet etching process. In the limited A higher withstand voltage is achieved on the terminal area, while also improving the device's ability to withstand thermal stress.

Description

分段式复合场板的终端结构Segmented Composite Field Slab Terminal Structure

技术领域Technical field

本发明涉及功率半导体器件技术领域,具体涉及一种分段式复合场板的终端结构。The invention relates to the technical field of power semiconductor devices, and in particular to a terminal structure of a segmented composite field plate.

背景技术Background technique

随着功率半导体器件不断向高电压、大电流的方向发展,对器件结构、工艺、可靠性要求也越来越高。As power semiconductor devices continue to develop toward high voltage and high current, the requirements for device structure, process, and reliability are getting higher and higher.

在高压器件终端保护中常用到的一种结构是场限环、多晶场板、金属场板相结合的复合终端技术,可以有效提高器件耐压。为了保证器件可靠性常使用偏置场板即通过接触孔将金属场板和场限环连接起来。由于器件耐压越高需要设计场限环和金属场板个数越多,在实现金属场板和场限环的连接时会遇到场限环间距太近,接触孔和金属边缘距离不够,导致金属间距不能满足金属湿法刻蚀工艺要求的问题。如图1所示,现有技术是在芯片的四个角上做接触孔将金属场板和场限环连接起来,通过将场限环宽度加大获得足够距离实现偏置场板。这样设计存在的问题是场限环曲率半径减小,器件耐压相对降低。A structure commonly used in terminal protection of high-voltage devices is composite terminal technology that combines field limiting rings, polycrystalline field plates, and metal field plates, which can effectively improve device withstand voltage. In order to ensure the reliability of the device, a bias field plate is often used to connect the metal field plate and the field limiting ring through contact holes. Since the higher the withstand voltage of the device, the more field limiting rings and metal field plates need to be designed. When connecting the metal field plates and field limiting rings, the distance between the field limiting rings will be too close, and the distance between the contact holes and the metal edge will not be enough, resulting in The metal spacing cannot meet the requirements of the metal wet etching process. As shown in Figure 1, the existing technology is to make contact holes at the four corners of the chip to connect the metal field plate and the field limiting ring. By increasing the width of the field limiting ring, sufficient distance is obtained to realize the biased field plate. The problem with this design is that the curvature radius of the field limiting ring is reduced, and the device withstand voltage is relatively reduced.

发明内容Contents of the invention

本发明的目的是提供一种分段式复合场板的终端结构,解决了现有技术中存在的问题。The purpose of the present invention is to provide a terminal structure of a segmented composite field plate to solve the problems existing in the prior art.

本发明所采用的技术方案为:The technical solutions adopted by the present invention are:

一种分段式复合场板的终端结构,其特征在于:A terminal structure of a segmented composite field plate, which is characterized by:

所述结构包括环注入区、多晶硅、短场板、接触孔、以及截止环金属;The structure includes a ring injection region, polysilicon, a short field plate, a contact hole, and a cutoff ring metal;

所述环注入区位于栅极引线外侧,多晶硅位于环注入区外侧;环注入区和多晶硅重复排布多组;The ring injection area is located outside the gate lead, and the polysilicon is located outside the ring injection area; the ring injection area and the polysilicon are repeatedly arranged in multiple groups;

所述截止环金属在最后一个多晶硅外侧,是芯片最外面一圈结构;The cutoff ring metal is outside the last polysilicon and is the outermost ring structure of the chip;

所述短场板在环注入区和多晶硅上面,通过接触孔实现和环注入区的连接;短场板在多晶硅的上面阵列式排列形成多晶硅和短场板的阵列区。The short field plates are on the ring injection area and polysilicon, and are connected to the ring injection area through contact holes; the short field plates are arranged in an array on the polysilicon to form an array area of polysilicon and short field plates.

多晶硅和短场板的阵列式排列形成分段式复合场板。The array arrangement of polysilicon and short field plates forms a segmented composite field plate.

阵列式排列是指在多晶硅和短场板的阵列区中,沿X轴方向,短场板和短场板错位且间隔布置;沿Y轴方向,多晶硅和短场板间隔布置。The array arrangement means that in the array area of polysilicon and short field plates, the short field plates and short field plates are staggered and arranged at intervals along the X-axis direction; along the Y-axis direction, the polysilicon and short field plates are arranged at intervals.

短场板厚度大于多晶硅厚度。The short field plate thickness is greater than the polysilicon thickness.

短场板属于偏置场板,短场板在环注入区和多晶硅上面,通过接触孔和环注入区连接,并且该接触孔位于芯片平边位置。The short field plate is a bias field plate. The short field plate is on the ring injection area and the polysilicon, and is connected to the ring injection area through a contact hole, and the contact hole is located at the flat edge of the chip.

短场板沿X轴的间距大于短场板的长度。The spacing of the short field plates along the X-axis is greater than the length of the short field plates.

短场板沿Y轴的间距小于短场板的宽度。The spacing of the short field plates along the Y-axis is smaller than the width of the short field plates.

截止环金属下面有环注入区,该环注入区不同于其它环注入区,作用是形成截止环。There is a ring injection area under the cutoff ring metal. This ring injection area is different from other ring injection areas and functions to form a cutoff ring.

本发明具有以下优点:The invention has the following advantages:

本发明在现有技术的基础上,通过采用分段式复合场板即多晶硅和短场板的阵列式排列,使得金属条宽度打破刻蚀间距限制,金属间距完全满足金属湿法刻蚀工艺要求。本发明提出的结构将现有技术金属场板和场限环的接触孔由芯片的四个角设计到芯片的平边,保证场限环设计的一致性。在有限的终端面积上实现了更高的耐压,最终使相同面积的器件具有更高的耐压。另外,本发明涉及的结构从两方面提高器件可靠性,第一,现有技术为金属场板改进后的新型设计是分段式复合场板,一个个短场板可以分散金属场板受到的力,使塑封料和芯片表面间应力减小,提高器件在热循环过程中承受热应力的能力;第二,本发明中涉及的接触孔作用是实现偏置场板,可以使器件具有更高的稳定性,满足在150℃,100%BVDSS条件下的高温老炼考核。Based on the existing technology, the present invention uses segmented composite field plates, that is, an array arrangement of polysilicon and short field plates, so that the width of the metal strips breaks the etching spacing limit, and the metal spacing fully meets the requirements of the metal wet etching process. . In the structure proposed by the present invention, the contact holes of the existing metal field plates and field limiting rings are designed from the four corners of the chip to the flat sides of the chip, ensuring the consistency of the field limiting ring design. A higher withstand voltage is achieved in a limited terminal area, ultimately enabling devices with the same area to have higher withstand voltage. In addition, the structure involved in the present invention improves device reliability from two aspects. First, the new design improved from the existing metal field plate is a segmented composite field plate. Each short field plate can disperse the stress on the metal field plate. force, so that the stress between the plastic packaging material and the chip surface is reduced, and the device's ability to withstand thermal stress during the thermal cycle is improved; secondly, the function of the contact hole involved in the present invention is to realize a bias field plate, which can make the device have higher The stability satisfies the high-temperature aging assessment under 150℃ and 100% BV DSS conditions.

附图说明Description of the drawings

图1是现有技术芯片表面示意图;Figure 1 is a schematic diagram of the chip surface in the prior art;

图2是分段式复合场板的结构示意图Figure 2 is a schematic structural diagram of the segmented composite field plate.

图3是分段式复合场板的结构布版实例图;Figure 3 is an example of the structural layout of a segmented composite field plate;

图4是芯片表面受力分析示意图。Figure 4 is a schematic diagram of the stress analysis on the chip surface.

具体实施方式Detailed ways

下面结合实例对本发明具体实施方式进行详细的说明,本领域技术人员可由说明书所公开的内容轻易地了解本发明的优点、功效及设计方法。本发明还可以通过另外不同的具体实施方式加以实施或应用,可以基于本发明的设计思想进行修饰或同类型应用。Specific embodiments of the present invention will be described in detail below with reference to examples. Those skilled in the art can easily understand the advantages, effects and design methods of the present invention from the content disclosed in the specification. The present invention can also be implemented or applied through other different specific embodiments, and can be modified or applied in the same type based on the design concept of the present invention.

本发明不涉及工艺过程,与普通VDMOS工艺兼容,其结构主要通过版图布局实现,属于器件横向结构,纵向结构和功能并不改变。The present invention does not involve a process and is compatible with ordinary VDMOS processes. Its structure is mainly realized through layout, and it belongs to the horizontal structure of the device, and the vertical structure and function do not change.

如图3所示,本发明公开一种分段式复合场板的终端结构,所述结构包括环注入区、多晶硅、短场板、接触孔、以及截止环金属;该结构属于功率半导体器件的终端结构,一般器件由内向外依次是有源区,栅极引线,终端结构;本发明分段式复合场板的终端结构所指的环注入区位于栅极引线外侧;多晶硅位于环注入区外侧;环注入区和多晶硅重复排布多组;最后截止环金属在最后一个多晶硅外侧,是芯片最外面一圈结构;短场板在环注入区和多晶硅上面,通过接触孔实现和环注入区的连接。本发明的技术特征是发明了分段式复合场板,其特征在于短场板在多晶硅的上面阵列式排列形成多晶硅和短场板的阵列区。As shown in Figure 3, the present invention discloses a terminal structure of a segmented composite field plate. The structure includes a ring injection region, polysilicon, a short field plate, a contact hole, and a cutoff ring metal; this structure belongs to a power semiconductor device. The terminal structure of a general device is the active area, the gate lead, and the terminal structure in order from the inside to the outside; the ring injection area referred to in the terminal structure of the segmented composite field plate of the present invention is located outside the gate lead; the polysilicon is located outside the ring injection area ; The ring injection area and polysilicon are repeatedly arranged in multiple groups; the final cutoff ring metal is outside the last polysilicon, which is the outermost ring structure of the chip; the short field plate is on the ring injection area and polysilicon, and is connected to the ring injection area through contact holes connect. The technical feature of the present invention is the invention of a segmented composite field plate, which is characterized in that short field plates are arranged in an array on polysilicon to form an array area of polysilicon and short field plates.

该结构位于器件的终端区,版图设计同普通版图设计规则,先完成有源区元胞排布,然后布置栅极引线,再布置环注入区、多晶硅及短场板;环注入区位于栅极引线外侧;多晶硅位于环注入区外侧,环注入区和多晶硅重复排布5组,截止环金属在多晶硅外侧是芯片最外面一圈结构;短场板在环注入区和多晶硅上面,通过接触孔实现和环注入区的连接。截止环金属下面做一个环注入区,该环注入区不同于其它环注入区,作用是形成截止环。This structure is located in the terminal area of the device. The layout design is the same as the ordinary layout design rules. First, the active area cell arrangement is completed, then the gate leads are arranged, and then the ring injection area, polysilicon and short field plate are arranged; the ring injection area is located at the gate Outside the lead; polysilicon is located outside the ring injection area, and the ring injection area and polysilicon are arranged in 5 repeated groups. The cutoff ring metal is outside the polysilicon and is the outermost ring structure of the chip; the short field plate is above the ring injection area and polysilicon, and is implemented through contact holes and the connection to the ring injection zone. A ring injection area is made under the cutoff ring metal. This ring injection area is different from other ring injection areas and functions to form a cutoff ring.

短场板在多晶硅上面阵列式排列,排列方法如图3所示,在多晶硅和短场板的阵列区中,沿X轴方向,短场板和短场板错位且间隔布置;沿Y轴方向,多晶硅和短场板间隔布置。短场板长度30μm,短场板沿X轴的间距为1个短场板长度加2.5个金属湿法刻蚀工艺冗余。短场板沿Y轴的间距较灵活。The short field plates are arranged in an array on the polysilicon. The arrangement method is shown in Figure 3. In the array area of the polysilicon and short field plates, along the X-axis direction, the short field plates and short field plates are staggered and arranged at intervals; along the Y-axis direction , polysilicon and short field plates are spaced apart. The length of the short field plate is 30 μm, and the spacing between the short field plates along the X-axis is 1 short field plate length plus 2.5 metal wet etching process redundancies. The spacing of short field plates along the Y-axis is more flexible.

如图3实例中,短场板在X轴方向的间距S1为40μm。在Y轴方向的间距S2为19.2μm,距满足湿法刻蚀工艺线宽需要,使得有足够距离放置多晶硅和短场板,以及短场板和环注入区的接触孔,接触孔宽度为20μm。短场板的作用一是使得金属条Y方向宽度打破刻蚀间距限制,金属间距完全满足金属湿法刻蚀工艺要求。二是减小芯片表面应力,原理如图4所示,该结构把本来作用在金属场板上的力,分散到多个短场板上。As shown in the example of Figure 3, the spacing S1 of the short field plate in the X-axis direction is 40 μm. The spacing S2 in the Y-axis direction is 19.2 μm, which meets the line width requirements of the wet etching process, allowing sufficient distance to place polysilicon and short field plates, as well as short field plates and contact holes in the ring injection area. The width of the contact holes is 20 μm. . The first function of the short field plate is to make the width of the metal strip in the Y direction break the etching spacing limit, and the metal spacing fully meets the requirements of the metal wet etching process. The second is to reduce chip surface stress. The principle is shown in Figure 4. This structure distributes the force that originally acts on the metal field plate to multiple short field plates.

本发明的内容不限于实例所列举,本领域普通技术人员通过阅读本发明说明书而对本发明技术方案采取的任何等效的变换,均为本发明的权利要求所涵盖。The content of the present invention is not limited to the examples listed. Any equivalent transformations made to the technical solution of the present invention by those of ordinary skill in the art after reading the description of the present invention will be covered by the claims of the present invention.

Claims (6)

1.一种分段式复合场板的终端结构,其特征在于:1. A terminal structure of a segmented composite field plate, characterized by: 所述结构包括环注入区、多晶硅、短场板、接触孔、以及截止环金属;The structure includes a ring injection region, polysilicon, a short field plate, a contact hole, and a cutoff ring metal; 所述环注入区位于栅极引线外侧,多晶硅位于环注入区外侧;环注入区和多晶硅重复排布多组;The ring injection area is located outside the gate lead, and the polysilicon is located outside the ring injection area; the ring injection area and the polysilicon are repeatedly arranged in multiple groups; 所述截止环金属在最后一个多晶硅外侧,是芯片最外面一圈结构;The cutoff ring metal is outside the last polysilicon and is the outermost ring structure of the chip; 所述短场板在环注入区和多晶硅上面,通过接触孔实现和环注入区的连接;短场板在多晶硅的上面阵列式排列形成多晶硅和短场板的阵列区;The short field plates are on the ring injection area and polysilicon, and are connected to the ring injection area through contact holes; the short field plates are arranged in an array on the polysilicon to form an array area of polysilicon and short field plates; 多晶硅和短场板的阵列式排列形成分段式复合场板;The array arrangement of polysilicon and short field plates forms a segmented composite field plate; 阵列式排列是指在多晶硅和短场板的阵列区中,沿X轴方向,短场板和短场板错位且间隔布置;沿Y轴方向,多晶硅和短场板间隔布置。The array arrangement means that in the array area of polysilicon and short field plates, the short field plates and short field plates are staggered and arranged at intervals along the X-axis direction; along the Y-axis direction, the polysilicon and short field plates are arranged at intervals. 2.根据权利要求1所述的分段式复合场板的终端结构,其特征在于:2. The terminal structure of the segmented composite field plate according to claim 1, characterized in that: 短场板厚度大于多晶硅厚度。The short field plate thickness is greater than the polysilicon thickness. 3.根据权利要求2所述的分段式复合场板的终端结构,其特征在于:3. The terminal structure of the segmented composite field plate according to claim 2, characterized in that: 短场板属于偏置场板,短场板在环注入区和多晶硅上面,通过接触孔和环注入区连接,并且该接触孔位于芯片平边位置。The short field plate is a bias field plate. The short field plate is on the ring injection area and the polysilicon, and is connected to the ring injection area through a contact hole, and the contact hole is located at the flat edge of the chip. 4.根据权利要求3所述的分段式复合场板的终端结构,其特征在于:4. The terminal structure of the segmented composite field plate according to claim 3, characterized in that: 短场板沿X轴的间距大于短场板的长度。The spacing of the short field plates along the X-axis is greater than the length of the short field plates. 5.根据权利要求4所述的分段式复合场板的终端结构,其特征在于:5. The terminal structure of the segmented composite field plate according to claim 4, characterized in that: 短场板沿Y轴的间距小于短场板的宽度。The spacing of the short field plates along the Y-axis is smaller than the width of the short field plates. 6.根据权利要求5所述的分段式复合场板的终端结构,其特征在于:6. The terminal structure of the segmented composite field plate according to claim 5, characterized in that: 截止环金属下面有环注入区,该环注入区不同于其它环注入区,作用是形成截止环。There is a ring injection area under the cutoff ring metal. This ring injection area is different from other ring injection areas and functions to form a cutoff ring.
CN202011201439.2A 2020-11-02 2020-11-02 Terminal structure of sectional type composite field plate Active CN112271211B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202011201439.2A CN112271211B (en) 2020-11-02 2020-11-02 Terminal structure of sectional type composite field plate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202011201439.2A CN112271211B (en) 2020-11-02 2020-11-02 Terminal structure of sectional type composite field plate

Publications (2)

Publication Number Publication Date
CN112271211A CN112271211A (en) 2021-01-26
CN112271211B true CN112271211B (en) 2024-01-09

Family

ID=74345598

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202011201439.2A Active CN112271211B (en) 2020-11-02 2020-11-02 Terminal structure of sectional type composite field plate

Country Status (1)

Country Link
CN (1) CN112271211B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113764527B (en) * 2021-09-06 2023-03-24 华羿微电子股份有限公司 MOSFET device groove terminal and preparation method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101345254A (en) * 2007-07-12 2009-01-14 富士电机电子技术株式会社 Semiconductor device
CN101719509A (en) * 2009-11-10 2010-06-02 深圳深爱半导体有限公司 Vertical double-diffusion metal-oxide-semiconductor field effect transistor
CN104882382A (en) * 2015-05-19 2015-09-02 上海先进半导体制造股份有限公司 Mosfet terminal structure and manufacturing method thereof
CN108767002A (en) * 2018-08-02 2018-11-06 盛廷微电子(深圳)有限公司 A kind of terminal for semiconductor power device
CN110911475A (en) * 2019-10-30 2020-03-24 深圳深爱半导体股份有限公司 Transistor termination structure and method of making the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101345254A (en) * 2007-07-12 2009-01-14 富士电机电子技术株式会社 Semiconductor device
CN101719509A (en) * 2009-11-10 2010-06-02 深圳深爱半导体有限公司 Vertical double-diffusion metal-oxide-semiconductor field effect transistor
CN104882382A (en) * 2015-05-19 2015-09-02 上海先进半导体制造股份有限公司 Mosfet terminal structure and manufacturing method thereof
CN108767002A (en) * 2018-08-02 2018-11-06 盛廷微电子(深圳)有限公司 A kind of terminal for semiconductor power device
CN110911475A (en) * 2019-10-30 2020-03-24 深圳深爱半导体股份有限公司 Transistor termination structure and method of making the same

Also Published As

Publication number Publication date
CN112271211A (en) 2021-01-26

Similar Documents

Publication Publication Date Title
US11881484B2 (en) Semiconductor integrated circuit device
JP2973588B2 (en) MOS type semiconductor device
KR101319470B1 (en) Semiconductor device
US9337112B2 (en) Semiconductor device having test structure
CN112271211B (en) Terminal structure of sectional type composite field plate
CN108321187B (en) Terminal structure with groove
CN202948932U (en) Trench type IGBT layout structure
CN106024634A (en) Power transistor with electrostatic discharge protection diode structures, and manufacturing method thereof
CN114203824B (en) Super junction power semiconductor device and manufacturing method thereof
CN111146285B (en) Semiconductor power transistor and manufacturing method thereof
CN106847808A (en) A kind of domain structure for improving super node MOSFET UIS abilities
CN103531620A (en) Insulated gate bipolar translator (IGBT) chip based on N-type injection layers and manufacturing method thereof
CN114220853B (en) Power chip
CN117276335A (en) An enhanced GaN HEMT with decoupling reverse conduction capability and its manufacturing method
CN113270399B (en) Semiconductor device and design layout thereof
CN214043672U (en) Novel IGBT power semiconductor device
CN112531018A (en) Novel IGBT power semiconductor device
CN107256857B (en) Grid metal bus bar chip structure design and manufacturing method thereof
CN103578997A (en) Manufacturing method of LDMOS grid electrode and product
CN110867375B (en) LDMOS device and manufacturing method thereof
CN101692425A (en) Novel design method for ESD protection
CN212517213U (en) Novel micro-groove IGBT structure
KR100709431B1 (en) Semiconductor Device Including 6F2 Cell Structure
CN221994472U (en) High withstand voltage super junction terminal structure
CN115799309A (en) A SiC MOSFET structure with a backside superjunction layer

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant