CN112271161A - Method for improving Fin size of Fin type transistor - Google Patents
Method for improving Fin size of Fin type transistor Download PDFInfo
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- CN112271161A CN112271161A CN202011154128.5A CN202011154128A CN112271161A CN 112271161 A CN112271161 A CN 112271161A CN 202011154128 A CN202011154128 A CN 202011154128A CN 112271161 A CN112271161 A CN 112271161A
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- fin
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- silicon
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- 238000000034 method Methods 0.000 title claims abstract description 45
- 239000004065 semiconductor Substances 0.000 claims abstract description 58
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 37
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 37
- 239000010703 silicon Substances 0.000 claims abstract description 37
- 238000000137 annealing Methods 0.000 claims abstract description 12
- 238000005229 chemical vapour deposition Methods 0.000 claims abstract description 8
- 239000012530 fluid Substances 0.000 claims abstract description 8
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 claims abstract 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 26
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 24
- 238000006243 chemical reaction Methods 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical group N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 238000005520 cutting process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0193—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices the components including FinFETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Abstract
本发明提供一种改善鳍式晶体管Fin尺寸的方法，提供包含有多个Fin的第一半导体结构，Fin的顶部上形成有第一、第二硬掩膜层；Fin的侧壁形成有第一薄型氧化层；将多个Fin中的部分Fin连同其上的第一、第二硬掩膜层和薄型氧化层切除形成第二半导体结构；在第二半导体结构上形成一层硅缓冲层；采用流体化学气相沉积法在形成有硅缓冲层的第二半导体结构上覆盖一氧化硅层；对第二半导体结构进行退火。本发明在FinFET器件的制造过程中，为了避免在FCVD及后续退火制程对Fin的消耗，在Fin成型之后的FCVD制程之前，在Fin上形成一层硅缓冲层以此中和FCVD以及后续退火过程中对Fin的消耗，从而确保Fin的形貌与尺寸不受影响。
The present invention provides a method for improving the size of a fin transistor Fin, and provides a first semiconductor structure including a plurality of Fins, first and second hard mask layers are formed on the top of the Fins, and first and second hard mask layers are formed on the sidewalls of the Fins. A thin oxide layer; part of the Fins in the plurality of Fins together with the first and second hard mask layers and the thin oxide layer thereon are excised to form a second semiconductor structure; a silicon buffer layer is formed on the second semiconductor structure; using The fluid chemical vapor deposition method covers the silicon monoxide layer on the second semiconductor structure formed with the silicon buffer layer; and the second semiconductor structure is annealed. In the manufacturing process of the FinFET device, in order to avoid the consumption of Fin during the FCVD and subsequent annealing processes, a silicon buffer layer is formed on the Fin before the FCVD process after the Fin is formed to neutralize the FCVD and subsequent annealing processes. The consumption of Fin in the process ensures that the morphology and size of Fin are not affected.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for improving Fin size of a Fin transistor.
Background
Fin transistors (finfets) have become a popular advanced CMOS technology in recent years, which has the advantage of increasing transistor density and electrical performance compared to conventional devices. The morphology and size of the Fin in a device are critical to the electrical parameters of the device. The high temperature process after Fin formation affects the Fin shape and size, and after Fin formation, FCVD is performed directly, thereby consuming Fin during FCVD and the subsequent Anneal annex process, thereby changing Fin shape and size.
Therefore, a new method is needed to solve the above problems.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, the present invention is directed to a method for improving Fin size of a Fin-type transistor, so as to solve the problem in the prior art that after Fin formation in FinFET device fabrication, Fin consumption due to high temperature annealing causes changes in the shape and size of Fin.
To achieve the above and other related objects, the present invention provides a method for improving Fin size of a Fin transistor, the method comprising:
providing a first semiconductor structure comprising a plurality of Fins, wherein a first hard mask layer and a second hard mask layer are formed on the tops of the Fins; a first thin oxide layer is formed on the side wall of the Fin and the bottom of the first semiconductor structure between the Fin and the Fin;
step two, cutting off part of Fin in the multiple Fin together with the first hard mask layer, the second hard mask layer and the thin oxide layer to form a second semiconductor structure;
step three, forming a silicon buffer layer on the second semiconductor structure;
fourthly, covering a silicon oxide layer on the second semiconductor structure with the silicon buffer layer by adopting a fluid chemical vapor deposition method;
and fifthly, annealing the second semiconductor structure.
Preferably, in the first step, the first hard mask layer is formed on the top of the Fin, and the second hard mask layer is formed on the first hard mask layer.
Preferably, in the first step, the first hard mask layer is silicon oxide, and the second hard mask layer is silicon nitride.
Preferably, the reaction temperature for forming the silicon buffer layer on the second semiconductor structure in the third step is 300-400 ℃.
Preferably, the source gas used in the third step of forming the silicon buffer layer on the second semiconductor structure is disilane.
Preferably, the thickness of the silicon buffer layer formed on the second semiconductor structure in the third step is 1 to 3 nm.
Preferably, a second thin oxide layer is formed on the silicon buffer layer of the second semiconductor structure before the fluid chemical vapor deposition process is performed in step four.
Preferably, the method further comprises a sixth step of removing the first and second hard mask layers on top of the Fin.
Preferably, the method further comprises a seventh step of back etching the silicon oxide layer.
As described above, the method for improving Fin size of a Fin transistor according to the present invention has the following advantages: in the manufacturing process of the FinFET device, in order to avoid the consumption of Fin in the FCVD and the subsequent annealing process, a silicon buffer layer is formed on the Fin before the FCVD process after Fin forming so as to neutralize the consumption of Fin in the FCVD and the subsequent annealing process, thereby ensuring that the shape and the size of Fin are not influenced.
Drawings
FIG. 1 is a schematic diagram illustrating a vertical cross-sectional structure of a second semiconductor structure according to the present invention;
FIG. 2 is a schematic diagram of a second semiconductor structure having a silicon buffer layer formed thereon according to the present invention;
FIG. 3 is a schematic diagram of a silicon oxide layer formed by FCVD on a second semiconductor according to the present invention;
FIG. 4 is a schematic structural diagram of a second semiconductor after etchback of silicon oxide in accordance with the present invention;
fig. 5 is a flowchart illustrating a method for improving Fin size of a Fin transistor according to the present invention.
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 5. It should be noted that the drawings provided in the present embodiment are only for illustrating the basic idea of the present invention, and the components related to the present invention are only shown in the drawings rather than drawn according to the number, shape and size of the components in actual implementation, and the type, quantity and proportion of the components in actual implementation may be changed freely, and the layout of the components may be more complicated.
Fig. 5 shows a flowchart of a method for improving Fin size of a Fin transistor according to the present invention, and fig. 5 shows a flowchart of the method for improving Fin size of a Fin transistor according to the present invention. The method at least comprises the following steps:
providing a first semiconductor structure comprising a plurality of Fins, wherein a first hard mask layer and a second hard mask layer are formed on the tops of the Fins; a first thin oxide layer is formed on the side wall of the Fin and the bottom of the first semiconductor structure between the Fin and the Fin; in the first step, the first hard mask layer is formed on the top of the Fin, and the second hard mask layer is formed on the first hard mask layer. In the first step, the first hard mask layer is silicon oxide, and the second hard mask layer is silicon nitride.
As shown in fig. 1, fig. 1 is a schematic longitudinal sectional structure of a second semiconductor structure according to the present invention. The second semiconductor structure is formed after the first semiconductor structure cuts off a part of Fin, in fig. 1, the first semiconductor structure includes a plurality of fins (i.e., Fin structure 01 in the Fin transistor in fig. 1), in the first semiconductor structure, a first hard mask layer 03 is formed on the top of the Fin (Fin structure 01), further, the first hard mask layer 03 in this embodiment is silicon oxide; forming a second hard mask layer 04 on the first hard mask layer on the Fin; in yet another embodiment of the present invention, the second hard mask layer 04 is silicon nitride.
In this embodiment, a first thin oxide layer (liner oxide)02 is formed on a sidewall of the Fin (Fin structure 01) in the first semiconductor structure; as shown in fig. 1, the first thin oxide layer (liner oxide)02 is also formed on the bottom of the first semiconductor structure between the Fin and the Fin.
Step two, cutting off part of Fin in the multiple Fin together with the first hard mask layer, the second hard mask layer and the thin oxide layer to form a second semiconductor structure; as shown in fig. 1, fig. 1 exemplarily discloses that a portion Fin in the first semiconductor structure is cut, for example, two fins located at the right side of the third Fin in fig. 1 are cut, and the positions and the number of the cut fins are not limited in other embodiments. Part of the Fin in the first semiconductor structure is cut off to form the second semiconductor structure in FIG. 2 because the part is not needed in the subsequent process.
Step three, forming a silicon buffer layer on the second semiconductor structure; further, in the third step of the present embodiment, the reaction temperature for forming the silicon buffer layer on the second semiconductor structure is 300-400 ℃. Still further, in the third step of the present invention, the source gas for forming the silicon buffer layer on the second semiconductor structure is disilane. Furthermore, in the third step of the present embodiment, the thickness of the silicon buffer layer formed on the second semiconductor structure is 1 to 3 nm.
As shown in fig. 2, fig. 2 is a schematic structural diagram illustrating a silicon buffer layer formed on a second semiconductor structure according to the present invention. That is, in the third step of this embodiment, at a reaction temperature of 300 to 400 ℃, disilane is used as a reaction source gas, the silicon buffer layer 05 is formed on the second semiconductor, the silicon buffer layer 05 covers the first thin oxide layer 02, the sidewall of the first hard mask layer 03, the sidewall of the second hard mask layer 04, the upper surface of the second hard mask layer 04, and the silicon buffer layer 05 covers the upper surface of the cut-off Fin.
Fourthly, covering a silicon oxide layer on the second semiconductor structure with the silicon buffer layer by adopting a fluid chemical vapor deposition method; as shown in fig. 3, fig. 3 is a schematic structural view illustrating a silicon oxide layer formed by FCVD on a second semiconductor according to the present invention. And fourthly, covering a silicon oxide layer 06 on the second semiconductor structure on which the silicon buffer layer 05 is formed by adopting a Fluid Chemical Vapor Deposition (FCVD), wherein the silicon oxide layer 06 fills the space between the Fin and covers the upper surfaces of the silicon buffer layer 05 on the tops of the first hard mask and the second hard mask.
In the present invention, before the fluid chemical vapor deposition is performed in the fourth step, a second thin oxide layer is formed on the silicon buffer layer of the second semiconductor structure. The second thin oxide layer is not shown in fig. 3. That is, after the third step of the present invention, i.e., after the silicon buffer layer 05 is formed, the second thin oxide layer is formed on the silicon buffer layer, and then the fourth step of covering the silicon oxide layer 06 on the second semiconductor layer by FCVD is performed.
And fifthly, annealing the second semiconductor structure. And fifthly, annealing (Anneal) the second semiconductor structure after the FCVD, wherein the silicon buffer layer is formed on the side wall of the Fin of the second semiconductor structure, and is oxidized into silicon oxide in the high-temperature annealing process, so that the direct oxidation of the Fin without the silicon buffer layer is avoided.
And sixthly, removing the first hard mask layer and the second hard mask layer on the top of the Fin.
And seventhly, etching back the silicon oxide layer. The structure is shown in fig. 4, and fig. 4 is a schematic structural diagram of the second semiconductor after etching back the silicon oxide in the present invention. Since step five is performed at a high temperature, the silicon buffer layer is oxidized into silicon oxide, and the first and second thin oxide layers are both silicon oxide in the present invention, and therefore the silicon oxide formed by oxidizing the first and second thin oxide layers and the silicon buffer layer and the silicon oxide layer 06 are both silicon dioxide, the first and second thin oxide layers, the oxidized product of the silicon buffer layer and the silicon oxide layer 06 are shown in fig. 4 as being combined, that is, combined in the silicon oxide layer 06. Step seven, after etching back the silicon oxide layer 06, a part of the top of the Fin is exposed, and the structure shown in fig. 4 is formed.
In summary, in the manufacturing process of the FinFET device, in order to avoid the consumption of Fin in the FCVD and the subsequent annealing processes, a silicon buffer layer is formed on the Fin before the FCVD process after the Fin formation to neutralize the consumption of Fin in the FCVD and the subsequent annealing processes, thereby ensuring that the shape and size of the Fin are not affected. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (9)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202011154128.5A CN112271161A (en) | 2020-10-26 | 2020-10-26 | Method for improving Fin size of Fin type transistor |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011154128.5A CN112271161A (en) | 2020-10-26 | 2020-10-26 | Method for improving Fin size of Fin type transistor |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104979266A (en) * | 2014-04-02 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | Method for forming shallow trench isolation structure |
| CN107369643A (en) * | 2016-05-11 | 2017-11-21 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| US9984933B1 (en) * | 2017-10-03 | 2018-05-29 | Globalfoundries Inc. | Silicon liner for STI CMP stop in FinFET |
| US10276687B1 (en) * | 2017-12-20 | 2019-04-30 | International Business Machines Corporation | Formation of self-aligned bottom spacer for vertical transistors |
| CN111564413A (en) * | 2020-03-03 | 2020-08-21 | 上海华力集成电路制造有限公司 | How to make a fin structure |
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2020
- 2020-10-26 CN CN202011154128.5A patent/CN112271161A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104979266A (en) * | 2014-04-02 | 2015-10-14 | 中芯国际集成电路制造(上海)有限公司 | Method for forming shallow trench isolation structure |
| CN107369643A (en) * | 2016-05-11 | 2017-11-21 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor structure and forming method thereof |
| US9984933B1 (en) * | 2017-10-03 | 2018-05-29 | Globalfoundries Inc. | Silicon liner for STI CMP stop in FinFET |
| US10276687B1 (en) * | 2017-12-20 | 2019-04-30 | International Business Machines Corporation | Formation of self-aligned bottom spacer for vertical transistors |
| CN111564413A (en) * | 2020-03-03 | 2020-08-21 | 上海华力集成电路制造有限公司 | How to make a fin structure |
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Application publication date: 20210126 |