CN112269068A - Method for analyzing pulse width - Google Patents
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Abstract
The invention relates to the technical field of signal analysis, and discloses a pulse width analysis method, which is characterized in that a capacitor is charged once through a pulse signal to be detected; monitoring a first voltage and a second voltage of a capacitor in a primary discharging process; obtaining a first capacitor voltage of the capacitor in one charging process based on the first voltage, the second voltage, the discharge duration corresponding to the first discharge time and the discharge duration corresponding to the second discharge time; the capacitor is charged for the second time through the test pulse signal; monitoring a third voltage of the capacitor and a fourth voltage of the capacitor in a secondary discharge process; obtaining a second capacitor voltage of the capacitor in secondary charging based on the third voltage, the fourth voltage, a discharging time corresponding to the third discharging time and a discharging time corresponding to the fourth discharging time; and obtaining the pulse width of the pulse signal to be tested according to the pulse width of the test pulse signal, the pulse amplitude of the pulse signal to be tested, the first capacitor voltage and the second capacitor voltage. The method disclosed by the invention can accurately measure the pulse width of the pulse signal.
Description
Technical Field
The invention relates to the technical field of signal analysis, in particular to a pulse width analysis method.
Background
As the product ages, the frequency of the atomic clock product output tends to drift more and more, and therefore in most circumstances it is necessary to calibrate the output frequency in a disciplinary manner. The domestication basis is that the time difference between the input reference signal and the local output signal is higher, the higher the measurement precision of the time difference is, the more the calibration accuracy is favorably improved, and the measurement of the time difference of the two pulses can be converted into the measurement of the pulse width through the conversion circuit, so that the measurement accuracy of the pulse width has direct influence on the calibration accuracy.
The invention patent with publication number CN 110672928A discloses a circuit and a device for measuring the time difference of pulse-per-second signals, which adopts the way that the measured signals charge the capacitor, and directly calculates the time difference information according to the charging voltage and the capacitance value of the capacitor.
However, in such a manner, the capacitance is easily affected by factors such as environment and aging, which results in low measurement precision of the pulse width, and thus poor accuracy in calibrating the frequency output by the atomic clock product.
Disclosure of Invention
In order to solve the problem of low measurement precision of the pulse width in the prior art, the invention aims to provide a pulse width analysis method to improve the measurement precision of the pulse width and ensure that the frequency output by an atomic clock product can be accurately calibrated.
In a first aspect, the present invention provides a method for analyzing pulse width, including:
charging the test capacitor for the first time through the pulse signal to be tested;
discharging the once-charged test capacitor once, and monitoring a first voltage of the test capacitor at a first discharging moment and a second voltage of the test capacitor at a second discharging moment in the process of discharging once;
obtaining a first capacitor voltage of the test capacitor when one-time charging is finished based on the first voltage, the second voltage, the discharging time corresponding to the first discharging time and the discharging time corresponding to the second discharging time;
when the voltage of the test capacitor is zero, carrying out secondary charging on the test capacitor through a test pulse signal with a preset pulse width;
carrying out secondary discharge on the secondarily charged test capacitor, and monitoring a third voltage of the test capacitor at a third discharge moment and a fourth voltage of the test capacitor at a fourth discharge moment in a secondary discharge process;
obtaining a second capacitor voltage of the test capacitor when the secondary charging is finished based on the third voltage, the fourth voltage, a discharging time corresponding to the third discharging time and a discharging time corresponding to the fourth discharging time;
and obtaining the pulse width of the pulse signal to be tested according to the pulse width of the test pulse signal, the pulse amplitude of the pulse signal to be tested, the first capacitor voltage and the second capacitor voltage.
Through the design, the test capacitor is charged and discharged through the pulse signal to be tested and the test pulse signal with the preset pulse width, the capacitor voltage when the charging is finished twice is determined according to the voltage and the discharging duration measured in the discharging process, the pulse width of the pulse signal to be tested is accurately obtained according to the capacitor voltage when the charging is finished twice, the pulse width of the test pulse signal and the pulse amplitude of the pulse signal to be tested, and the accurate calibration of the frequency output by the atomic clock product is ensured.
In one possible design, the discharging the once charged test capacitor once includes:
and discharging the test capacitor once when the charging is completed.
In one possible design, the secondarily discharging the secondarily charged test capacitor includes:
and discharging the test capacitor for the second time when the secondary charging is finished.
In one possible design, the first capacitor voltage is calculated by
Wherein, U1Representing said first voltage, U2Representing said second voltage, t1Indicating a discharge time duration, t, corresponding to the first discharge time2And indicating the discharge time length corresponding to the second discharge time.
In one possible design, the second capacitor voltage is calculated by
Wherein, U3Represents said third voltage, U4Representing said fourth voltage, t3Indicating a discharge time period, t, corresponding to the third discharge time4And indicating the discharge time corresponding to the fourth discharge time.
In one possible design, the pulse width of the pulse signal to be measured is calculated by the formula
Wherein, U0Representing the pulse amplitude, t, of the pulse signal to be measuredrRepresenting the pulse width of the test pulse signal.
In one possible design, the monitoring a first voltage of the test capacitor at a first discharge time and a second voltage of the test capacitor at a second discharge time during a discharge process includes:
monitoring first voltages of the test capacitor at a plurality of first discharging moments and second voltages of the test capacitor at a plurality of second discharging moments in a primary discharging process;
the obtaining a first capacitor voltage of the test capacitor when one-time charging is completed based on the first voltage, the second voltage, a discharging time corresponding to the first discharging time, and a discharging time corresponding to the second discharging time includes:
obtaining a plurality of capacitor voltages based on the plurality of first voltages, the plurality of second voltages, the discharge time periods corresponding to the plurality of first discharge moments and the discharge time periods corresponding to the plurality of second discharge moments;
and obtaining a first capacitor voltage of the test capacitor when one-time charging is finished according to the plurality of capacitor voltages.
In a possible design, the obtaining a first capacitor voltage of the test capacitor at the time of completing one charging according to the plurality of capacitor voltages includes:
and fitting, arithmetic mean or least square calculation is carried out according to the plurality of capacitance voltages to obtain the first capacitance voltage.
In one possible design, the monitoring a third voltage of the test capacitor at a third discharge time and a fourth voltage of the test capacitor at a fourth discharge time during the secondary discharge includes:
monitoring third voltages of the test capacitor at a plurality of third discharging moments and fourth voltages of the test capacitor at a plurality of fourth discharging moments in a secondary discharging process;
the obtaining a second capacitor voltage of the test capacitor when the secondary charging is completed based on the third voltage, the fourth voltage, a discharging time corresponding to the third discharging time and a discharging time corresponding to the fourth discharging time includes:
obtaining a plurality of capacitor voltages based on the plurality of third voltages, the plurality of fourth voltages, the discharge time periods corresponding to the plurality of third discharge times, and the discharge time periods corresponding to the plurality of fourth discharge times;
and obtaining a second capacitor voltage of the test capacitor when the secondary charging is finished according to the plurality of capacitor voltages.
In a possible design, the obtaining a second capacitor voltage of the test capacitor when the secondary charging is completed according to the plurality of capacitor voltages includes:
and fitting, arithmetic mean or least square calculation is carried out according to the plurality of capacitance voltages to obtain the second capacitance voltage.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic diagram of a circuit structure for analyzing pulse width according to the present invention.
Fig. 2 is a flow chart of a method for analyzing pulse width according to the present invention.
Detailed Description
The invention is further described with reference to the following figures and specific embodiments. It should be noted that the description of the embodiments is provided to help understanding of the present invention, but the present invention is not limited thereto. Specific structural and functional details disclosed herein are merely illustrative of example embodiments of the invention. This invention may, however, be embodied in many alternate forms and should not be construed as limited to the embodiments set forth herein.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of example embodiments of the present invention.
It should be understood that, for the term "and/or" as may appear herein, it is merely an associative relationship that describes an associated object, meaning that three relationships may exist, e.g., a and/or B may mean: a exists alone, B exists alone, and A and B exist at the same time; for the term "/and" as may appear herein, which describes another associative object relationship, it means that two relationships may exist, e.g., a/and B, may mean: a exists independently, and A and B exist independently; in addition, for the character "/" that may appear herein, it generally means that the former and latter associated objects are in an "or" relationship.
It will be understood that when an element is referred to herein as being "connected," "connected," or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. Conversely, if a unit is referred to herein as being "directly connected" or "directly coupled" to another unit, it is intended that no intervening units are present. In addition, other words used to describe the relationship between elements should be interpreted in a similar manner (e.g., "between … …" versus "directly between … …", "adjacent" versus "directly adjacent", etc.).
It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes" and/or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and/or groups thereof.
It should also be noted that, in some alternative implementations, the functions/acts noted may occur out of the order noted in the figures. For example, two figures shown in succession may, in fact, be executed substantially concurrently, or the figures may sometimes be executed in the reverse order, depending upon the functionality/acts involved.
It should be understood that specific details are provided in the following description to facilitate a thorough understanding of example embodiments. However, it will be understood by those of ordinary skill in the art that the example embodiments may be practiced without these specific details. For example, systems may be shown in block diagrams in order not to obscure the examples in unnecessary detail. In other instances, well-known processes, structures and techniques may be shown without unnecessary detail in order to avoid obscuring example embodiments.
Examples
In order to accurately determine the pulse width of the pulse signal, the embodiment of the application provides a pulse width analysis method, which can improve the measurement precision of the pulse width and ensure that the frequency output by an atomic clock product can be accurately calibrated.
First, in order to more intuitively understand the scheme provided by the embodiment of the present application, a circuit for analyzing the pulse width provided by the embodiment of the present application is described below with reference to fig. 1.
Fig. 1 is a schematic diagram of a circuit structure for analyzing a pulse width according to one or more embodiments of the present disclosure. As shown in fig. 1, the resistor R1 is connected to an AD circuit (a circuit for converting an analog signal into a digital signal), one end of the resistor R2 is connected between the resistor R1 and the AD circuit, the other end of the resistor R2 is grounded, one end of the test capacitor C is connected between the resistor R1 and the AD circuit, the other end of the test capacitor C is grounded, a pulse signal can charge the test capacitor C through the resistor R1, and the charged test capacitor C can be discharged through the resistor R2.
The following will explain the analysis method of the pulse width provided in the embodiments of the present application in detail.
As shown in fig. 2, which is a flowchart of a method for analyzing a pulse width provided in an embodiment of the present application, the method for analyzing a pulse width may include the following steps:
and S201, charging the test capacitor for one time through the pulse signal to be tested.
The pulse signal to be measured is a signal whose pulse width needs to be measured, and the pulse signal to be measured may be a signal output by an atomic clock product and converted by a conversion circuit, and when the test capacitor is charged once, the converted pulse signal to be measured charges the test capacitor through the resistor R1.
It should be noted that, the charging time for charging the test capacitor once is not suitable to be too long, and the voltage of the test capacitor after charging once cannot reach the maximum voltage value of the test capacitor, which is preferably 1/4-3/4 of the maximum voltage value of the test capacitor.
Step S202, discharging the once-charged test capacitor once, and monitoring a first voltage of the test capacitor at a first discharging moment and a second voltage of the test capacitor at a second discharging moment in the once discharging process.
The test capacitor can be discharged once when charging is completed once, that is, the test capacitor can be discharged once when the pulse signal to be tested starts at the end of time, or can be discharged once after charging is completed for a period of time. In the embodiment of the application, the test capacitor is discharged once when the pulse signal to be tested is ended.
In the process of discharging the test capacitor once, the voltages at the two ends of the test capacitor can be tested at a first discharging moment which is a certain time interval from the beginning of discharging to obtain a first voltage of the test capacitor at the first discharging moment, and then the voltages at the two ends of the test capacitor are tested at a second discharging moment which is a certain time interval from the beginning of discharging to obtain a second voltage of the test capacitor at the second discharging moment.
Step S203, obtaining a first capacitor voltage of the test capacitor when one-time charging is completed based on the first voltage, the second voltage, the discharging time corresponding to the first discharging time and the discharging time corresponding to the second discharging time.
In the embodiment of the present application, the formula of the capacitor discharge process may be expressed as:
wherein U represents the current voltage of the capacitor, UsIndicating the initial voltage of the discharge, R2Representing the resistance of resistor R2 and C representing the capacitance of the test capacitor. The discharge time can be increased by adjusting the resistance value of the resistor R2, and the relation between the capacitor voltage and the time can be equivalent to a linear relation in the discharge process, so that the following can be obtained:
the first voltage, the second voltage, the discharge time corresponding to the first discharge time, and the discharge time corresponding to the second discharge time are substituted, and they can be expressed as:
the calculation formula of the first capacitor voltage obtained by simultaneous equations (3) and (4) is:
wherein, U1Representing said first voltage, U2Representing said second voltage, t1Indicating a discharge time duration, t, corresponding to the first discharge time2And indicating the discharge time length corresponding to the second discharge time.
Further, in this embodiment of the application, the first discharging time and the second discharging time may be multiple, that is, a first voltage of the test capacitor at the multiple first discharging times and a second voltage of the test capacitor at the multiple second discharging times in one discharging process may be monitored. When the first capacitor voltage is determined, a plurality of capacitor voltages may be obtained according to the plurality of first voltages, the plurality of second voltages, the discharge time periods corresponding to the plurality of first discharge times, and the discharge time periods corresponding to the plurality of second discharge times. And then fitting, arithmetic mean or least square method calculation is carried out according to the plurality of capacitor voltages to obtain a first capacitor voltage of the tested capacitor when one-time charging is finished.
For example, 3 capacitor voltages are obtained, U respectivelyx1、Ux2And Ux3Then, the 3 capacitor voltages are subjected to arithmetic averaging to obtain a first capacitor voltage Ux＝(Ux1+Ux2+Ux3)/3。
And S204, when the voltage of the test capacitor is zero, carrying out secondary charging on the test capacitor through a test pulse signal with a preset pulse width.
When the voltage across the test capacitor is zero, the test capacitor can be charged again through the resistor R1 by a test pulse signal with a predetermined pulse width.
Similarly, the charging time for the secondary charging of the test capacitor is not suitable to be too long, and the voltage of the test capacitor after the secondary charging cannot reach the maximum voltage value of the test capacitor, which is preferably 1/4-3/4 of the maximum voltage value of the test capacitor.
And S205, carrying out secondary discharge on the secondarily charged test capacitor, and monitoring a third voltage of the test capacitor at a third discharge moment and a fourth voltage of the test capacitor at a fourth discharge moment in the secondary discharge process.
The secondary discharge of the test capacitor may be performed when the secondary charge is completed, that is, the test capacitor may be discharged for the second time when the test pulse signal is ended, or may be discharged for the second time after a period of time after the charge is completed. In the embodiment of the application, the test capacitor is discharged for the second time when the test pulse signal is ended.
And S206, obtaining a second capacitor voltage of the tested capacitor when the secondary charging is finished based on the third voltage, the fourth voltage, the discharging time corresponding to the third discharging time and the discharging time corresponding to the fourth discharging time.
The calculation formula of the second capacitance voltage can be expressed as:
wherein, U3Represents said third voltage, U4Representing said fourth voltage, t3Indicating a discharge time period, t, corresponding to the third discharge time4And indicating the discharge time corresponding to the fourth discharge time.
The derivation process of the calculation formula of the second capacitor voltage is the same as the derivation process in step S203, and is not repeated here.
Further, in this embodiment of the application, the third discharging time and the fourth discharging time may be multiple, that is, the third voltage of the test capacitor at the multiple third discharging times and the fourth voltage of the test capacitor at the multiple fourth discharging times in the secondary discharging process may be monitored. When the second capacitor voltage is determined, a plurality of capacitor voltages may be obtained according to the plurality of third voltages, the plurality of fourth voltages, the discharge time periods corresponding to the plurality of third discharge times, and the discharge time periods corresponding to the plurality of fourth discharge times. And then fitting, arithmetic mean or least square method calculation is carried out according to the plurality of capacitor voltages to obtain a second capacitor voltage of the tested capacitor when the secondary charging is finished.
And S207, obtaining the pulse width of the pulse signal to be tested according to the pulse width of the test pulse signal, the pulse amplitude of the pulse signal to be tested, the first capacitor voltage and the second capacitor voltage.
The relation between the capacitor voltage and the time in the charging process can be equivalently a linear relation, and can be expressed as follows:
the transformation may result in:
substituting parameters, we can get:
the formula (9) is divided by the formula (10) to eliminate R under the same experimental conditions1The two quantities of the pulse width and the pulse width of the pulse signal to be measured, which are easily changed under the influence of environmental factors, are as follows:
wherein, U0To representThe pulse amplitude, t, of the pulse signal to be measuredrRepresenting the pulse width of the test pulse signal. Thus, the pulse width t of the pulse signal to be tested can be obtained by substituting the pulse width of the test pulse signal, the pulse amplitude of the pulse signal to be tested, the first capacitor voltage and the second capacitor voltage into formula 11x。
The pulse width analysis method provided by the embodiment of the application can respectively charge and discharge a test capacitor through a pulse signal to be tested and a test pulse signal with a preset pulse width, determine the capacitor voltage when the charging is completed twice according to the voltage and the discharging duration measured in the discharging process, and then obtain the pulse width of the pulse signal to be tested according to the capacitor voltage when the charging is completed twice, the pulse width of the test pulse signal and the pulse amplitude of the pulse signal to be tested.
The invention is not limited to the above alternative embodiments, and any other various forms of products can be obtained by anyone in the light of the present invention, but any changes in shape or structure thereof, which fall within the scope of the present invention as defined in the claims, fall within the scope of the present invention.
Claims (10)
1. A method of analyzing pulse width, comprising:
charging the test capacitor for the first time through the pulse signal to be tested;
discharging the once-charged test capacitor once, and monitoring a first voltage of the test capacitor at a first discharging moment and a second voltage of the test capacitor at a second discharging moment in the process of discharging once;
obtaining a first capacitor voltage of the test capacitor when one-time charging is finished based on the first voltage, the second voltage, the discharging time corresponding to the first discharging time and the discharging time corresponding to the second discharging time;
when the voltage of the test capacitor is zero, carrying out secondary charging on the test capacitor through a test pulse signal with a preset pulse width;
carrying out secondary discharge on the secondarily charged test capacitor, and monitoring a third voltage of the test capacitor at a third discharge moment and a fourth voltage of the test capacitor at a fourth discharge moment in a secondary discharge process;
obtaining a second capacitor voltage of the test capacitor when the secondary charging is finished based on the third voltage, the fourth voltage, a discharging time corresponding to the third discharging time and a discharging time corresponding to the fourth discharging time;
and obtaining the pulse width of the pulse signal to be tested according to the pulse width of the test pulse signal, the pulse amplitude of the pulse signal to be tested, the first capacitor voltage and the second capacitor voltage.
2. The method of claim 1, wherein said discharging the once charged test capacitor comprises:
and discharging the test capacitor once when the charging is completed.
3. The method of claim 1, wherein said secondarily discharging the secondarily charged test capacitor comprises:
and discharging the test capacitor for the second time when the secondary charging is finished.
4. The method of claim 1, wherein the first capacitor voltage is calculated as
Wherein, U1Representing said first voltage, U2Representing said second voltage, t1Indicating a discharge time duration, t, corresponding to the first discharge time2Presentation instrumentAnd the discharge time length corresponding to the second discharge time.
5. The method of claim 4, wherein the second capacitor voltage is calculated by the formula
Wherein, U3Represents said third voltage, U4Representing said fourth voltage, t3Indicating a discharge time period, t, corresponding to the third discharge time4And indicating the discharge time corresponding to the fourth discharge time.
6. The method of claim 5, wherein the pulse width of the pulse signal under test is calculated by the formula
Wherein U0 represents the pulse amplitude of the pulse signal to be measured, trRepresenting the pulse width of the test pulse signal.
7. The method of claim 1, wherein the monitoring a first voltage of the test capacitor at a first discharge time and a second voltage of the test capacitor at a second discharge time during a discharge process comprises:
monitoring first voltages of the test capacitor at a plurality of first discharging moments and second voltages of the test capacitor at a plurality of second discharging moments in a primary discharging process;
the obtaining a first capacitor voltage of the test capacitor when one-time charging is completed based on the first voltage, the second voltage, a discharging time corresponding to the first discharging time, and a discharging time corresponding to the second discharging time includes:
obtaining a plurality of capacitor voltages based on the plurality of first voltages, the plurality of second voltages, the discharge time periods corresponding to the plurality of first discharge moments and the discharge time periods corresponding to the plurality of second discharge moments;
and obtaining a first capacitor voltage of the test capacitor when one-time charging is finished according to the plurality of capacitor voltages.
8. The method of claim 7, wherein obtaining the first capacitor voltage of the test capacitor at the completion of a charge according to the plurality of capacitor voltages comprises:
and fitting, arithmetic mean or least square calculation is carried out according to the plurality of capacitance voltages to obtain the first capacitance voltage.
9. The method of claim 1, wherein monitoring a third voltage of the test capacitor at a third discharge time and a fourth voltage of the test capacitor at a fourth discharge time during the second discharge comprises:
monitoring third voltages of the test capacitor at a plurality of third discharging moments and fourth voltages of the test capacitor at a plurality of fourth discharging moments in a secondary discharging process;
the obtaining a second capacitor voltage of the test capacitor when the secondary charging is completed based on the third voltage, the fourth voltage, a discharging time corresponding to the third discharging time and a discharging time corresponding to the fourth discharging time includes:
obtaining a plurality of capacitor voltages based on the plurality of third voltages, the plurality of fourth voltages, the discharge time periods corresponding to the plurality of third discharge times, and the discharge time periods corresponding to the plurality of fourth discharge times;
and obtaining a second capacitor voltage of the test capacitor when the secondary charging is finished according to the plurality of capacitor voltages.
10. The method of claim 9, wherein obtaining the second capacitor voltage of the test capacitor at the completion of the second charging according to the plurality of capacitor voltages comprises:
and fitting, arithmetic mean or least square calculation is carried out according to the plurality of capacitance voltages to obtain the second capacitance voltage.
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