CN112259505B

CN112259505B - Method for forming fin body of semiconductor device

Info

Publication number: CN112259505B
Application number: CN202011117903.XA
Authority: CN
Inventors: 李勇
Original assignee: Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Current assignee: Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Priority date: 2020-10-19
Filing date: 2020-10-19
Publication date: 2023-08-15
Anticipated expiration: 2040-10-19
Also published as: CN112259505A

Abstract

The invention relates to a method for forming fin bodies of a semiconductor device, which relates to a semiconductor integrated circuit manufacturing technology, wherein after a second side wall is formed, at least part of a first etching stop layer and a second etching stop layer which are exposed are removed through an etching process, so that a groove between the fin bodies formed later is a double-groove structure comprising a shallow groove and a deep groove, wherein the isolation effect of the deep groove is better, therefore, the isolation performance of the semiconductor device can be improved, and the process is simple.

Description

Method for forming fin body of semiconductor device

Technical Field

The present invention relates to semiconductor integrated circuit fabrication, and more particularly, to a method for forming a fin body of a semiconductor device.

Background

In the field of semiconductor integrated circuits, with the development of technology, the critical dimensions of semiconductor devices are continuously shrinking, and the requirements for the manufacturing process of semiconductor devices are also becoming more and more stringent. In order to increase the integration density of semiconductor devices, many different methods have been used in the prior art, such as Self-aligned four-time pattern (Self-alignedQuadruple Patterning, SAQP) processes, and the like. Devices with smaller nodes can be fabricated using the SAQP process, and it has been demonstrated that the SAQP process can provide less process variation. With the continued development of the process, the adoption of SAQP can enable the pitch of the fin to be smaller than 40nm.

Typical SAQP process steps are: first, a first mandrel is formed. And then forming a side wall covering the first mandrel, and forming a second mandrel by taking the side wall of the first mandrel as a mask. And forming a side wall covering the second mandrel, and forming the fin part by taking the side wall of the second mandrel as a mask. The fin portions formed by adopting the SAQP process are dense, and the spacing of the fin portions can be smaller than 40nm. When forming devices such as SRAM, it is necessary to etch the fins to increase the pitch of the fins.

Disclosure of Invention

The invention provides a method for forming a fin body of a semiconductor device, which comprises the following steps: s1: providing a semiconductor substrate, wherein the semiconductor substrate comprises a layer to be patterned, a fin part hard mask layer, a first mandrel layer and a second mandrel layer which are sequentially overlapped, a first etching stop layer is arranged between the first mandrel layer and the second mandrel layer, a second etching stop layer is arranged between the first mandrel layer and the fin part hard mask layer, and a pad oxygen layer is arranged between the fin part hard mask layer and the layer to be patterned; s2: etching the second mandrel layer to form a plurality of second mandrels with a preset interval; s3: forming first side walls on two sides of the second mandrel; s4: removing the second mandrel by taking the first etching stop layer as a stop layer, and reserving the first side wall; s5: etching the first etching stop layer and the first mandrel layer by taking the second etching stop layer as a stop layer and the first side wall as a mask so as to form a plurality of first mandrels; s6: removing the first side wall and forming second side walls covering two sides of the first mandrel; s7: etching to remove at least part of the exposed first etching stop layer and second etching stop layer; s8: removing the first mandrel and reserving the second side wall; s9: etching by taking the second side wall as a mask until the layer to be patterned is formed, so that a plurality of discrete patterns are formed on the layer to be patterned, and removing the second side wall; s10: forming a photoresist layer, exposing and developing at least one discrete pattern adjacent to two sides of the effective discrete pattern, protecting the effective discrete pattern and other discrete patterns by the photoresist, and performing an etching process to remove the developed at least one discrete pattern; s11: removing the photoresist, forming a photoresist layer, exposing and developing to protect the effective discrete patterns by the photoresist, developing other discrete patterns, and etching to remove the developed discrete patterns; s12: removing the photoresist to form an oxide layer, performing a thermal annealing process, and performing a planarization process by taking the fin hard mask layer as a stop layer; s13: and removing the fin part hard mask layer and the pad oxide layer on the discrete pattern, and then removing part of the oxide layer to expose the effective discrete pattern so as to form the effective fin body.

Further, in S2, a photolithography pattern is formed over the second mandrel layer, and the first mandrel layer is etched using the photolithography pattern as a mask to form a plurality of second mandrels.

Further, depositing a first sidewall material layer covering the second mandrel in S3; and etching back the first side wall material layer to form the first side wall.

Further, depositing a second side wall material layer covering the first mandrel in S6; and etching the second side wall material layer back to form the second side wall.

Further, all of the exposed first and second etch stop layers are etched away in S7.

Further, in S7, etching is further continued to remove a portion of the fin hard mask layer under the second etch stop layer and the first mandrel under the first etch stop layer.

Further, the etching process in S7 is performed, so that the trench between the discrete patterns formed in S9 includes a shallow trench and a deep trench, wherein the trench corresponding to the first mandrel removed in S8 is a shallow trench, and wherein the top of the remaining portion of the discrete pattern removed after S11 is flush with the bottom of the shallow trench.

Further, the etching process in S7 is performed, so that the trench between the discrete patterns formed in S9 includes a shallow trench and a deep trench, wherein the trench corresponding to the first mandrel removed in S8 is a shallow trench, and wherein the top of the remaining portion of the discrete pattern removed after S11 is higher than the bottom of the shallow trench.

Further, the etching process in S7 is performed such that the trench between the discrete patterns formed in S9 includes a shallow trench and a deep trench, wherein the trench corresponding to the first mandrel removed in S8 is a shallow trench, and wherein the top of the remaining portion of at least one discrete pattern removed after S10 is flush with the bottom of the shallow trench 116.

Further, the etching process in S7 is performed, so that the trenches between the discrete patterns formed in S9 include shallow trenches and deep trenches, wherein the trenches corresponding to the first mandrels removed in S8 are shallow trenches, and wherein the top of the remaining portion of at least one discrete pattern removed after S10 is higher than the bottom of the shallow trenches.

Therefore, after the second side wall is formed, at least part of the exposed first etching stop layer and the second etching stop layer are removed through one etching process, so that the grooves among the fins formed later are of a double-groove structure comprising shallow grooves and deep grooves, the isolation effect of the deep grooves is better, the isolation performance of the semiconductor device can be improved, and the process is simple.

Drawings

Fig. 1a to 13a are schematic top views illustrating the structure of the fin body of the semiconductor device at each step in the formation process according to an embodiment of the invention.

Fig. 1b to 13b are schematic cross-sectional views along Y-Y' in fig. 1a to 13a, respectively, during the formation of a fin body of a semiconductor device according to an embodiment of the present invention.

Fig. 9c to 13c are schematic cross-sectional views along X-X' in fig. 9a to 13a, respectively, during the formation of the fin body of the semiconductor device according to an embodiment of the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

It should be understood that the present invention may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size of layers and regions, as well as the relative sizes, may be exaggerated for the same elements throughout. It will be understood that when an element or layer is referred to as being "on" …, "" adjacent to "…," "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected to or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on" …, "" directly adjacent to "…," "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatially relative terms, such as "under …," "under …," "below," "under …," "above …," "above," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "under …" and "under …" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

In an embodiment of the present invention, a method for forming a fin body of a semiconductor device is provided, including: s1: providing a semiconductor substrate, wherein the semiconductor substrate comprises a layer to be patterned, a fin part hard mask layer, a first mandrel layer and a second mandrel layer which are sequentially overlapped, a first etching stop layer is arranged between the first mandrel layer and the second mandrel layer, a second etching stop layer is arranged between the first mandrel layer and the fin part hard mask layer, and a pad oxygen layer is arranged between the fin part hard mask layer and the layer to be patterned; s2: etching the second mandrel layer to form a plurality of second mandrels with a preset interval;

s3: forming first side walls on two sides of the second mandrel; s4: removing the second mandrel by taking the first etching stop layer as a stop layer, and reserving the first side wall; s5: etching the first etching stop layer and the first mandrel layer by taking the second etching stop layer as a stop layer and the first side wall as a mask so as to form a plurality of first mandrels; s6: removing the first side wall and forming second side walls covering two sides of the first mandrel; s7: etching to remove at least part of the exposed first etching stop layer and second etching stop layer; s8: removing the first mandrel and reserving the second side wall; s9: etching by taking the second side wall as a mask until the layer to be patterned is formed, so that a plurality of discrete patterns are formed on the layer to be patterned, and removing the second side wall; s10: forming a photoresist layer, exposing and developing at least one discrete pattern adjacent to two sides of the effective discrete pattern, protecting the effective discrete pattern and other discrete patterns by the photoresist, and performing an etching process to remove the developed at least one discrete pattern; s11: removing the photoresist, forming a photoresist layer, exposing and developing to protect the effective discrete patterns by the photoresist, developing other discrete patterns, and etching to remove the developed discrete patterns; s12: removing the photoresist to form an oxide layer, performing a thermal annealing process, and performing a planarization process by taking the fin hard mask layer as a stop layer; s13: and removing the fin part hard mask layer and the pad oxide layer on the discrete pattern, and then removing part of the oxide layer to expose the effective discrete pattern so as to form the effective fin body.

In particular, please refer to fig. 1a to 13a, fig. 1b to 13b, and fig. 9c to 13c. Fig. 1a to 13a are schematic top views illustrating the structure of the fin body of the semiconductor device at each step in the formation process according to an embodiment of the invention. Fig. 1b to 13b are schematic cross-sectional views along Y-Y' in fig. 1a to 13a, respectively, during the formation of a fin body of a semiconductor device according to an embodiment of the present invention. Fig. 9c to 13c are schematic cross-sectional views along X-X' in fig. 9a to 13a, respectively, during the formation of the fin body of the semiconductor device according to an embodiment of the present invention. The method for forming the fin body of the semiconductor device according to the embodiment of the invention comprises the following steps:

s1: as shown in fig. 1a and 1b, a semiconductor substrate 10 is provided, the semiconductor substrate 10 includes a layer to be patterned 101, a Fin Hard Mask layer (Fin HM) 102, a first mandrel layer 103 and a second mandrel layer 104 stacked in order, a first Etch Stop Layer (ESL) 105 is provided between the first mandrel layer 103 and the second mandrel layer 104, a second Etch stop layer 106 is provided between the first mandrel layer 103 and the Fin Hard Mask layer 102, and a Pad Oxide (PO) 107 is provided between the Fin Hard Mask layer 102 and the layer to be patterned 101;

specifically, in an embodiment, the layer 101 to be patterned is a silicon single crystal, a germanium single crystal, or a silicon germanium single crystal. Alternatively, the layer 101 to be patterned may also be a silicon-on-insulator (SOI) substrate, a silicon-on-insulator (SSOI), a silicon-on-insulator (S-SiGeOI), a silicon-on-insulator (SiGeOI), a germanium-on-insulator (GeOI), a substrate of epitaxial layer structure on silicon, or a compound semiconductor. The compound semiconductor includes silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, or indium dysprosium. Preferably, the layer 101 to be patterned is a silicon single crystal. The pad oxide layer 107 is silicon oxide (SiO 2). The fin hard mask layer 102 may be one or more of titanium nitride (TiN), tantalum nitride (TaN), silicon carbide (SiC), and titanium oxide (TiO 2). The pad oxygen layer and the fin hard mask layer are used for protecting the fin. The first and second etch stop layers 105 and 106 may be carbon-containing silicon Nitride (NDC), silicon oxide, or silicon nitride. The first etching stop layer 105 and the second etching stop layer 106 are used to prevent over etching. The first mandrel layer 103 and the second mandrel layer 104 may be Spin On Carbon (SOC), spin On Hard mask (SOH), amorphous silicon, amorphous Carbon, or the like. The materials of the first mandrel layer 103 and the second mandrel layer 104 may be the same or different.

S2: as shown in fig. 2a and 2b, the second mandrel layer 104 is etched to form a plurality of second mandrels 108 having a predetermined spacing from each other;

specifically, a photolithography pattern is formed over the second mandrel layer 104, and the first mandrel layer 104 is etched using the photolithography pattern as a mask to form a plurality of second mandrels 108. Specifically, the second mandrel 108 has a predetermined spacing therebetween. Optionally, the spacing between the second mandrels 108 is equal.

S3: as shown in fig. 3a and 3b, first side walls 110 are formed on both sides of the second mandrel 108;

specifically, a first layer of sidewall material is deposited overlying the second mandrel 108; and etching back the first sidewall material layer to form the first sidewall 110. In an alternative implementation, the sidewall material may be silicon nitride. The sidewall material layer may be formed by any technique known to those skilled in the art, preferably by chemical vapor deposition (Chemical Vapor Deposition, CVD). Alternatively, the etch-back method may be an anisotropic etch, alternatively, a plasma etch (PlasmaEtching, PE).

S4: as shown in fig. 4a and 4b, the second mandrel 108 is removed with the first etching stop layer 105 as a stop layer, and the first sidewall 110 is remained;

alternatively, the second mandrel 108 may be removed using Wet Strip (WS) methods.

S5: as shown in fig. 5a and 5b, the second etching stop layer 106 is used as a stop layer and the first sidewall 110 is used as a mask to etch the first etching stop layer 105 and the first mandrel layer 103, so as to form a plurality of first mandrels 111;

specifically, the first mandrel layer 103 may be etched using a wet etching process. After the etching is completed, the width of the first mandrel 111 is substantially the same as the width of the first sidewall 110.

S6: as shown in fig. 6a and 6b, the first sidewall 110 is removed, and second sidewalls 112 covering both sides of the first mandrel 111 are formed;

specifically, a second sidewall material layer is deposited to cover the first mandrel 111; and etching the second side wall material layer back to form the second side wall 112. Specifically, the material of the second sidewall 112 may be silicon nitride.

S7: as shown in fig. 7a and 7b, the exposed at least part of the first etch stop layer 105 and the second etch stop layer 106 are etched away;

specifically, in an embodiment, all of the first and second etch stop layers 105 and 106 exposed are etched away in S7. Further, in the embodiment shown in fig. 7a and 7b, the etching is continued in S7 to remove part of the fin hard mask layer 102 located under the second etch stop layer 106 and the first mandrel 111 located under the first etch stop layer 105.

S8: as shown in fig. 8a and 8b, the first mandrel 111 is removed, and the second sidewall 112 is left;

alternatively, the first mandrel 111 may be removed using a Wet Strip (WS) method.

S9: as shown in fig. 9a and 9b, etching with the second side wall 112 as a mask until the layer 101 to be patterned, so as to form a plurality of discrete patterns 113 on the layer 101 to be patterned, and removing the second side wall 112;

specifically, a wet etching process is used to form a plurality of discrete patterns 113 corresponding to the second sidewalls 112.

Referring to fig. 9c, fig. 9c is a schematic cross-sectional view along X-X' in fig. 9a during formation of a fin body of a semiconductor device according to an embodiment of the invention.

Specifically, since at least part of the exposed first etching stop layer 105 and second etching stop layer 106 are removed by etching in S7, the depths of the trenches between the discrete patterns 113 formed by etching with the second sidewall 112 as a mask are different, including the shallow trenches 116 and the deep trenches 117, as shown in fig. 9b and 9 c. Wherein the trenches corresponding to the first mandrels 111 removed in S8 are shallow trenches 116 and the others are deep trenches 117. That is, the trenches between the discrete patterns 113 formed in S9 include shallow trenches 116 and deep trenches 117 by the etching process in S7, wherein the trenches corresponding to the first mandrels 111 removed in S8 are shallow trenches 116.

S10: as shown in fig. 10a and 10b, a photoresist layer is formed, and exposure and development are performed to develop at least one of the discrete patterns 113 adjacent to both sides of the effective discrete pattern 113', the effective discrete pattern 113' and other discrete patterns 113 are protected by the photoresist 220, and an etching process is performed to remove the developed at least one discrete pattern 113;

as shown in fig. 10a and 10b, the effective discrete pattern 113 'is four, and one discrete pattern 113 adjacent to both sides of the effective discrete pattern 113' is removed. One of the discrete patterns 113 is removed as in fig. 10a and 10b, but two discrete patterns 113 may be removed. As in fig. 10a and 10b, the number of the effective discrete patterns 113 'is four, but the number of the effective discrete patterns 113' is not limited in the present invention. This process is commonly referred to as a fine removal process or a horizontal removal process.

Referring to fig. 10c, fig. 10c is a schematic cross-sectional view along X-X' in fig. 8a during formation of a fin body of a semiconductor device according to an embodiment of the invention. As shown in fig. 10c, two separate patterns 113 are included on both sides in the X-X' direction.

As further shown in fig. 10b, the top of the remaining portion of the at least one discrete pattern 113 removed after S10 is level with the bottom of the shallow trench 116 or slightly higher than the bottom of the shallow trench 116, and in one embodiment, the top of the remaining portion of the at least one discrete pattern 113 removed after S10 is less than 5nm higher than the bottom of the shallow trench 116.

S11: as shown in fig. 11a and 11b, the photoresist is removed, and a photoresist layer is formed again, and exposure and development are performed to protect the effective discrete pattern 113' with the photoresist 230, and other discrete patterns 113 are developed, and an etching process is performed to etch the developed discrete patterns 113;

typically this process becomes a roughness removal process.

Referring to fig. 11c, fig. 11c is a schematic cross-sectional view along X-X' in fig. 11a during formation of a fin body of a semiconductor device according to an embodiment of the invention.

As further shown in fig. 11b, the top of the remaining portion of the discrete pattern 113 removed after S11 is level with the bottom of the shallow trench 116 or slightly higher than the bottom of the shallow trench 116, and in one embodiment, the top of the remaining portion of the discrete pattern 113 removed after S11 is less than 5nm higher than the bottom of the shallow trench 116.

S12: as shown in fig. 12a and 12b, the photoresist 230 is removed to form the oxide layer 114, and a thermal annealing process is performed, and then a planarization process is performed using the fin hard mask layer 102 as a stop layer;

referring to fig. 12c, fig. 12c is a schematic cross-sectional view along X-X' in fig. 12a during formation of a fin body of a semiconductor device according to an embodiment of the invention.

S13: as shown in fig. 13a and 13b, fin hard mask layer 102 and pad oxide layer 107 over discrete pattern 113 are removed, and then a portion of oxide layer 114 is removed to expose active discrete pattern 113' to form active fin 115.

Referring to fig. 13c, fig. 13c is a schematic cross-sectional view along X-X' in fig. 13a during formation of a fin body of a semiconductor device according to an embodiment of the invention.

Specifically, oxide layer 114 at the bottom of active fins 115 forms spacers between active fins 115.

Specifically, the height of the oxide layer 114 remaining in step S13 is higher than the height of the removed discrete pattern.

After the second side wall is formed, at least part of the exposed first etching stop layer and the second etching stop layer are removed through one etching process, so that the grooves among fins formed later are of a double-groove structure comprising shallow grooves and deep grooves, the isolation effect of the deep grooves is better, the isolation performance of a semiconductor device can be improved, and the process is simple.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims

1. The method for forming the fin body of the semiconductor device is characterized by comprising the following steps of:

s1: providing a semiconductor substrate, wherein the semiconductor substrate comprises a layer to be patterned, a fin part hard mask layer, a first mandrel layer and a second mandrel layer which are sequentially overlapped, a first etching stop layer is arranged between the first mandrel layer and the second mandrel layer, a second etching stop layer is arranged between the first mandrel layer and the fin part hard mask layer, and a pad oxygen layer is arranged between the fin part hard mask layer and the layer to be patterned;

s2: etching the second mandrel layer to form a plurality of second mandrels with a preset interval;

s3: forming first side walls on two sides of the second mandrel;

s4: removing the second mandrel by taking the first etching stop layer as a stop layer, and reserving the first side wall;

s5: etching the first etching stop layer and the first mandrel layer by taking the second etching stop layer as a stop layer and the first side wall as a mask so as to form a plurality of first mandrels;

s6: removing the first side wall and forming second side walls covering two sides of the first mandrel;

s7: etching to remove at least part of the exposed first etching stop layer and second etching stop layer;

s8: removing the first mandrel and reserving the second side wall;

s9: etching by taking the second side wall as a mask until the layer to be patterned is formed, so that a plurality of discrete patterns are formed on the layer to be patterned, and removing the second side wall;

s10: forming a photoresist layer, exposing and developing at least one discrete pattern adjacent to two sides of the effective discrete pattern, protecting the effective discrete pattern and other discrete patterns by the photoresist, and performing an etching process to remove the developed at least one discrete pattern;

s11: removing the photoresist, forming a photoresist layer, exposing and developing to protect the effective discrete patterns by the photoresist, developing other discrete patterns, and etching to remove the developed discrete patterns;

s12: removing the photoresist to form an oxide layer, performing a thermal annealing process, and performing a planarization process by taking the fin hard mask layer as a stop layer; and

s13: and removing the fin part hard mask layer and the pad oxide layer on the discrete pattern, and then removing part of the oxide layer to expose the effective discrete pattern so as to form the effective fin body.

2. The method of claim 1, wherein a lithographic pattern is formed over the second mandrel layer in S2, and the first mandrel layer is etched using the lithographic pattern as a mask to form a plurality of second mandrels.

3. The method of claim 1, wherein depositing a first sidewall material layer overlying the second mandrel in S3; and etching back the first side wall material layer to form the first side wall.

4. The method of claim 1, wherein depositing a second sidewall material layer covering the first mandrel in S6; and etching the second side wall material layer back to form the second side wall.

5. The method of claim 1, wherein all of the exposed first and second etch stop layers are etched away in S7.

6. The method of claim 5, further comprising continuing to etch in S7 to remove portions of the fin hardmask layer underlying the second etch stop layer and the first mandrel underlying the first etch stop layer.

7. The method of claim 1, wherein the etching process in S7 is performed such that the trench between the discrete patterns formed in S9 includes a shallow trench and a deep trench, wherein the trench corresponding to the first mandrel removed in S8 is a shallow trench, and wherein the top of the remaining portion of the discrete pattern removed after S11 is flush with the bottom of the shallow trench.

8. The method of claim 1, wherein the etching process in S7 is performed such that the trench between the discrete patterns formed in S9 includes a shallow trench and a deep trench, wherein the trench corresponding to the first mandrel removed in S8 is a shallow trench, and wherein the top of the remaining portion of the discrete pattern removed after S11 is higher than the bottom of the shallow trench.

9. The method of claim 1, wherein the etching process in S7 is performed such that the trench between the discrete patterns formed in S9 includes a shallow trench and a deep trench, wherein the trench corresponding to the first mandrel removed in S8 is a shallow trench, and wherein the top of the remaining portion of the at least one discrete pattern removed after S10 is flush with the bottom of the shallow trench 116.

10. The method of claim 1, wherein the etching process in S7 is performed such that the trench between the discrete patterns formed in S9 includes a shallow trench and a deep trench, wherein the trench corresponding to the first mandrel removed in S8 is a shallow trench, and wherein the top of the remaining portion of the at least one discrete pattern removed after S10 is higher than the bottom of the shallow trench.