CN112216329B - Data erasing method, memory control circuit unit and memory storage device - Google Patents

Abstract

The invention provides a data erasing method, a memory control circuit unit and a memory storage device. The method comprises the following steps: selecting a first physical erase unit group from the plurality of physical erase unit groups; and performing an erase operation on the first physically erased cell group. The first physical erasing unit group comprises a plurality of first physical erasing units, and the number of at least one second physical erasing unit in the plurality of first physical erasing units used for executing the erasing operation in the same time point is different from the number of the plurality of first physical erasing units.

Description

Data erasure method, memory control circuit unit and memory storage device

Technical field

The invention relates to a data erasure method, a memory control circuit unit and a memory storage device.

Background technique

Digital cameras, mobile phones and MP3 players have grown rapidly in recent years, causing consumer demand for storage media to increase rapidly. Since rewritable non-volatile memory modules (such as flash memory) have the characteristics of non-volatile data, power saving, small size, and no mechanical structure, they are very suitable for being built into various removable memory modules as listed above. in portable multimedia devices.

Generally speaking, a rewritable non-volatile memory module may include multiple memory sub-modules. In order to increase writing efficiency, the memory management circuit usually writes data into the aforementioned memory sub-modules through multiple data buses in a parallel manner. In the process of parallel writing, assuming that the amount of data used for writing is exactly equal to the amount of data that can be stored in a physical erasure unit group, each physical erasure unit in the physical erasure unit group will usually be A point in time is filled with data simultaneously.

Assuming that later the memory management circuit needs to perform an erasure operation on the physical erasure unit in the aforementioned physical erasure unit group for some reason (for example, performing valid data merging or other operations), the memory management circuit will usually perform the physical erasure operation at the same time. Perform erasure operations on multiple physical erasure units in the erasure unit group. That is to say, in the prior art, in order to maintain the efficiency of parallel writing, the erasing operation is usually performed in units of one physical erasing unit group to release the space of one physical erasing unit group and use it as a subsequent parallel writing Use.

In the case where a physical erasure unit group includes a physical erasure unit in each memory sub-module, when an erasure operation is performed in units of a physical erasure unit group, due to the rewritable non-volatile memory All memory sub-modules are used to perform erase operations. Assuming that the host system continues to issue multiple write commands at this time, the data from the host system cannot be written into the rewritable non-volatile memory. is temporarily stored in buffer memory. However, due to the limited space of the buffer memory, when the erase operation takes longer and the host system continues to issue write instructions, a buffer memory with a larger capacity is required to temporarily store data from the host system. Therefore, how to avoid the problem caused by all memory sub-modules in the rewritable non-volatile memory being used to perform erasure operations at the same time is one of the problems that those skilled in the art want to solve.

Contents of the invention

The invention provides a data erasure method, a memory control circuit unit and a memory storage device, which can avoid using a buffer memory with a large capacity and avoid all memory sub-modules in a rewritable non-volatile memory from being used to execute at the same time. Problems caused by erasure operations.

The present invention proposes a data erasure method for a rewritable non-volatile memory module. The rewritable non-volatile memory module includes a plurality of physical erasure unit groups, and the multiple physical erasure units Each physical erasure unit group in the unit group has a plurality of physical erasure units, and the data erasure method includes: selecting a first physical erasure unit group from the plurality of physical erasure unit groups; and The first physical erasure unit group performs an erasure operation, wherein the first physical erasure unit group includes a plurality of first physical erasure units, and the first physical erasure unit group is used to perform the erasure operation at the same point in time. The number of at least one second physical erasing unit among the plurality of first physical erasing units is different from the number of the plurality of first physical erasing units.

In an embodiment of the present invention, the method further includes: performing a write operation on a second physical erasure unit group among the plurality of physical erasure unit groups according to at least one write instruction, wherein the The second physical erasure unit group includes a plurality of third physical erasure units; when the amount of data stored in the second physical erasure unit group reaches a first threshold, the first physical erasure unit is executed. The unit group performs the step of the erasing operation to perform the erasing operation on a fourth physical erasing unit among the plurality of first physical erasing units; and when the second physical erasing unit group When the amount of stored data reaches a second threshold, the step of performing the erasure operation on the first entity erasure unit group is performed to erase a fifth entity among the plurality of first entity erasure units. The erasing unit performs the erasing operation, wherein the first threshold is smaller than the second threshold.

In an embodiment of the present invention, when the amount of data stored in the second physical erasure unit group reaches the capacity of the second physical erasure unit group that can be used to store data, the first physical erasure unit group The data stored in the plurality of first physical erasure units of the unit group have all been erased.

In an embodiment of the present invention, the rewritable non-volatile memory module includes a plurality of memory sub-modules, and the plurality of memory sub-modules are respectively connected to a memory control circuit unit through a plurality of channels. The plurality of physical erasure units of each physical erasure unit group in the physical erasure unit group respectively belong to different memory sub-modules among the plurality of memory sub-modules.

In an embodiment of the present invention, the memory control circuit unit performs the write operation on the plurality of third physical erasure units in the second physical erasure unit group through the plurality of channels to A plurality of data are written into the plurality of third physical erasing units in parallel.

In an embodiment of the present invention, before performing the erase operation on the first physical erase unit group, the method further includes: adjusting to perform a write operation on the plurality of first physical erase units. The order of operations; and performing the write operation on the plurality of first physical erasure units according to the write order and a write instruction so that when the storage space of the second physical erasure unit is full At this time, at least one sixth physical erasure unit among the plurality of first physical erasure units still has available storage space.

In an embodiment of the present invention, among the plurality of physical erasure unit groups, the plurality of physical erasure units in the same physical erasure unit group correspond to a logical address-physical address mapping table. Same index code.

In an embodiment of the present invention, each of the plurality of first physical erasure units in the first physical erasure unit group includes a first physical programming unit and a second physical programming unit. After the first physical programming unit of each of the first physical erasing units is programmed first, the second physical programming unit of each of the first physical erasing units Only then can it be programmed.

In an embodiment of the present invention, each of the plurality of first physical erasure units in the first physical erasure unit group includes a first physical programming unit. When a continuous data is written into the first physical erasure unit group, the plurality of data stored in the first physical programming unit of the first physical erasure unit in the first physical erasure unit group Multiple logical addresses corresponding to each data are consecutive.

In an embodiment of the present invention, each of the plurality of first physical erasure units in the first physical erasure unit group includes a first physical programming unit and a second physical programming unit. When a continuous data is written into the first physical erasure unit group, the data stored in the first physical programming unit of a seventh physical erasure unit in the first physical erasure unit group is The corresponding logical address is discontinuous with the logical address corresponding to the data stored in the second physical programming unit of the seventh physical erasing unit, and the first physical erasing unit of the seventh physical erasing unit The physical programming unit and the second physical programming unit are physically continuously arranged.

The present invention proposes a memory control circuit unit for controlling a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical erasure unit groups, and the plurality of physical erasure unit groups Each physical erasure unit group in the erasure unit group has multiple physical erasure units, and the memory control circuit unit includes: a host interface, a memory interface and a memory management circuit. The host interface is used to electrically connect to a host system. The memory interface is used to electrically connect to the rewritable non-volatile memory module. The memory management circuit is electrically connected to the host interface and the memory interface, and is used to perform the following operations: select a first physical erasure unit group from the plurality of physical erasure unit groups; and perform the following operations on the first physical erasure unit group: A group of physical erasing units performs an erasing operation, wherein the first group of physical erasing units includes a plurality of first physical erasing units, and the plurality of first physical erasing units are used to perform the erasing operation at the same point in time. The number of at least one second physical erasing unit among the first physical erasing units is different from the number of the plurality of first physical erasing units.

In an embodiment of the present invention, the memory management circuit is further configured to perform a write operation on a second physical erasure unit group among the plurality of physical erasure unit groups according to at least one write instruction, wherein The second physical erasing unit group includes a plurality of third physical erasing units. When the amount of data stored in the second physical erasure unit group reaches a first threshold, the memory management circuit is also used to perform the erase operation on the first physical erasure unit group. Operated to perform the erasing operation on a fourth physical erasing unit among the plurality of first physical erasing units. When the amount of data stored in the second physical erasure unit group reaches a second threshold, the memory management circuit is also used to perform the erase operation on the first physical erasure unit group. Operate to perform the erase operation on a fifth physical erase unit among the plurality of first physical erase units, wherein the first threshold is less than the second threshold.

In an embodiment of the present invention, when the amount of data stored in the second physical erasure unit group reaches the capacity of the second physical erasure unit group that can be used to store data, the first physical erasure unit group The data stored in the plurality of first physical erasure units of the unit group have all been erased.

In an embodiment of the present invention, the rewritable non-volatile memory module includes a plurality of memory sub-modules, and the plurality of memory sub-modules are respectively connected to the memory management circuit through a plurality of channels. The plurality of physical erasure units of each physical erasure unit group in the physical erasure unit group respectively belong to different memory sub-modules among the plurality of memory sub-modules.

In an embodiment of the present invention, the memory management circuit performs the write operation on the plurality of third physical erasure units in the second physical erasure unit group through the plurality of channels to A plurality of data are written in the plurality of third physical erasing units in parallel.

In an embodiment of the present invention, before performing the erasing operation on the first physical erasing unit group, the memory management circuit is further used to adjust the execution of an erasing operation on the plurality of first physical erasing units. The order of write operations. The memory management circuit is also used to perform the write operation on the plurality of first physical erasure units according to the write order and a write instruction, so that when the storage space of the second physical erasure unit When full, at least one sixth physical erasing unit among the plurality of first physical erasing units still has usable storage space.

In an embodiment of the present invention, among the plurality of physical erasure unit groups, the plurality of physical erasure units in the same physical erasure unit group correspond to a logical address-physical address mapping table. Same index code.

In an embodiment of the present invention, each of the plurality of first physical erasure units in the first physical erasure unit group includes a first physical programming unit and a second physical programming unit. After the first physical programming unit of each of the first physical erasing units is programmed first, the second physical programming unit of each of the first physical erasing units Only then can it be programmed.

In an embodiment of the present invention, each of the plurality of first physical erasure units in the first physical erasure unit group includes a first physical programming unit. When a continuous data is written into the first physical erasure unit group, the plurality of data stored in the first physical programming unit of the first physical erasure unit in the first physical erasure unit group Multiple logical addresses corresponding to each data are consecutive.

In an embodiment of the present invention, each of the plurality of first physical erasure units in the first physical erasure unit group includes a first physical programming unit and a second physical programming unit. When a continuous data is written into the first physical erasure unit group, the data stored in the first physical programming unit of a seventh physical erasure unit in the first physical erasure unit group is The corresponding logical address is discontinuous with the logical address corresponding to the data stored in the second physical programming unit of the seventh physical erasing unit, and the first physical erasing unit of the seventh physical erasing unit The physical programming unit and the second physical programming unit are physically continuously arranged.

The invention proposes a memory storage device, which includes: a connection interface unit, a rewritable non-volatile memory module and a memory control circuit unit. The connection interface unit is used to electrically connect to a host system. The rewritable non-volatile memory module includes a plurality of physical erasure unit groups, and each of the plurality of physical erasure unit groups has a plurality of physical erasure units. The memory control circuit unit is electrically connected to the connection interface unit and the rewritable non-volatile memory module and is used to perform the following operations: select a first physical erasure unit from the plurality of physical erasure unit groups. unit group; and perform an erasure operation on the first physical erasure unit group, wherein the first physical erasure unit group includes a plurality of first physical erasure units and is used to perform all the first physical erasure units at the same point in time. In the erasing operation, the number of at least one second physical erasing unit among the plurality of first physical erasing units is different from the number of the plurality of first physical erasing units.

In an embodiment of the present invention, the memory control circuit unit is further configured to perform a write operation on a second physical erasure unit group among the plurality of physical erasure unit groups according to at least one write instruction, The second physical erasing unit group includes a plurality of third physical erasing units. When the amount of data stored in the second physical erasure unit group reaches a first threshold, the memory control circuit unit is also used to perform the erase operation on the first physical erasure unit group. The step of performing the erasing operation on a fourth physical erasing unit among the plurality of first physical erasing units. When the amount of data stored in the second physical erasure unit group reaches a second threshold, the memory control circuit unit is also used to perform the erase operation on the first physical erasure unit group. The step of performing the erasing operation on a fifth physical erasing unit among the plurality of first physical erasing units, wherein the first threshold is smaller than the second threshold.

In an embodiment of the present invention, when the amount of data stored in the second physical erasure unit group reaches the capacity of the second physical erasure unit group that can be used to store data, the first physical erasure unit group The data stored in the plurality of first physical erasure units of the unit group have all been erased.

In an embodiment of the present invention, the rewritable non-volatile memory module includes a plurality of memory sub-modules, and the plurality of memory sub-modules are respectively connected to a memory control circuit unit through a plurality of channels. The plurality of physical erasure units of each physical erasure unit group in the physical erasure unit group respectively belong to different memory sub-modules among the plurality of memory sub-modules.

In an embodiment of the present invention, the memory control circuit unit performs the write operation on the plurality of third physical erasure units in the second physical erasure unit group through the plurality of channels to A plurality of data are written into the plurality of third physical erasing units in parallel.

In an embodiment of the present invention, before performing the erasing operation on the first physical erasing unit group, the memory control circuit unit is further used to adjust the execution of the plurality of first physical erasing units. A sequence of write operations, the memory control circuit unit is further configured to perform the write operations on the plurality of first physical erasure units according to the write sequence and a write instruction, so that when the second When the storage space of the physical erasure unit is full, at least one sixth physical erasure unit among the plurality of first physical erasure units still has usable storage space.

In an embodiment of the present invention, among the plurality of physical erasure unit groups, the plurality of physical erasure units in the same physical erasure unit group correspond to a logical address-physical address mapping table. Same index code.

In an embodiment of the present invention, each of the plurality of first physical erasure units in the first physical erasure unit group includes a first physical programming unit and a second physical programming unit. After the first physical programming unit of each of the first physical erasing units is programmed first, the second physical programming unit of each of the first physical erasing units Only then can it be programmed.

In an embodiment of the present invention, each of the plurality of first physical erasure units in the first physical erasure unit group includes a first physical programming unit. When a continuous data is written into the first physical erasure unit group, the plurality of data stored in the first physical programming unit of the first physical erasure unit in the first physical erasure unit group Multiple logical addresses corresponding to each data are consecutive.

In an embodiment of the present invention, each of the plurality of first physical erasure units in the first physical erasure unit group includes a first physical programming unit and a second physical programming unit. When a continuous data is written into the first physical erasure unit group, the data stored in the first physical programming unit of a seventh physical erasure unit in the first physical erasure unit group is The corresponding logical address is discontinuous with the logical address corresponding to the data stored in the second physical programming unit of the seventh physical erasing unit, and the first physical erasing unit of the seventh physical erasing unit The physical programming unit and the second physical programming unit are physically continuously arranged.

Based on the above, in the data erasure method, memory control circuit unit and memory storage device of the present invention, since the erasure operation will not be performed on all physical erasure units in a physical erasure unit group at the same time, therefore at the same time Not all memory sub-modules are used to perform erase operations at this point in time. At this time, when the host system continues to issue write instructions, the data from the host system can be written into the rewritable non-volatile memory without being temporarily stored in the buffer memory to wait for the completion of the erasure operation. Thereby, the data erasing method of the present invention does not use a buffer memory with a large capacity and avoids the problem caused by all memory sub-modules in the rewritable non-volatile memory being used to perform erasing operations at the same time.

In order to make the above-mentioned features and advantages of the present invention more obvious and understandable, embodiments are given below and described in detail with reference to the accompanying drawings.

Description of the drawings

FIG. 1 is a schematic diagram of a host system, a memory storage device and an input/output (I/O) device according to an exemplary embodiment of the present invention;

Figure 2 is a schematic diagram of a host system, a memory storage device and an I/O device according to another exemplary embodiment of the present invention;

Figure 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the present invention;

Figure 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention;

FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention;

Figure 6 is a schematic block diagram of a rewritable non-volatile memory module according to the first exemplary embodiment of the present invention;

Figure 7 is a flow chart of a data erasure method according to an exemplary embodiment of the present invention;

8A, 8B, 9A, 9B, 10A, 10B, 11A, 11B, 12A and 12B are schematic diagrams of an example of a data erasure method according to the first exemplary embodiment of the present invention. ;

FIG. 13 is a schematic diagram of an example of a data erasure method according to a second exemplary embodiment of the present invention.

Explanation of reference numbers:

30, 10: Memory storage device

31, 11: Host system

110: System bus

111: Processor

112: Random Access Memory

113: Read-only memory

114: Data transmission interface

12: Input/output (I/O) device

20: Motherboard

201: Flash drive

202: Memory card

203: Solid state drive

204: Wireless memory storage device

205: Global Positioning System Module

206: Network interface card

207: Wireless transmission device

208: Keyboard

209: Screen

210: Speaker

32: SD card

33: CF card

34: Embedded storage device

341: Embedded multimedia card

342: Embedded multi-chip package storage device

402: Connect interface unit

404: Memory control circuit unit

406: Rewritable non-volatile memory module

502: Memory management circuit

504: Host interface

506: Memory interface

508: Error checking and correction circuit

510: Buffer memory

512: Power management circuit

310: First memory submodule

320: Second memory submodule

330: Third memory submodule

340: Fourth memory submodule

316, 326, 336, 346: Data bus

410(0)～410(N), 420(0)～420(N), 430(0)～430(N), 440(0)～440(N): Entity erasure unit

OD1～OD16, ND1～ND16, ID1～ID8: data

S701: Step of selecting a first physical erasure unit group from multiple physical erasure unit groups

S703: Perform an erasure operation on the first physical erasure unit group, where the first physical erasure unit group includes a plurality of first physical erasure units, and the first entities used to perform the erasure operation at the same point in time The number of second physical erasing units in the erasing unit is different from the number of first physical erasing units.

Detailed ways

Generally speaking, a memory storage device (also called a memory storage system) includes a rewritable non-volatile memory module (rerewritable non-volatile memory module) and a controller (also called a control circuit). Typically a memory storage device is used with a host system so that the host system can write data to or read data from the memory storage device.

FIG. 1 is a schematic diagram of a host system, a memory storage device, and an input/output (I/O) device according to an exemplary embodiment of the present invention. FIG. 2 is a schematic diagram of a host system, a memory storage device and an I/O device according to another exemplary embodiment of the present invention.

Referring to FIGS. 1 and 2 , the host system 11 generally includes a processor 111 , a random access memory (RAM) 112 , a read only memory (ROM) 113 and a data transmission interface 114 . The processor 111 , the random access memory 112 , the read-only memory 113 and the data transmission interface 114 are all electrically connected to the system bus 110 .

In this exemplary embodiment, the host system 11 is electrically connected to the memory storage device 10 through the data transmission interface 114 . For example, the host system 11 may store data to or read data from the memory storage device 10 via the data transfer interface 114 . In addition, the host system 11 is electrically connected to the I/O device 12 through the system bus 110 . For example, host system 11 may transmit output signals to or receive input signals from I/O device 12 via system bus 110 .

In this exemplary embodiment, the processor 111 , the random access memory 112 , the read-only memory 113 and the data transmission interface 114 may be disposed on the motherboard 20 of the host system 11 . The number of data transmission interfaces 114 may be one or more. Through the data transmission interface 114, the motherboard 20 can be electrically connected to the memory storage device 10 via wired or wireless methods. The memory storage device 10 may be, for example, a pen drive 201, a memory card 202, a solid state drive (SSD) 203 or a wireless memory storage device 204. The wireless memory storage device 204 may be, for example, a Near Field Communication (NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth (Bluetooth) memory storage device, or a low-power Bluetooth memory storage device (eg, iBeacon ) and other memory storage devices based on various wireless communication technologies. In addition, the motherboard 20 can also be electrically connected to various I devices such as a Global Positioning System (GPS) module 205, a network interface card 206, a wireless transmission device 207, a keyboard 208, a screen 209, a speaker 210, etc. through the system bus 110. /O device. For example, in an exemplary embodiment, the motherboard 20 can access the wireless memory storage device 204 through the wireless transmission device 207 .

In an example embodiment, the host system is substantially any system that can cooperate with a memory storage device to store data. Although in the above exemplary embodiments, the host system is described as a computer system, FIG. 3 is a schematic diagram of a host system and a memory storage device according to another exemplary embodiment of the present invention. Please refer to FIG. 3 . In another exemplary embodiment, the host system 31 can also be a digital camera, video camera, communication device, audio player, video player or tablet computer, and the memory storage device 30 can be used therefor. Various non-volatile memory storage devices such as Secure Digital (SD) card 32, Compact Flash (CF) card 33 or embedded storage device 34. The embedded storage device 34 includes various types such as an embedded Multi MediaCard (eMMC) 341 and/or an embedded Multi Chip Package (eMCP) storage device 342. The memory module is directly electrically connected to the host system. Embedded storage device on the substrate.

FIG. 4 is a schematic block diagram of a memory storage device according to an exemplary embodiment of the present invention.

Referring to FIG. 4 , the memory storage device 10 includes a connection interface unit 402 , a memory control circuit unit 404 and a rewritable non-volatile memory module 406 .

The connection interface unit 402 is used to electrically connect the memory storage device 10 to the host system 11 . In this exemplary embodiment, the connection interface unit 402 complies with the Peripheral Component Interconnect Express (PCI Express) standard and is compatible with the NVM express interface standard. Specifically, the fast non-volatile memory interface standard is a communication protocol between the host system and the memory device. It defines the temporary memory interface and instructions between the controller of the memory storage device and the operating system of the host system. Set and function set, and by optimizing the interface standard of the memory storage device, to promote the data access speed and data transfer rate of the memory storage device based on the PCIe interface. However, in another example embodiment, the connection interface unit 402 may also comply with other suitable standards. In addition, the connection interface unit 402 and the memory control circuit unit 404 may be packaged in a chip, or the connection interface unit 402 may be arranged outside a chip including the memory control circuit unit 404.

The memory control circuit unit 404 is used to execute a plurality of logic gates or control instructions implemented in hardware or solid state, and write and read data in the rewritable non-volatile memory module 406 according to the instructions of the host system 11 Operations such as fetching and erasing.

The rewritable non-volatile memory module 406 is electrically connected to the memory control circuit unit 404 and used to store data written by the host system 11 . The rewritable non-volatile memory module 406 may be a single-level cell (SLC) NAND flash memory module (that is, a flash memory module that can store 1 bit in one memory cell), a multi-level Memory cell (Multi Level Cell, MLC) NAND type flash memory module (that is, a flash memory module that can store 2 bits in one memory cell), Complex level memory cell (Triple Level Cell, TLC) NAND type flash memory module (ie, a flash memory module that can store 3 bits in one memory cell), other flash memory modules, or other memory modules with the same characteristics.

Each memory cell in the rewritable non-volatile memory module 406 stores one or more bits based on changes in voltage (hereinafter also referred to as critical voltage). Specifically, there is a charge trapping layer between the control gate and the channel of each memory cell. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the critical voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell." As the threshold voltage changes, each memory cell in the rewritable non-volatile memory module 406 has multiple memory states. By applying a read voltage, it is possible to determine which storage state a memory cell belongs to, thereby obtaining one or more bits stored in the memory cell.

In this exemplary embodiment, the storage units of the rewritable non-volatile memory module 406 will constitute multiple physical programming units, and these physical programming units will constitute multiple physical erasure units. Specifically, memory cells on the same word line will form one or more physical programming units. If each storage unit can store more than 2 bits, the physical programming units on the same word line can at least be classified into lower physical programming units and upper physical programming units. For example, the Least Significant Bit (LSB) of a memory unit belongs to the lower physical programming unit, and the Most Significant Bit (MSB) of a memory unit belongs to the upper physical programming unit. Generally speaking, in MLC NAND flash memory, the writing speed of the lower physical programming unit will be greater than the writing speed of the upper physical programming unit, and/or the reliability of the lower physical programming unit is higher than that of the upper physical programming unit. Reliability of programmed units.

In this exemplary embodiment, the physical programming unit is the smallest unit of programming. That is, the physical programming unit is the smallest unit for writing data. For example, the entity programming unit is an entity page (page) or an entity sector (sector). If the entity programming units are entity pages, these entity programming units usually include data bit areas and redundancy bit areas. The data bit area contains multiple physical sectors to store user data, while the redundant bit area is used to store system data (for example, management data such as error correction codes). In this exemplary embodiment, the data bit area includes 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other example embodiments, the data bit zone may also include 8, 16, or more or less physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, the physical erasure unit is the smallest unit of erasure. That is, each physical erase unit contains one of the minimum number of erased memory cells. For example, the physical erasure unit is a physical block.

FIG. 5 is a schematic block diagram of a memory control circuit unit according to an exemplary embodiment of the present invention.

Referring to FIG. 5 , the memory control circuit unit 404 includes a memory management circuit 502 , a host interface 504 and a memory interface 506 .

The memory management circuit 502 is used to control the overall operation of the memory control circuit unit 404. Specifically, the memory management circuit 502 has a plurality of control instructions, and when the memory storage device 10 is operating, these control instructions will be executed to perform data writing, reading, erasing and other operations. When the operation of the memory management circuit 502 is described below, it is equivalent to describing the operation of the memory control circuit unit 404.

In this exemplary embodiment, the control instructions of the memory management circuit 502 are implemented in a solid state. For example, the memory management circuit 502 has a microprocessor unit (not shown) and a read-only memory (not shown), and the control instructions are burned into the read-only memory. When the memory storage device 10 is operating, these control instructions will be executed by the microprocessor unit to perform data writing, reading, erasing and other operations.

In another exemplary embodiment, the control instructions of the memory management circuit 502 can also be stored in a specific area of the rewritable non-volatile memory module 406 in the form of program code (for example, a system area in the memory module dedicated to storing system data). middle. In addition, the memory management circuit 502 has a microprocessor unit (not shown), a read-only memory (not shown), and a random access memory (not shown). In particular, this read-only memory has a boot code, and when the memory control circuit unit 404 is enabled, the microprocessor unit will first execute the boot code to store the data in the rewritable non-volatile memory module. The control instructions in 406 are loaded into the random access memory of the memory management circuit 502 . Afterwards, the microprocessor unit will run these control instructions to perform operations such as writing, reading and erasing data.

In addition, in another exemplary embodiment, the control instructions of the memory management circuit 502 can also be implemented in a hardware form. For example, the memory management circuit 502 includes a microcontroller, a memory unit management circuit, a memory writing circuit, a memory reading circuit, a memory erasing circuit and a data processing circuit. The memory unit management circuit, the memory writing circuit, the memory reading circuit, the memory erasing circuit and the data processing circuit are electrically connected to the microcontroller. The memory cell management circuit is used to manage the memory cells or groups thereof of the rewritable non-volatile memory module 406 . The memory writing circuit is used to issue a write instruction sequence to the rewritable non-volatile memory module 406 to write data into the rewritable non-volatile memory module 406 . The memory reading circuit is used to issue a read instruction sequence to the rewritable non-volatile memory module 406 to read data from the rewritable non-volatile memory module 406 . The memory erasure circuit is used to issue an erasure instruction sequence to the rewritable non-volatile memory module 406 to erase data from the rewritable non-volatile memory module 406 . The data processing circuit is used to process data to be written to the rewritable non-volatile memory module 406 and data to be read from the rewritable non-volatile memory module 406 . The write instruction sequence, the read instruction sequence and the erase instruction sequence may each include one or more program codes or instruction codes and are used to instruct the rewritable non-volatile memory module 406 to perform corresponding writing and reading. and erase operations. In an exemplary embodiment, the memory management circuit 502 can also issue other types of instruction sequences to the rewritable non-volatile memory module 406 to instruct the execution of corresponding operations.

The host interface 504 is electrically connected to the memory management circuit 502 and is used to receive and identify instructions and data transmitted by the host system 11 . That is to say, the instructions and data transmitted by the host system 11 will be transmitted to the memory management circuit 502 through the host interface 504 . In this example embodiment, the host interface 504 is compatible with the SATA standard. However, it must be understood that the present invention is not limited to this. The host interface 504 may also be compatible with the PATA standard, IEEE 1394 standard, PCIExpress standard, USB standard, SD standard, UHS-I standard, UHS-II standard, MS standard, MMC standard, eMMC standard, UFS standard, CF standard, IDE standard or other suitable data transmission standards.

The memory interface 506 is electrically connected to the memory management circuit 502 and used to access the rewritable non-volatile memory module 406 . That is to say, the data to be written to the rewritable non-volatile memory module 406 will be converted into a format acceptable to the rewritable non-volatile memory module 406 through the memory interface 506 . Specifically, if the memory management circuit 502 wants to access the rewritable non-volatile memory module 406, the memory interface 506 will transmit a corresponding instruction sequence. For example, these instruction sequences may include a write instruction sequence instructing to write data, a read instruction sequence instructing to read data, an erase instruction sequence instructing to erase data, and to instruct various memory operations (e.g., change read corresponding instruction sequence to obtain voltage levels or perform garbage collection operations, etc.). These instruction sequences are generated, for example, by the memory management circuit 502 and transmitted to the rewritable non-volatile memory module 406 through the memory interface 506 . These command sequences may include one or more signals, or data on the bus. These signals or data may include instruction codes or program codes. For example, the read instruction sequence will include the read identification code, memory address and other information.

In an exemplary embodiment, the memory control circuit unit 404 also includes an error checking and correction circuit 508, a buffer memory 510 and a power management circuit 512.

The error checking and correcting circuit 508 is electrically connected to the memory management circuit 502 and is used to perform error checking and correcting operations to ensure the accuracy of data. Specifically, when the memory management circuit 502 receives a write command from the host system 11, the error checking and correction circuit 508 generates a corresponding error correcting code (ECC) and /or error detecting code (EDC), and the memory management circuit 502 will write the data corresponding to this write instruction and the corresponding error correction code and/or error checking code into the rewritable non-volatile memory In module 406. Afterwards, when the memory management circuit 502 reads data from the rewritable non-volatile memory module 406, it will also read the error correction code and/or error checking code corresponding to the data, and the error checking and correction circuit 508 will This error correction code and/or error checking code performs error checking and correction operations on the data being read.

The buffer memory 510 is electrically connected to the memory management circuit 502 and is used to temporarily store data and instructions from the host system 11 or data from the rewritable non-volatile memory module 406 . The power management circuit 512 is electrically connected to the memory management circuit 502 and used to control the power supply of the memory storage device 10 .

FIG. 6 is a schematic block diagram of a rewritable non-volatile memory module according to the first exemplary embodiment of the present invention.

Referring to FIG. 6 , the rewritable non-volatile memory module 406 includes a first memory sub-module 310 , a second memory sub-module 320 , a third memory sub-module 330 and a fourth memory sub-module 340 . For example, the first, second, third and fourth memory sub-modules 310, 320, 330 and 340 are respectively memory dies. The first memory sub-module 310 has physical erasure units 410(0)˜410(N). The second memory sub-module 320 has physical erasure units 420(0)˜420(N). The third memory sub-module 330 has physical erasure units 430(0)˜430(N). The fourth memory sub-module 340 has physical erasure units 440(0)˜440(N).

For example, the first, second, third and fourth memory sub-modules 310, 320, 330 and 340 are electrically connected to the memory control circuit unit 404 through independent data buses 316, 326, 336 and 346 respectively. Based on this, the memory management circuit 502 can write data to the first, second, third and fourth memory sub-modules 310, 320, 330 and 340 through the data buses 316, 326, 336 and 346 in a parallel manner.

However, it must be understood that in another exemplary embodiment of the present invention, the first, second, third and fourth memory sub-modules 310, 320, 330 and 340 can also only use one data bus and a memory control circuit. Unit 404 is electrically connected. Here, the memory management circuit 502 may write data to the first, second, third and fourth memory sub-modules 310, 320, 330 and 340 through a single data bus in an interleave manner.

In particular, the first, second, third and fourth memory sub-modules 310, 320, 330 and 340 may respectively include multiple word lines, and multiple memory cells on the same word line will form multiple physical pages. Multiple entity pages of the same word line can be called entity page groups. Each physical erasure unit of the first, second, third and fourth memory sub-modules 310, 320, 330 and 340 respectively has a plurality of physical pages, wherein the physical pages belonging to the same physical erasure unit can be independently written and erased simultaneously. For example, each physical erasure unit is composed of 128 physical pages. However, it must be understood that the present invention is not limited thereto. Each physical erasure unit may be composed of 64 physical pages, 256 physical pages, or any other number of physical pages.

In more detail, the physical erasure unit is the smallest unit of erasure. That is, each physical erase unit contains one of the minimum number of erased memory cells. The entity page is the smallest unit of programming. That is, the physical page is the smallest unit for writing data. However, it must be understood that in another exemplary embodiment of the present invention, the smallest unit of written data may also be a sector (Sector) or other sizes. Each entity page usually includes a data bit area and a redundant bit area. The data bit area is used to store user data, while the redundant bit area is used to store system data (for example, error checking and correction codes). It should be noted that in another exemplary embodiment, a physical erasure unit may also refer to a physical address, a physical programming unit, or be composed of multiple consecutive or discontinuous physical addresses.

It is worth mentioning that although the exemplary embodiment of the present invention is described using a rewritable non-volatile memory module 406 including four memory sub-modules as an example. However, the present invention is not limited thereto. In other embodiments, the rewritable non-volatile memory module 406 may also include six, eight or ten memory sub-modules.

Here, multiple physical erasing units simultaneously used for parallel writing may be collectively referred to as a "physical erasing unit group". In this embodiment, multiple physical erasure units in a physical erasure unit group respectively belong to different memory sub-modules and can be written simultaneously through the data bus. Taking the physical erasure unit group composed of the physical erasure unit 410(1), the physical erasure unit 420(1), the physical erasure unit 430(1) and the physical erasure unit 440(1) as an example, the memory management circuit 502 may write data to the physical erase unit 410(1), the physical erase unit 420(1), the physical erase unit 430(1), and the physical erase unit 440 in parallel through the data buses 316, 326, 336, and 346. (1). The physical erasure unit 410(1), the physical erasure unit 420(1), the physical erasure unit 430(1) and the physical erasure unit 440(1) are respectively located in different memory sub-modules. As another example, taking the physical erasure unit group composed of the physical erasure unit 410(0), the physical erasure unit 420(0), the physical erasure unit 430(0), and the physical erasure unit 440(0) as an example, The memory management circuit 502 may write data to the physical erase unit 410(0), the physical erase unit 420(0), the physical erase unit 430(0) and the physical erase unit in parallel through the data buses 316, 326, 336 and 346. Divide unit 440(0). The physical erasure unit 410(0), the physical erasure unit 420(0), the physical erasure unit 430(0) and the physical erasure unit 440(0) are respectively located in different memory sub-modules.

In particular, in this embodiment, in order to facilitate management, multiple physical erasure units in the same physical erasure unit group will correspond to the same index code in a logical address-physical address mapping table. Different entities The erasure unit groups correspond to different index codes. For example, taking the physical erasure unit group composed of the physical erasure unit 410(0), the physical erasure unit 420(0), the physical erasure unit 430(0) and the physical erasure unit 440(0) as an example, the physical erasure unit group The erasure unit 410(0), the physical erasure unit 420(0), the physical erasure unit 430(0) and the physical erasure unit 440(0) will correspond to the same index code in the logical address-physical address mapping table , the value of this index code is "001", for example. As another example, taking the physical erasure unit group composed of the physical erasure unit 410(1), the physical erasure unit 420(1), the physical erasure unit 430(1), and the physical erasure unit 440(1) as an example, The physical erasure unit 410(1), the physical erasure unit 420(1), the physical erasure unit 430(1) and the physical erasure unit 440(1) will correspond to the same index in the logical address-physical address mapping table code, the value of this index code is for example "002". Other entity erasure unit groups also have similar situations, which will not be described again here.

It should be noted that, generally speaking, in order to increase writing efficiency, the memory management circuit 502 usually writes data to the first, second, and third bus terminals through the data buses 316, 326, 336, and 346 in a parallel manner. and fourth memory sub-modules 310, 320, 330 and 340. For example, the memory management circuit 502 writes data in parallel to the above-mentioned physical erasure unit 410(1), physical erasure unit 420(1), and physical erasure unit 430(1) through the data buses 316, 326, 336, and 346. In the physical erasure unit group formed with the physical erasure unit 440(1). In the process of parallel writing, it is assumed that the amount of data used for writing is exactly equal to the amount of data that can be stored by one physical erasure unit group (that is, the amount of data that can be stored by four physical erasure units). The erasure unit 410(1), the physical erasure unit 420(1), the physical erasure unit 430(1), and the physical erasure unit 440(1) are usually filled with data simultaneously at a certain point in time.

It is assumed that the memory management circuit 502 needs to perform physical erasure of the physical erasure unit 410(1), the physical erasure unit 420(1), the physical erasure unit 430(1), and the physical erasure unit 440(1) for some reason. When the erase unit group performs an erase operation (for example, performing valid data merging or other operations), the memory management circuit 502 usually simultaneously performs the physical erase unit 410(1), the physical erase unit 420(1), and the physical erase unit 410(1). The erase unit 430(1) and the physical erase unit 440(1) perform the erase operation. That is to say, in the prior art, in order to maintain the efficiency of parallel writing, the erasing operation is usually performed in units of one physical erasing unit group to release the space of one physical erasing unit group and use it as a subsequent parallel writing Use.

In this case, since the four memory sub-modules in the rewritable non-volatile memory 406 are all used to perform the erase operation, assuming that the host system 11 continues to issue multiple write instructions at this time, the host system 11 The data cannot be written into the rewritable non-volatile memory 406 but needs to be temporarily stored in the buffer memory 510 . However, due to the limited space of the buffer memory 510 , when the erase operation takes longer and the host system 11 continues to issue write instructions, a buffer memory 510 with a larger capacity is required to temporarily store data from the host system 11 . Therefore, how to prevent all memory sub-modules in the rewritable non-volatile memory 406 from being used to perform erasure operations at the same time is one of the problems that those skilled in the art want to solve.

FIG. 7 is a flow chart of a data erasure method according to an exemplary embodiment of the present invention.

Referring to FIG. 7 , assuming that an erasure operation needs to be performed, in step S701 , the memory management circuit 502 selects a physical erasure unit group from a plurality of physical erasure unit groups in the rewritable non-volatile memory 406 ( Also known as, first physical erasure unit group). Thereafter, in step S703, the memory management circuit 502 performs an erasure operation on the aforementioned first physical erasure unit group. In particular, the first physical erasure unit group includes a plurality of physical erasure units (also referred to as first physical erasure units), and the first physical erasure unit is used to perform the erasure operation at the same point in time. The number of at least one physical erasing unit (also referred to as the second physical erasing unit) in is different from the number of the first physical erasing unit.

It should be noted that in this embodiment, since multiple physical erasure units in a physical erasure unit group belong to different memory sub-modules respectively, in the data erasure method of the present invention, since the same time point The erase operation is not performed on all physical erase units in a physical erase unit group, so not all memory sub-modules are used to perform the erase operation at the same point in time. At this time, when the host system 11 continues to issue write instructions, the data from the host system 11 can be written into the rewritable non-volatile memory 406 without being temporarily stored in the buffer memory 510 waiting for an erasure operation. Finish. Thereby, the data erasing method of the present invention does not need to use the buffer memory 510 with a large capacity and avoids the problem caused by all memory sub-modules in the rewritable non-volatile memory 406 being used to perform erasing operations at the same time. .

The data erasure method of the present invention is described below with multiple embodiments.

[First Embodiment]

8A, 8B, 9A, 9B, 10A, 10B, 11A, 11B, 12A and 12B are schematic diagrams of an example of a data erasure method according to the first exemplary embodiment of the present invention. .

First, please refer to FIG. 8A and FIG. 8B. Here, the physical erasure unit 410(1), the physical erasure unit 420(1), the physical erasure unit 430(1), and the physical erasure unit 440(1) are constituted. The physical erasure unit group is called the "first physical erasure unit group", and the multiple physical erasure units owned by the first physical erasure unit group may be called the "first physical erasure unit". In addition, here, the physical erasure unit group composed of the physical erasure unit 410(0), the physical erasure unit 420(0), the physical erasure unit 430(0), and the physical erasure unit 440(0) is called "Second physical erasure unit group", and the plurality of physical erasure units owned by the second physical erasure unit group may be called "third physical erasure unit".

In the initial state of the first embodiment, the physical erasure unit 410(0), the physical erasure unit 420(0), the physical erasure unit 430(0) and the physical erasure unit 440 of the second physical erasure unit group (0) No data has been stored, and the physical erasure unit 410(1), the physical erasure unit 420(1), the physical erasure unit 430(1) and the physical erasure unit 440(1) of the first physical erasure unit group ) stores data OD1~OD16. As shown in FIG. 8B , the first to fourth physical programming units of the physical erasing unit 410(1) respectively store data OD1, data OD5, data OD9 and data OD13. The first to fourth physical programming units of the physical erasing unit 420(1) respectively store data OD2, data OD6, data OD10 and data OD14. The first to fourth physical programming units of the physical erasing unit 430(1) respectively store data OD3, data OD7, data OD11 and data OD15. The first to fourth physical programming units of the physical erasure unit 440(1) respectively store data OD4, data OD8, data OD12 and data OD16.

Since the physical erasure unit 410(1), the physical erasure unit 420(1), the physical erasure unit 430(1), and the physical erasure unit 440(1) have stored data OD1˜OD16, it is assumed that the memory management circuit 502 is It is necessary to perform erasing operations on the physical erasing unit 410(1), the physical erasing unit 420(1), the physical erasing unit 430(1), and the physical erasing unit 440(1). In this embodiment, the memory management The circuit 502 distributes the erasing operations performed on the plurality of physical erasing units into writing operations.

In more detail, please refer to FIG. 9A and FIG. 9B at the same time. It is assumed that the host system 11 then issues a write command to write the data ND1 to ND4 into the rewritable non-volatile memory 10 . Since the second physical erasure unit group has not yet stored data, the memory management circuit 502 may select the second physical erasure unit group for writing. Afterwards, the memory management circuit 502 may perform a write operation on the second physical erasure unit group according to the write instruction issued by the host system 11 . For example, the memory management circuit 502 may first write the data ND1 to ND4 in parallel to the first physical program of the physical erasure unit 410(0) in the second physical erasure unit group according to the write instruction issued by the host system 11. unit, the first physical programming unit of the physical erasure unit 420(0), the first physical programming unit of the physical erasure unit 430(0), and the first physical program of the physical erasure unit 440(0) in the unit.

At this time, the memory management circuit 502 determines whether the amount of data stored in the second physical erasure unit group reaches a threshold (also referred to as the first threshold). In this example, it is assumed that the first threshold is one quarter of the amount of data that can be stored in a physical erasure unit group. However, the present invention is not used to limit the exact value of the first threshold.

Since the second physical erasure unit group in FIG. 9A contains 16 physical programming units, and 4 of these physical programming units store data ND1˜ND4, the memory management circuit 502 determines that the second physical erasing unit group The amount of data stored in the physical erasure unit group reaches the first threshold. At this time, the memory management circuit 502 may perform an erasure operation on the physical erasure unit 410(1) of the first physical erasure unit group (also known as the fourth physical erasure unit), as shown in FIG. 9B.

After that, please refer to FIG. 10A and FIG. 10B at the same time. It is assumed that the host system 11 then issues a write command to write the data ND5 to ND8 into the rewritable non-volatile memory 10 . The memory management circuit 502 may perform a write operation on the second physical erasure unit group again according to the write instruction issued by the host system 11 . For example, the memory management circuit 502 may write the data ND5˜ND8 in parallel to the second physical programming unit of the physical erasing unit 410(0) in the second physical erasing unit group according to the write command issued by the host system 11 , the second physical programming unit of the physical erasure unit 420(0), the second physical programming unit of the physical erasure unit 430(0), and the second physical programming unit of the physical erasure unit 440(0). in the unit.

At this time, the memory management circuit 502 determines whether the amount of data stored in the second physical erasure unit group reaches another threshold (also called a second threshold). In this example, it is assumed that the second threshold is half the amount of data that can be stored in a physical erasure unit group. However, the present invention is not used to limit the exact value of the second threshold.

Since the second physical erasure unit group in FIG. 10A contains 16 physical programming units, and 8 of these physical programming units store data ND1˜ND8, the memory management circuit 502 determines that the second physical erasing unit group The amount of data stored in the physical erasure unit group reaches the second threshold. At this time, the memory management circuit 502 may perform an erasure operation on the physical erasure unit 420(1) of the first physical erasure unit group (also known as the fifth physical erasure unit), as shown in FIG. 10B.

After that, please refer to FIG. 11A and FIG. 11B at the same time, assuming that the host system 11 then issues a write command to write the data ND9 to ND12 into the rewritable non-volatile memory 10 . The memory management circuit 502 may perform a write operation on the second physical erasure unit group again according to the write instruction issued by the host system 11 . For example, the memory management circuit 502 may write the data ND9 to ND12 in parallel to the third physical programming unit of the physical erasing unit 410(0) in the second physical erasing unit group according to the write command issued by the host system 11. , the third physical programming unit of the physical erasure unit 420(0), the third physical programming unit of the physical erasure unit 430(0), and the third physical programming unit of the physical erasure unit 440(0). in the unit.

At this time, the memory management circuit 502 determines whether the amount of data stored in the second physical erasure unit group reaches another threshold (also called a third threshold). In this example, it is assumed that the third threshold is three-quarters of the amount of data that can be stored in a physical erasure unit group. However, the present invention is not used to limit the exact value of the third threshold.

Since the second physical erasure unit group in FIG. 11A contains 16 physical programming units, and 12 of these physical programming units store data ND1˜ND12, the memory management circuit 502 determines that the second physical erasing unit group The amount of data stored in the physical erasure unit group reaches the third threshold. At this time, the memory management circuit 502 may perform an erasure operation on the physical erasure unit 430(1) of the first physical erasure unit group, as shown in FIG. 11B.

After that, please refer to FIG. 12A and FIG. 12B at the same time, assuming that the host system 11 then issues a write command to write the data ND13 to ND16 into the rewritable non-volatile memory 10 . The memory management circuit 502 may perform a write operation on the second physical erasure unit group again according to the write instruction issued by the host system 11 . For example, the memory management circuit 502 may write the data ND13 to ND16 in parallel to the fourth physical programming unit of the physical erasing unit 410(0) in the second physical erasing unit group according to the write command issued by the host system 11. , the fourth physical programming unit of the physical erasure unit 420(0), the fourth physical programming unit of the physical erasure unit 430(0), and the fourth physical programming unit of the physical erasure unit 440(0). in the unit.

At this time, the memory management circuit 502 determines whether the amount of data stored in the second physical erasure unit group reaches another threshold (also known as the fourth threshold). In this example, it is assumed that the fourth threshold is the amount of data that can be stored by a physical erasure unit group. However, the present invention is not used to limit the exact value of the fourth threshold.

Since the second physical erasure unit group in FIG. 12A contains 16 physical programming units, and 16 of these physical programming units store data ND1˜ND16, the memory management circuit 502 determines that the second physical erasing unit group The amount of data stored in the physical erasure unit group reaches the fourth threshold. At this time, the memory management circuit 502 may perform an erasure operation on the physical erasure unit 440(1) of the first physical erasure unit group, as shown in FIG. 12B.

In other words, in the data writing method of the present invention, when the amount of data stored in the second physical erasure unit group reaches the capacity of the second physical erasure unit group that can be used to store data (i.e., the second physical erasure unit group When all 16 physical programming units in the erasure unit group have been written with data), the physical erasure unit 410(1), the physical erasure unit 420(1), and the physical erasure unit of the first physical erasure unit group 430(1) and the data stored in the physical erasure unit 440(1) have been erased. Therefore, after completing the aforementioned write operations corresponding to data ND1 to ND16, since the second physical erasure unit group will return to the idle state, when the host system 11 continues to issue write instructions, the memory management circuit 502 can directly The second group of physical erase units is written in parallel.

It should be noted here that the first of the physical erasing unit 410(0), the physical erasing unit 420(0), the physical erasing unit 430(0) and the physical erasing unit 440(0) may be used here. Each physical programming unit is called a "first physical programming unit", and the physical erasing unit 410(0), the physical erasing unit 420(0), the physical erasing unit 430(0) and the physical erasing unit 440 are The second entity programming unit in (0) is called the "second entity programming unit". In particular, during the parallel writing process, the physical erasure unit 410(0), the physical erasure unit 420(0), the physical erasure unit 430(0), and the physical erasure unit 440(0) After one physical programming unit is programmed first, the physical erasing unit 410(0), the physical erasing unit 420(0), the physical erasing unit 430(0) and the physical erasing unit 440(0) Only the second entity programming unit can be programmed.

In addition, it is assumed that the aforementioned data ND1 to ND16 are continuous data. In other words, the data of data ND1 to ND16 are data ND1 to ND16 in order. In the aforementioned example, the physical erasure unit group composed of the physical erasure unit 410(0), the physical erasure unit 420(0), the physical erasure unit 430(0), and the physical erasure unit 440(0) is used to write consecutive data ND1 to ND16, so the physical erase unit 410(0), the physical erase unit 420(0), the physical erase unit 430(0) and the physical erase unit 440(0) store The multiple logical addresses corresponding to the data are consecutive. For example, the first physical programming unit in the physical erasure unit 410(0), the physical erasure unit 420(0), the physical erasure unit 430(0) and the physical erasure unit 440(0) is respectively used. The data ND1 to ND4 are stored, and the multiple logical addresses corresponding to the data ND1 to ND4 are consecutive.

It should be noted that in the foregoing, continuous data ND1 to ND16 are written in parallel to the physical erasure unit 410(0), the physical erasure unit 420(0), the physical erasure unit 430(0) and the physical erasure unit 440. In the process of (0), the data stored in multiple physical programming units in the same physical erasure unit are discontinuous with each other. For example, taking the physical erasure unit 430(0) (also known as the seventh physical erasure unit) as an example, the data ND3 stored in the first physical programming unit of the physical erasure unit 430(0) is The corresponding logical address is discontinuous with the logical address corresponding to the data ND7 stored in the second physical programming unit of the physical erasing unit 430(0). However, in the physical erasure unit 430(0), the first physical programming unit of the physical erasure unit 430(0) and the second physical programming unit of the physical erasure unit 430(0) are physically continuous. arranged ground. Other entity erasure units also have similar phenomena, which will not be described again here.

Through the aforementioned method, since the memory management circuit 502 will not perform the erase operation on all physical erasure units in a physical erasure unit group at the same time point, not all memory sub-modules are used to perform the erase operation at the same time point. delete operation. In this way, problems caused by simultaneously performing erasure operations on all memory sub-modules in the rewritable non-volatile memory 406 in the prior art can be avoided, and the capacity of the buffer memory 510 can be effectively reduced.

[Second Embodiment]

FIG. 13 is a schematic diagram of an example of a data erasure method according to a second exemplary embodiment of the present invention. It should be noted here that in the second embodiment of the present invention, the memory management circuit 502 adjusts the order in which write operations are performed on multiple physical erasure units in a physical erasure unit group, thereby allowing these The physical erase unit will not be filled with data at the same time. In particular, the physical erase unit that is filled with data first can be used to perform the erase operation first, thereby avoiding the simultaneous execution of all memory sub-modules in the rewritable non-volatile memory 406 in the prior art. Problems caused by erasure operations.

Specifically, please refer to FIG. 13 , where it is assumed that the aforementioned first physical erasure unit group is written. Assume that the host system 11 issues a write command to write data ID1 to ID8 into the rewritable non-volatile memory 10 . The memory management circuit 502 may perform a write operation on the first physical erasure unit group according to the write instruction issued by the host system 11 . In particular, unlike the parallel writing method used in the prior art, in the second embodiment of the present invention, the memory management circuit 502 adjusts the writing to a plurality of first physical erasing units in the first erasing unit. The order of operations. For example, the memory management circuit 502 may obtain the order of performing write operations on multiple physical erasure units in a physical erasure unit group according to an algorithm or a lookup table. In particular, the present invention is not intended to limit the order of write operations and the manner in which the order is generated and obtained.

Here, it is assumed that the order of write operations obtained by the memory management circuit 502 according to the algorithm or lookup table is "physical erasure unit 410(1), physical erasure unit 420(1), physical erasure unit 410(1). ), physical erasure unit 420(1), physical erasure unit 430(1), physical erasure unit 440(1), physical erasure unit 420(1) and physical erasure unit 420(1)". The memory management circuit 502 will perform operations on the physical erasure unit 410(1), the physical erasure unit 420(1), the physical erasure unit 430(1) and the physical erasure unit 440( 1) Perform a write operation. In more detail, the memory management circuit 502 writes data ID1 to the physical erasure unit 410(1), writes data ID2 to the physical erasure unit 420(1), and writes data ID3 to the physical erasure unit 420(1) according to the aforementioned writing sequence. Write to the physical erase unit 410(1), write data ID4 to the physical erase unit 420(1), write data ID5 to the physical erase unit 430(1), write data ID6 to the physical erase unit erase unit 440(1), write data ID7 to the physical erase unit 420(1), and write data ID8 into the physical erase unit 420(1). The result is as shown in FIG. 13 .

That is to say, in the second embodiment of the present invention, when the storage space of a physical erasure unit (for example, the physical erasure unit 420(1)) in a physical programming unit group is filled, the physical program At least one other physical erasure unit in the unit group still has available storage space. In particular, the physical erase unit that is filled with data first can be used to perform the erase operation first, thereby avoiding the simultaneous execution of all memory sub-modules in the rewritable non-volatile memory 406 in the prior art. Problems caused by erasure operations.

Based on the above, in the data erasure method, memory control circuit unit and memory storage device of the present invention, since the erasure operation will not be performed on all physical erasure units in a physical erasure unit group at the same time, therefore at the same time Not all memory sub-modules are used to perform erase operations at this point in time. At this time, when the host system continues to issue write instructions, the data from the host system can be written into the rewritable non-volatile memory without being temporarily stored in the buffer memory to wait for the completion of the erasure operation. Thereby, the data erasing method of the present invention does not use a buffer memory with a large capacity and avoids the problem caused by all memory sub-modules in the rewritable non-volatile memory being used to perform erasing operations at the same time.

Although the present invention has been disclosed above through embodiments, they are not intended to limit the present invention. Any person skilled in the art can make some modifications and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the claims.

Claims (27)

1. A data erasure method for a rewritable non-volatile memory module, the rewritable non-volatile memory module includes a plurality of physical erasure unit groups, the plurality of physical erasure unit groups Each physical erasure unit group in has multiple physical erasure units, characterized in that the data erasure method includes: Select a first physical erasure unit group from the plurality of physical erasure unit groups; Perform an erasure operation on the first physical erasure unit group, wherein the first physical erasure unit group includes a plurality of first physical erasure units and is used to perform the erasure operation at the same point in time. The number of at least one second physical erasure unit among the plurality of first physical erasure units is different from the number of the plurality of first physical erasure units; Perform a write operation on a second physical erasure unit group among the plurality of physical erasure unit groups according to at least one write instruction, wherein the second physical erasure unit group includes a plurality of third physical erasure units; When the amount of data stored in the second physical erasing unit group reaches a first threshold, performing the step of performing the erasing operation on the first physical erasing unit group to erase the plurality of first physical erasing units. A fourth physical erasing unit among the physical erasing units performs the erasing operation; and When the amount of data stored in the second physical erasing unit group reaches a second threshold, performing the step of performing the erasing operation on the first physical erasing unit group to erase the plurality of first physical erasing units. The fifth physical erasing unit in the physical erasing unit performs the erasing operation, The first threshold value is smaller than the second threshold value. 2. The data erasing method according to claim 1, wherein when the amount of data stored in the second physical erasing unit group reaches the capacity of the second physical erasing unit group that can be used to store data, the The data stored in the plurality of first physical erasure units of the first physical erasure unit group have all been erased. 3. The data erasing method according to claim 1, wherein the rewritable non-volatile memory module includes a plurality of memory sub-modules, and the plurality of memory sub-modules are respectively connected to the memory control circuit unit through a plurality of channels. , the plurality of physical erasing units of each of the plurality of physical erasing unit groups respectively belong to different memory sub-modules among the plurality of memory sub-modules. 4. The data erasing method according to claim 3, wherein the memory control circuit unit performs on the plurality of third physical erasing units in the second physical erasing unit group through the plurality of channels. The writing operation is to write a plurality of data into the plurality of third physical erasing units in parallel. 5. The data erasing method according to claim 1, wherein before performing the erasing operation on the first physical erasing unit group, the method further comprises: Adjust the order in which the write operations are performed on the plurality of first physical erasure units; and The writing operation is performed on the plurality of first physical erasing units according to the writing sequence and the at least one writing instruction, so that when the storage space of the second physical erasing unit is full, the writing operation is performed on the plurality of first physical erasing units. At least one sixth physical erasing unit among the plurality of first physical erasing units still has available storage space. 6. The data erasing method according to claim 1, wherein among the plurality of physical erasing unit groups, the plurality of physical erasing units in the same physical erasing unit group correspond to a logical address - The same index code in the entity address mapping table. 7. The data erasing method according to claim 1, wherein each of the plurality of first physical erasing units in the first physical erasing unit group includes a first physical programming unit and a second physical program. ization unit, After the first physical programming unit of each of the first physical erasing units is programmed first, the second physical programming unit of each of the first physical erasing units Only then can it be programmed. 8. The data erasure method according to claim 1, wherein each of the plurality of first physical erasure units in the first physical erasure unit group includes a first physical programming unit, When the first physical erasure unit group is written with continuous data, the plurality of physical programming units stored in the first physical erasure unit in the first physical erasure unit group Multiple logical addresses corresponding to data are consecutive. 9. The data erasing method according to claim 1, wherein each of the plurality of first physical erasing units in the first physical erasing unit group includes a first physical programming unit and a second physical program. ization unit, When the first physical erasure unit group is written with continuous data, the data stored in the first physical programming unit of the seventh physical erasure unit in the first physical erasure unit group corresponds to The logical address corresponding to the data stored in the second physical programming unit of the seventh physical erasing unit is discontinuous, and the first physical program of the seventh physical erasing unit The programming unit and the second physical programming unit are physically continuously arranged. 10. A memory control circuit unit for controlling a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical erasure unit groups, and the plurality of physical erasure units Each physical erasure unit group in the unit group has multiple physical erasure units, characterized in that the memory control circuit unit includes: Host interface, used to electrically connect to the host system; A memory interface for electrically connecting to the rewritable non-volatile memory module; A memory management circuit electrically connected to the host interface and the memory interface, wherein the memory management circuit is used to select a first physical erasure unit group from the plurality of physical erasure unit groups, The memory management circuit is further used to perform an erasure operation on the first physical erasure unit group, wherein the first physical erasure unit group includes a plurality of first physical erasure units, and at the same point in time The number of at least one second physical erasing unit among the plurality of first physical erasing units used to perform the erasing operation is different from the number of the plurality of first physical erasing units, The memory management circuit is further configured to perform a write operation on a second physical erasure unit group among the plurality of physical erasure unit groups according to at least one write instruction, wherein the second physical erasure unit group includes Multiple third entity erasure units, When the amount of data stored in the second physical erasure unit group reaches a first threshold, the memory management circuit is further configured to perform an operation of performing the erase operation on the first physical erasure unit group. to perform the erasing operation on a fourth physical erasing unit among the plurality of first physical erasing units, When the amount of data stored in the second physical erasure unit group reaches a second threshold, the memory management circuit is also used to perform the operation of performing the erase operation on the first physical erasure unit group. to perform the erasing operation on a fifth physical erasing unit among the plurality of first physical erasing units, The first threshold value is smaller than the second threshold value. 11. The memory control circuit unit according to claim 10, wherein when the amount of data stored in the second physical erasure unit group reaches a capacity of the second physical erasure unit group that can be used to store data, the The data stored in the plurality of first physical erasure units of the first physical erasure unit group have all been erased. 12. The memory control circuit unit according to claim 10, wherein the rewritable non-volatile memory module includes a plurality of memory sub-modules, and the plurality of memory sub-modules are respectively connected to the memory management through a plurality of channels. In a circuit, the plurality of physical erasing units of each of the plurality of physical erasing unit groups respectively belong to different memory sub-modules among the plurality of memory sub-modules. 13. The memory control circuit unit according to claim 12, wherein the memory management circuit performs the plurality of third physical erasure units in the second physical erasure unit group through the plurality of channels. The writing operation is to write a plurality of data into the plurality of third physical erasing units in parallel. 14. The memory control circuit unit of claim 10, wherein before performing the erase operation on the first physical erase unit group, The memory management circuit is also used to adjust the order in which the write operations are performed on the plurality of first physical erasure units, The memory management circuit is further configured to perform the write operation on the plurality of first physical erasure units according to the writing sequence and the at least one write instruction, so that when the storage of the second physical erasure unit When the space is full, at least one sixth physical erasing unit among the plurality of first physical erasing units still has usable storage space. 15. The memory control circuit unit according to claim 10, wherein among the plurality of physical erasure unit groups, the plurality of physical erasure units in the same physical erasure unit group correspond to a logical address-physical The same index code in the address mapping table. 16. The memory control circuit unit of claim 10, wherein each of the plurality of first physical erasure units in the first physical erasure unit group includes a first physical programming unit and a second physical program ization unit, After the first physical programming unit of each of the first physical erasing units is programmed first, the second physical programming unit of each of the first physical erasing units Only then can it be programmed. 17. The memory control circuit unit of claim 10, wherein each of the plurality of first physical erase units in the first physical erase unit group includes a first physical programming unit, When the first physical erasure unit group is written with continuous data, the plurality of physical programming units stored in the first physical erasure unit in the first physical erasure unit group Multiple logical addresses corresponding to data are consecutive. 18. The memory control circuit unit of claim 10, wherein each of the plurality of first physical erasure units in the first physical erasure unit group includes a first physical programming unit and a second physical program ization unit, When the first physical erasure unit group is written with continuous data, the data stored in the first physical programming unit of the seventh physical erasure unit in the first physical erasure unit group corresponds to The logical address corresponding to the data stored in the second physical programming unit of the seventh physical erasing unit is discontinuous, and the first physical program of the seventh physical erasing unit The programming unit and the second physical programming unit are physically continuously arranged. 19. A memory storage device, characterized by comprising: The connection interface unit is used to electrically connect to the host system; A rewritable non-volatile memory module, the rewritable non-volatile memory module includes a plurality of physical erasure unit groups, each of the plurality of physical erasure unit groups has a plurality of physical erasure units; and a memory control circuit unit electrically connected to the connection interface unit and the rewritable non-volatile memory module, wherein the memory control circuit unit is used to select a first physical erasure unit group from the plurality of physical erasure unit groups, The memory control circuit unit is further used to perform an erasure operation on the first physical erasure unit group, wherein the first physical erasure unit group includes a plurality of first physical erasure units, and at the same point in time The number of at least one second physical erasing unit among the plurality of first physical erasing units used to perform the erasing operation is different from the number of the plurality of first physical erasing units, The memory control circuit unit is further configured to perform a write operation on a second physical erase unit group among the plurality of physical erase unit groups according to at least one write instruction, wherein the second physical erase unit group Including multiple third entity erasure units, When the amount of data stored in the second physical erasure unit group reaches a first threshold, the memory control circuit unit is also used to perform the erase operation on the first physical erasure unit group. the step of performing the erasing operation on a fourth physical erasing unit among the plurality of first physical erasing units, When the amount of data stored in the second physical erasure unit group reaches a second threshold, the memory control circuit unit is also used to perform the erase operation on the first physical erasure unit group. the step of performing the erasing operation on a fifth physical erasing unit among the plurality of first physical erasing units, The first threshold value is smaller than the second threshold value. 20. The memory storage device of claim 19, wherein when the amount of data stored in the second physical erasure unit group reaches a capacity of the second physical erasure unit group that can be used to store data, the The data stored in the plurality of first physical erasure units of the first physical erasure unit group have all been erased. 21. The memory storage device according to claim 19, wherein the rewritable non-volatile memory module includes a plurality of memory sub-modules, and the plurality of memory sub-modules are respectively connected to the memory control circuit unit through a plurality of channels, The plurality of physical erasure units in each of the plurality of physical erasure unit groups respectively belong to different memory sub-modules among the plurality of memory sub-modules. 22. The memory storage device according to claim 21, wherein the memory control circuit unit performs the plurality of third physical erasure units in the second physical erasure unit group through the plurality of channels. The writing operation is to write a plurality of data into the plurality of third physical erasing units in parallel. 23. The memory storage device of claim 19, wherein before performing the erase operation on the first physical erase unit group, The memory control circuit unit is also used to adjust the order in which the write operations are performed on the plurality of first physical erasure units, The memory control circuit unit is further configured to perform the writing operation on the plurality of first physical erasing units according to the writing sequence and the at least one writing instruction, so that when the second physical erasing unit When the storage space is full, at least one sixth physical erasing unit among the plurality of first physical erasing units still has usable storage space. 24. The memory storage device according to claim 19, wherein among the plurality of physical erasure unit groups, the plurality of physical erasure units in the same physical erasure unit group correspond to a logical address-physical address. The same index code in the mapping table. 25. The memory storage device of claim 19, wherein each of the plurality of first physical erase units in the first group of physical erase units includes a first physical programming unit and a second physical programming unit. unit, After the first physical programming unit of each of the first physical erasing units is programmed first, the second physical programming unit of each of the first physical erasing units Only then can it be programmed. 26. The memory storage device of claim 19, wherein each of the plurality of first physical erase units in the first group of physical erase units includes a first physical programming unit, When the first physical erasure unit group is written with continuous data, the plurality of physical programming units stored in the first physical erasure unit in the first physical erasure unit group Multiple logical addresses corresponding to data are consecutive. 27. The memory storage device of claim 19, wherein each of the plurality of first physical erase units in the first group of physical erase units includes a first physical programming unit and a second physical programming unit. unit, When the first physical erasure unit group is written with continuous data, the data stored in the first physical programming unit of the seventh physical erasure unit in the first physical erasure unit group corresponds to The logical address corresponding to the data stored in the second physical programming unit of the seventh physical erasing unit is discontinuous, and the first physical program of the seventh physical erasing unit The programming unit and the second physical programming unit are physically continuously arranged.