CN112214196A

CN112214196A - Floating-point exception handling method and device

Info

Publication number: CN112214196A
Application number: CN202011117866.2A
Authority: CN
Inventors: 袁苗苗; 张稚
Original assignee: Shanghai Zhaoxin Integrated Circuit Co Ltd
Current assignee: Shanghai Zhaoxin Integrated Circuit Co Ltd
Priority date: 2020-10-19
Filing date: 2020-10-19
Publication date: 2021-01-12

Abstract

The present disclosure relates to a floating-point exception handling method and apparatus. The floating-point exception processing method includes: if a floating-point exception is detected in the operand of the floating-point operation, in the process of performing the floating-point operation on the operand by using an operator corresponding to the operation type of the floating-point operation to obtain the operation result, according to the following steps: The operand is corrected by the number of leading zeros; if it is detected that the operand does not have a floating-point exception, the operand corresponding to the operation type of the floating-point operation is directly used to perform the floating-point operation on the operand to obtain the operation result; if the operation The result overflows, and the operation result is corrected. According to the floating-point exception processing method and device according to the embodiments of the present application, the repeated execution of the cycle repair process is avoided, and complex interaction between multiple modules is not required. Processing flexibility, thereby improving computing efficiency.

Description

Floating point exception handling method and device

Technical Field

The present disclosure relates to the field of computer technologies, and in particular, to a floating point exception handling method and apparatus.

Background

The IEEE (institute of electrical and electronic engineering) standard for floating-point arithmetic (IEEE 754) specifies how to represent floating-point numbers of single precision, double precision, single extended precision, and double extended precision.

IEEE 754 Standard with V (-1)^s*M*2^EApproximately representing a number. And the bit representation of a floating point number is divided into three fields:

the sign (sign) s field determines whether this number is a negative number or a positive number, where s-0 denotes a positive number and s-1 denotes a negative number.

The mantissa (also called mantissa, hereinafter abbreviated as man) M is a binary decimal number with a range of 1-2-xi or 0-1-xi, and the mantissa field M is an n-bit decimal field frac ═ f_n-1…f₀And (5) encoding.

The exponent E acts to weight floating point numbers to the power E of 2 (which may be negative).

The length of a single-precision floating point number defined by the IEEE 754 standard is 32 bits, the length of a double-precision floating point number is 64 bits, the length of an extended double-precision floating point number is 80 bits, and the extended double-precision floating point number can be divided into the following parts according to bit fields: a sign field, an exponent field, and a mantissa field. As shown in Table 1

TABLE 1 Floating Point number definition

Single precision	S(31)	exp: 8 bit (30 to 23)	frac: 23 bit (22 to 0)
				Double precision	S(63)	exp: 11 bit (62 to 52)	frac: 52 bit (51 to 0)
Extended double precision	S(79)	exp: 15 bit (78 to 64)	frac: 64 bit (63 to 0)

Depending on the value of the exponent field exp, the encoded value can be divided into three different classes.

Case 1: normalized value

In the most general case, when the value of the exponent field exp (exp) is not all 0's nor all 1's. In this case, the order field is interpreted as representing a signed integer in the form of offset (biased), and in the case of a single precision floating point, the exponent field exp is 8 bits, exp is an unsigned number, and the expressible range is (1 to 254), and in order for the exponent field exp to express a signed number, the offset value Bias is set, and for a single precision floating point, Bias is 127, E is exp-Bias, and therefore, the exponent E ranges from-126 to + 127.

frac is described as a fractional value, and 0 ≦ frac <1, which is binary represented as 0. frac. The mantissa is defined as M ═ 1+ frac, and then M ═ 1. frac. Then there is 1. ltoreq. M <2, and since the order code E can be adjusted so that M is in the range 1. ltoreq. M <2, the displayed representation "1" is not needed, which also results in an extra precision bit. That is, when storing M internally in a computer, the first bit of the number is always 1 by default (i.e. the default bit implicitit bit, hereinafter imp), and therefore can be discarded, only the following frac portion is stored, and the first bit of 1 is added when reading the mantissa.

Case 2: unnormalized values

When the exponent field exp has a value of all 0's, the number represented is denormal, in which case the order value E is 1-Bias (a method is provided for converting from an unformatted value to a formatted value). Mantissa M ═ frac.

The denormal number has two roles:

(1) representing a value of 0. In the normalized number, M.gtoreq.1 is always present, and therefore 0 cannot be represented. When the exponent field is all 0's and the mantissa is also all 0's, the exponent field may represent a value of 0.

(2) Representing a number close to 0.0. The value it represents is distributively close to 0.0, and this property causes the value represented to gradually overflow (underflow). Denormals are under-filled by stages because they allow slow (gradual) degradation of precision when the results are small.

Case 3: special value

There are two types:

(1) the codes are all 1, and the decimal fields are all 0. The values expressed are + ∞ (s ═ 0) or- ∞ (s ═ 1), and the result of an overflow can be expressed in a computer, for example, by multiplying two very large numbers.

(2) The levels are all 1, and the decimal fields are not all 0. The indicated value is nan (note a number). An illegal number can be represented in the computer, for example, a value when the root number-1 is calculated.

For example, a binary single precision floating point format of a value of 1.0 may be represented as 2^ 0x 1.0, where the sign bit is 0, the exponent field is 0+127 ═ 127, and the mantissa bits are all 0. Thus, the binary single precision floating point format of the value 1.0 may be represented as 00111111100000000000000000000000 (7F 00000).

Disclosure of Invention

In view of this, the present disclosure provides a method and an apparatus for processing a floating-point exception, which can correct a downward overflow of an operation result, flexibly select a floating-point operation process according to different input operands, and improve operation efficiency.

In a first aspect, an embodiment of the present application provides a method for processing a floating-point exception of a floating-point operation, where the method is applied to a floating-point operation unit FPU, and the method includes:

detecting the operation type of the floating-point operation and whether floating-point exceptions exist in the operand of the floating-point operation;

if the floating point abnormality of the operand is detected, determining the leading zero number of the operand with the floating point abnormality, and correcting the operand according to the leading zero number in the process of carrying out floating point operation on the operand by adopting an arithmetic unit corresponding to the operation type of the floating point operation to obtain an operation result;

if the operand is detected to have no floating point exception, directly adopting an arithmetic unit corresponding to the operation type of the floating point operation to carry out the floating point operation on the operand to obtain an operation result;

and if the operation result overflows downwards, correcting the operation result.

The floating point exception repairing of the operand is arranged inside the FPU, so that the repeated execution of the cyclic repairing process can be avoided, the complex interaction among multiple modules is not needed, and the operation performance can be improved. According to the floating point exception handling method of the embodiment of the application, the correction of the downward overflow of the operation result can be realized, the process of the floating point operation is flexibly selected according to different input operands, and the operation efficiency is improved.

With reference to the first aspect, in a first possible implementation manner, the floating-point operation is a multiplication operation, the operation result is a first multiplication result, and the first multiplication result includes a first exponent result and a first mantissa result;

in the process of performing floating-point operation on the operand by adopting an arithmetic unit corresponding to the operation type of the floating-point operation to obtain an operation result, correcting the operand according to the leading zero number, and the method comprises the following steps:

and calculating by adopting a multiplier according to the exponent and the leading zero number of the operand of the multiplication operation to obtain the first exponent result, and multiplying the mantissas of the operand of the multiplication operation to obtain the first mantissa result.

With reference to the first possible implementation manner of the first aspect, in a second possible implementation manner, if the operation result overflows downwards, the modifying the operation result includes:

judging whether the first multiplication result overflows downwards or not according to the size relation between the first exponent result and the minimum exponent;

if the first multiplication result overflows downwards, calculating a first mantissa shift number and a second exponent result according to the minimum exponent and the first exponent result;

shifting the first mantissa result according to the first mantissa shift number to obtain a second mantissa result;

and converting according to the second mantissa result and the second exponent result to obtain a second multiplication result in a floating point format.

With reference to the second possible implementation manner of the first aspect, in a third possible implementation manner, the calculating a first mantissa shift number and a second exponent result according to the minimum exponent and the first exponent result includes:

calculating a first mantissa shift number according to the minimum exponent and a first exponent result;

and calculating a second exponent result according to the first exponent result and the first mantissa shift number.

With reference to the second possible implementation manner of the first aspect, in a fourth possible implementation manner, if the operation result overflows downwards, the correcting the operation result further includes:

if the first multiplication result does not overflow downwards, calculating a second mantissa shift number according to the leading zero number of the first mantissa result and the leading zero number of the operand;

shifting the first mantissa result according to the second mantissa shift number and the leading zero number of the input operand to obtain a second mantissa result, and calculating according to the second mantissa shift number and the first exponent result to obtain a second mantissa result;

The method of the embodiment of the application reduces the number of shifts, namely, the implementation process of the operation method of the embodiment of the application is more friendly to operation time and circuit area.

With reference to the first aspect, in a fifth possible implementation manner, the floating-point operation is a division operation, the operation result is a first division result,

normalizing the operand according to the number of leading zeros;

and performing division operation on the normalized operand by adopting a divider to obtain the first division result.

With reference to the fifth possible implementation manner of the first aspect, in a sixth possible implementation manner, the first division result includes a third exponent result and a third mantissa result;

if the operation result overflows downwards, correcting the operation result, wherein the correction comprises the following steps:

judging whether the first division result overflows downwards or not according to the magnitude relation between the third exponential result and the minimum exponent;

under the condition that the first division result overflows downwards, calculating a third mantissa shift number according to the minimum exponent and the third exponent result, and calculating a fourth exponent result according to the third exponent result and the third mantissa shift number;

shifting the third mantissa result according to the third mantissa shift number, and rounding the third mantissa result according to a rounding mode to obtain a fourth mantissa result;

and converting according to the fourth mantissa result and the fourth exponent result to obtain a second division result in a floating point format.

With reference to the sixth possible implementation manner of the first aspect, in a seventh possible implementation manner, if the operation result overflows downwards, the correcting the operation result further includes:

judging whether normalization processing needs to be carried out on the third mantissa result or not according to the leading zero number of the third mantissa result under the condition that the first division result does not overflow downwards;

if the third mantissa result does not need to be normalized, a second division result in a floating point format is obtained directly according to the third exponent result and the third mantissa result;

if the third mantissa result needs to be normalized, the third mantissa result is shifted to the left by one bit to obtain a fourth mantissa result, the third exponent result is subtracted by 1 to obtain a fourth exponent result, and the fourth exponent result are converted to obtain a second division result in a floating point format.

With reference to the first aspect or any one of the first to seventh possible implementation manners of the first aspect, in an eighth possible implementation manner, the method further includes:

before floating-point operation is carried out on the operand by adopting an arithmetic unit corresponding to the operation type of the floating-point operation, bit width expansion is carried out on the operand.

The multiple operands in the same channel can be unified into the same bit width by expanding the bit width of the operands, the precision of the multiple operands input after expanding is the same, and if the operation result overflows downwards, the precision of the operation result can be improved by the wider bit width.

In a second aspect, an embodiment of the present application provides a floating point exception handling apparatus, including: a detection module, a leading zero counter, a multiplier and a divider,

the detection module is connected with a leading zero counter, and the leading zero counter is respectively connected with a multiplier and a divider;

when the detection module detects that the floating-point operation is multiplication operation or division operation and an operand of the floating-point operation is abnormal, the leading zero counter is used for calculating the number of leading zeros of the operand with the abnormal floating-point operation, and the multiplier and the divider are used for correcting the operand according to the number of the leading zeros in the process of executing the floating-point operation to obtain an operation result;

when the detection module detects that the floating-point operation is multiplication operation or division operation and the operand of the floating-point operation is not abnormal, the multiplier and the divider are used for directly carrying out the floating-point operation on the operand to obtain an operation result;

and if the operation result overflows downwards, the multiplier and the divider are also used for correcting the operation result.

The floating point exception repairing of the operand is arranged inside the FPU, so that the repeated execution of the cyclic repairing process can be avoided, the complex interaction among multiple modules is not needed, and the operation performance can be improved. According to the floating point exception handling device of the embodiment of the application, the correction of the downward overflow of the operation result can be realized, the process of the floating point operation is flexibly selected according to different input operands, and the operation efficiency is improved.

In a first possible implementation manner with reference to the second aspect, the floating-point operation is a multiplication operation, the operation result is a first multiplication result, and the first multiplication result includes a first exponent result and a first mantissa result;

the multiplier comprises a multiplication unit, wherein the multiplication unit is used for calculating according to the exponent of the operand and the leading zero number to obtain the first exponent result, and multiplying the mantissas of the operand subjected to multiplication to obtain the first mantissa result.

With reference to the first possible implementation manner of the second aspect, in a second possible implementation manner, when the detection module detects that the operand of the floating-point operation has a floating-point exception, the multiplication unit obtains the leading zero number of the operand from the leading zero counter;

and when the detection module detects that the operand of the floating-point operation has no floating-point abnormality, the multiplication unit sets the leading zero number to 0.

With reference to the first possible implementation manner of the second aspect, in a third possible implementation manner, the multiplier further includes a first underflow correcting unit;

the first overflow correcting unit is used for correcting the first multiplication result under the condition that the first multiplication result is judged to overflow downwards according to the first exponential result.

With reference to the third possible implementation manner of the second aspect, in a fourth possible implementation manner, the first underflow correcting unit is configured to determine whether the first multiplication result overflows downwards according to a size relationship between the first exponent result and a minimum exponent;

if the first multiplication result overflows downwards, the first underflow correcting unit calculates a first mantissa shift number and a second mantissa result according to the minimum exponent and the first exponent result, shifts the first mantissa result according to the first mantissa shift number, and rounds the first mantissa result according to a rounding mode to obtain a second mantissa result.

With reference to the fourth possible implementation manner of the second aspect, in a fifth possible implementation manner, the first underflow correcting unit is configured to, if the first multiplication result overflows downwards, calculate a first mantissa shift number according to the minimum exponent and the first exponent result, and calculate a second exponent result according to the first exponent result and the first mantissa shift number.

With reference to the fourth possible implementation manner of the second aspect, in a sixth possible implementation manner, the first underflow correcting unit is further configured to calculate a second mantissa shift number according to the leading zero number of the first mantissa result and the leading zero number of the operand if the first multiplication result does not overflow downwards;

and shifting the first mantissa result according to the second mantissa shift number and the leading zero number of the input operand to obtain a second mantissa result, and calculating according to the second mantissa shift number and the first exponent result to obtain a second mantissa result.

With reference to the fourth or sixth possible implementation manner of the second aspect, in a seventh possible implementation manner, the multiplier further includes a first format conversion unit,

and the first format conversion unit is used for converting the second mantissa result and the second exponent result to obtain a second multiplication result in a floating point format.

In an eighth possible implementation manner combined with the second aspect, the floating-point operation is a division operation, the operation result is a first division result,

the divider comprises a normalization unit, a division unit and a second underflow correction unit;

the normalization unit is used for normalizing the abnormal operands according to the leading zero number of the operands when the detection module detects that the operands of the division operation are abnormal;

the division unit is used for executing division operation according to the normalized operand to obtain a first division result;

the second underflow correcting unit is configured to correct the first division result when the first division result is detected to overflow downwards.

With reference to the eighth possible implementation manner of the second aspect, in a ninth possible implementation manner, the first division result includes a third exponent result and a third mantissa result;

the second underflow correcting unit is used for judging whether the first division result overflows downwards or not according to the size relation between the third exponent result and the minimum exponent;

and shifting the third mantissa result according to the third mantissa shift number, and rounding the third mantissa result according to a rounding mode to obtain a fourth mantissa result.

With reference to the ninth possible implementation manner of the second aspect, in a tenth possible implementation manner, the second underflow correcting unit is further configured to, when the first division result does not overflow downwards, determine whether normalization processing needs to be performed on the third mantissa result according to the leading zero number of the third mantissa result;

if the third mantissa result needs to be normalized, the third mantissa result is shifted to the left by one bit to obtain a fourth mantissa result, and the third exponent result is subtracted by 1 to obtain a fourth exponent result.

With reference to the eighth possible implementation manner of the second aspect, in an eleventh possible implementation manner, the division unit is further configured to, when the detection module detects that there is no floating point abnormality in an operand of the division operation, directly perform the division operation on the operand of the division operation to obtain a first division result.

With reference to the ninth or tenth possible implementation manner of the second aspect, in a twelfth possible implementation manner, the divider further includes a second format conversion unit,

the second format conversion unit is used for converting the fourth mantissa result and the fourth exponent result to obtain a second division result in a floating point format;

or, if the second underflow correcting unit judges that normalization processing of the third mantissa result is not required, the second format converting unit is configured to directly convert the third exponent result and the third mantissa result to obtain the second division result in the floating point format.

In a thirteenth possible implementation manner in combination with the second aspect, the multiplier and the divider both include a bit width expansion unit, and the bit width expansion unit is configured to expand a bit width of an operand before performing a floating point operation on the operand.

In a third aspect, an embodiment of the present application provides a processing system, including:

a processor;

the memory is used for storing floating-point operation instructions executable by the processor and operands corresponding to the floating-point operation instructions;

the processor is configured to perform the method of the first aspect and any one of the possible implementations of the first aspect when the floating-point operation instruction is to process the operand.

Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.

Fig. 1 shows an application scenario of a floating point exception handling method in the related art.

FIG. 2 shows a block diagram of a floating point exception handling apparatus according to an embodiment of the present application.

FIG. 3 shows a block diagram of a floating point exception handling apparatus according to another embodiment of the present application.

FIG. 4 shows a flow diagram of a floating point exception handling method according to an embodiment of the present application.

Fig. 5a shows a schematic diagram of bit width expansion of an exponent field according to an embodiment of the present application.

Fig. 5b shows a schematic diagram of expanding the bit width of the mantissa field according to an embodiment of the present application.

FIG. 6 shows a flow diagram of a multiplication operation according to an embodiment of the present application.

FIG. 7 shows a flow diagram of a multiplication operation according to an embodiment of the present application.

Fig. 8 shows a block diagram of a multiplier according to an embodiment of the present application.

FIG. 9 shows a schematic diagram of an exponent adder and a unit for exponent underflow prediction according to an embodiment of the present application.

FIG. 10 shows a flow diagram of a division operation according to an embodiment of the present application.

FIG. 11 shows a flow diagram of a division operation according to an embodiment of the present application.

FIG. 12 shows a block diagram of a divider according to an embodiment of the present application.

FIG. 13 shows a schematic diagram of an exponent adder and a unit for exponent underflow prediction according to an embodiment of the application.

FIG. 14 shows a schematic diagram of a processing system 200 according to an embodiment of the present application.

Detailed Description

Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers can indicate functionally identical or similar elements. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.

The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.

Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the present disclosure.

When the processor runs an instruction to perform operation, an exception is triggered when a denormal number is used or generated, and the exception is transferred to a software module or other hardware to be processed. The way to handle exceptions is typically: the data is represented by a wider format because the wider format has sufficient precision to represent the denormal number as a smaller normalized number. This approach requires conversion of data between different formats and is computationally slow.

The processor can also be provided with an instruction for executing Single Instruction Multiple Data (SIMD) operation on floating point numbers, when the SIMD instruction is executed, if the SIMD instruction is used or generates denormal numbers, the processor can trigger the exception for multiple times, the exception needs to be processed circularly for multiple times, the operation performance is poor, and the complex interaction, the expansibility and the like can be caused by the multiple-time exception triggering.

In order to more clearly explain the solution of the present application, the application scenario and the technical problem to be solved will be explained in detail. Fig. 1 shows an application scenario of a floating point exception handling method in the related art. As shown in fig. 1, an MFX (media fix) module is disposed in the Reservation Station (RS), and is used for correcting the abnormality caused by denormal numbers and result underflow, where the result underflow may refer to the result of instruction operation overflowing downward, i.e., the underflow as described above. That is, there are mainly two types of data that need to be modified: one is exception caused by denormal number and exception masked (be masked); one is an exception caused by underflow of the result, and the exception is masked. The exception masking may refer to not triggering the exception to process an operand or a result, and may need to perform internal processing, which may refer to processing the exception at a reservation station.

The reservation station stores an instruction to be dispatched, and is responsible for dispatching the instruction to be dispatched to the execution Unit, for example, in an embodiment of the present application, the reservation station may dispatch an instruction of a Floating Point operation to a Floating Point Unit (FPU).

The floating-point operation execution unit shown in fig. 1 is further configured to perform floating-point exception detection, and if no floating-point exception is detected in an operand of an instruction or an operation result, after the floating-point operation execution unit executes the instruction, the complete state of the instruction may be set to 1 and sent to a reorder Buffer (ROB). If the floating-point operation execution unit detects that an operand of the instruction or an operation result has a floating-point exception, the floating-point operation execution unit may set a complete state of the instruction to 0 and send the complete state to the ROB, and the floating-point operation execution unit may further return exception information of the detected floating-point exception to the reservation station, so that the reservation station may correct the floating-point exception according to the exception information.

The ROB stores the information of the instructions to be reordered, and processes the instructions according to the information of the instructions. In one possible implementation, the ROBs store information of the instructions in the form of entries, and each entry of the ROB may include: 1) complete: indicating whether an instruction has been executed; 2) areg: the instruction is given in the form of a logic register in a destination register specified in an original program; 3) preg: after the aregs of the instruction are renamed through the register, the number of the corresponding physical register; 4) OPreg: before the Areg of the instruction is renamed to be the new Preg, the corresponding old Preg can use the value when the state is recovered due to the exception of the instruction; 5) PC: corresponding to the PC value of the instruction, when one instruction is interrupted or abnormal, the PC value of the instruction needs to be saved so as to be capable of re-executing the program; 6) exception: if an exception occurs in the instruction, the type of the exception is written into the exception, and when the instruction is to be retired (retire), the exception is processed; 7) type: the type of instruction is recorded, and when the instruction retires (retire), different types of instructions will have different actions. Therefore, the ROB may perform corresponding processing on the instruction according to the information of the instruction, for example, if the instruction has an exception and needs to be re-executed, the ROB may send the instruction (information of re-executing the instruction) back to the reservation station, and if the instruction has been processed, may send a retirement (reiire) to the next stage.

In the application scenario shown in fig. 1, for SIMD instructions, because the floating point exceptions handled by the Reservation Station (RS) at a time are limited, if there are exceptions in multiple operands of SIMD instructions, multiple cycles are required to be performed between the three units (RS, FPU, and ROB) shown in fig. 1 to correct all exceptions, resulting in poor operation performance, and multiple exception triggering results in complex interaction and non-extensibility.

For example, suppose a SIMD instruction has two operands, Source1 and Source2, Source1 and Source2, respectively, that are packed single precision floating point numbers, each Source containing four channels (channels), each channel being a 32-bit single precision floating point number. When the reservation station processes the floating point exceptions, the floating point exceptions of the operands are processed one by one according to the following priority: source1> Source2, SP0> SP1> SP2> SP 3.

If the four channels of operand Source1 are denormals, then the process of floating point exception handling may include:

step 1: the RS distributes the SIMD instruction to the FPU;

step 2: the FPU carries out floating point exception detection, detects that four channels of an operand Source1 are denormal numbers and have floating point exceptions, triggers the process of re-executing the instruction, sends the SIMD instruction to the ROB and returns exception information to the RS;

and step 3: the ROB returns the information of the re-execution SIMD instruction to the RS;

and 4, step 4: the RS modifies lane SP0 of operand Source1 based on the exception information and information from re-executing the SIMD instruction. And then returns to step 1 to dispatch the instruction to the FPU.

The above process is repeated until the floating point exceptions of all operands of the SIMD instruction are corrected and the execution of the SIMD instruction is completed, the ROB may send a retirement (retire) to the next stage.

Therefore, for the case of a floating point exception for four lanes with one operand, 4 cycles are required to complete the modification of the instruction. If the instruction has three operands, and four channels of each operand have floating point exception, the FPU will trigger 12 times re-execution processes, and as the operands increase and the precision expands, the complexity of the operation increases by times, which results in poor operation performance, and multiple times of exception triggering also results in complex interaction and inextensibility.

Although the related art has an adder, a multiplier or a divider supporting floating-point operation of denormal numbers, none of the conventional arithmetic units can correct the underflow of the operation result, and the processing flexibility and efficiency are insufficient for different input operands.

In order to solve the above technical problem, the present application provides a floating point exception handling apparatus. Fig. 2 is a block diagram of a floating-Point exception handling apparatus 2 according to an embodiment of the present application, and as shown in fig. 2, the floating-Point exception handling apparatus of the present application may be located in a floating-Point unit (FPU), where the FPU is configured to detect a floating-Point exception of an operand of an operation instruction (floating-Point operation) and/or an operation result, and correct the floating-Point exception during execution of the floating-Point operation. For the sake of clarity, other components that may also be included in the FPU have been omitted from the example of fig. 2, that is, fig. 2 is only one example of the present application and does not limit the present application in any way.

In an embodiment of the present application, the floating point exception handling apparatus 2 may include: a detection module 20, a leading zero counter 21, a multiplier 22 and a divider 23.

In the example shown in fig. 2, the detection module 20 may be connected to a leading zero counter 21, a multiplier 22 and a divider 23, the leading zero counter 21 being further connected to the multiplier 22 and the divider 23, respectively. It should be noted that the connection manner of the components shown in fig. 2 is only one example of the present application, and the present application is not limited thereto.

FIG. 3 shows a block diagram of a floating point exception handling apparatus 2 according to another embodiment of the present application. As shown in fig. 3, the detection module 20 may be connected to a multiplexing circuit 24 and a leading zero counter 21, the multiplexing circuit being connected to a multiplier 22 and a divider 23, respectively.

The detection module 20 is configured to detect an operation type of a floating-point operation and whether a floating-point exception exists in an operand of the floating-point operation.

In a possible implementation manner, the detection module 20 may be connected to the RS, and receive an operation instruction sent by the RS, where the operation instruction may include information about an operation type, so that the operation type of the floating-point operation may be identified according to the operation instruction. In the embodiments of the present application, the operation types of the floating-point operation may include addition (subtraction), multiplication, and division (root finding), but the addition and the subtraction are not the important points discussed in the present application, and the embodiments of the present application mainly aim at multiplication, division, root finding, and the like.

A floating point exception to an input operand may mean that the input operand is an denormal number. Since the normal number and the denormal number can be distinguished according to the value of the exponent field, the detection module 20 can detect whether the operand has a floating-point exception according to the exponent field of the operand, and if the detection module 20 detects that the value of the exponent field of the operand of the floating-point operation is all 0, the operand can be determined to be the denormal number, and the operand has the floating-point exception. If the detection module 20 detects that the values of the exponent fields of the operands of the floating-point operation are not all 0 or 1, the operands of the floating-point operation can be determined to be normalized numbers.

If the floating-point operation is identified as an addition operation or a subtraction operation, the detection module 20 may send an operation instruction to the adder. That is, the floating-point exception handling apparatus 2 according to the embodiment of the present application may further include an adder (not shown in fig. 2). In the embodiments of the present application, the adder may adopt any type of adder that supports floating-point operation of denormal numbers in the related art, and the present application does not limit this. For example, an adder having an N-R (Near-Remote) path structure may be used to select an N path or an R path for addition or subtraction according to the difference between exponent bits of an operand and significand bits of a mantissa.

When the detection module 20 detects that the floating-point operation is a multiplication or a division operation (root operation), and there is a floating-point exception in an operand of the floating-point operation, the leading-zero counter 21 is configured to count the number of leading zeros of the operand in which the floating-point exception exists.

When the detection module 20 detects that there is no floating point exception in the operand of the floating point operation, the operation instruction corresponding to the floating point operation may be directly output to the operator corresponding to the floating point operation, where the operator may be the multiplier 22 or the divider 23 as described above. For example, as shown in fig. 2, if the detection module 20 detects that the floating-point operation is a multiplication operation, the corresponding operation instruction may be output to the multiplier 22, and if the detection module 20 detects that the floating-point operation is a division operation or a root operation, the corresponding operation instruction may be output to the divider 23. Alternatively, as shown in fig. 3, if the detection module 20 detects that there is no floating-point exception to the operand, the operation instruction corresponding to the floating-point operation may be sent to the multiplexing circuit 24 and sent to the corresponding operator through the multiplexing circuit 24. The multiplexing circuit 24 may be designed according to the logic described above, and the specific circuit connection of the multiplexing circuit 24 is not limited in this application.

In the embodiment of the present application, a module for correcting floating point exceptions of operands and operation results may be provided in the multiplier 22 and the divider 23.

According to the floating point exception handling device provided by the embodiment of the application, the floating point exception of the operand is repaired inside the FPU, so that the process of repeatedly executing the loop repair can be avoided, the complex interaction among multiple modules is not required, and the operation performance can be improved. According to the floating point exception handling device of the embodiment of the application, the correction of the downward overflow of the operation result can be realized, the process of the floating point operation is flexibly selected according to different input operands, and the operation efficiency is improved.

The present application further provides a floating point exception handling method for floating point operations, which is applied to an FPU, and fig. 4 shows a flowchart of the floating point exception handling method according to an embodiment of the present application. As shown in fig. 4, the floating point exception handling method may include:

step S40, detecting the operation type of the floating-point operation and whether the operand of the floating-point operation has floating-point exception;

step S41, if detecting that the operand of the floating-point operation has floating-point abnormality, determining the leading zero number of the operand having floating-point abnormality, and correcting the operand according to the leading zero number in the process of performing the floating-point operation on the operand by adopting an arithmetic unit corresponding to the operation type of the floating-point operation to obtain an operation result; if the operation result overflows downwards, correcting the operation result;

in step S42, if it is detected that there is no floating point exception in the operand of the floating point operation, an arithmetic unit corresponding to the operation type of the floating point operation is used to perform the floating point operation to obtain an operation result, and if the operation result overflows downwards, the operation result is corrected.

The step S40 may be executed by the detection module 20, and the operation efficiency may be improved by detecting the operation type of the floating-point operation and whether the operand has a floating-point exception, and branching processing according to the detection result, and flexibly selecting the process of the floating-point operation for different input operands.

In one possible implementation, if a floating point exception is detected for any one or more of the operands of the floating point operation, then the operands of the floating point operation have a floating point exception. And if all operands of the floating-point operation are detected to be normalized numbers and no floating-point exception exists, the operands of the floating-point operation have no floating-point exception.

The operator corresponding to the operation type of the floating-point operation may include a multiplier 22 and a divider 23. In the embodiments of the present application, the addition operation and the subtraction operation performed by the adder are not within the scope of the discussion. Thus, the above operation types may include multiplication, division (root operation). If the operation type of the floating-point operation detected by the detection module 20 is a multiplication operation, a multiplier may be used for the floating-point operation, and if the operation type of the floating-point operation detected by the detection module 20 is a division operation (root operation), a divider 23 may be used for the floating-point operation. During the process of executing the floating-point operation, the arithmetic unit can correct the floating-point exception of the operand if the operand of the floating-point operation has the floating-point exception, and can correct the operation result if the operation result of the floating-point operation overflows downwards.

In a possible implementation manner, before the floating-point operation is performed by using the operator corresponding to the operation type of the floating-point operation, the bit width of the operand may be expanded to obtain the bit-width expanded operand, and the floating-point operation may be performed according to the bit-width expanded operand. The bit width expansion may refer to widening the number of bits representing floating point numbers. The multiple operands in the same channel can be unified into the same bit width by expanding the bit width of the exponent and the mantissa, the precision of the multiple operands input after expansion is the same, and if the operation result overflows downwards, the precision of the operation result can be improved by the wider bit width.

It should be noted that, if a plurality of channels are included, the FPU may perform bit width expansion on all or part of the input operands of the channels, and after the bit width expansion, the number of bits between the input operands of each channel may be the same or different, which is not limited in this application.

The application provides a way of expanding bit width, which expands the operand of floating-point operation into an EP (extended Double Precision) format, that is, expands the operand into 80 bits. Of course, the precision can be expanded to other precision according to the requirement of the actual application scenario, for example, a double-precision format, and the like, which is not limited in the present application. The bit width expansion method of the present application is described below by taking a floating point number expanded to an EP format as an example.

Since the exponent represented by IEEE 754 is biased, the bias value of the original format is removed and the bias value of the new format after expansion is added in the process of expanding the exponent field.

For the exponent field of the normalized number, the value of the exponent field after bit width expansion can be calculated from the value of the exponent field before bit width expansion by the following formula (1):

exp_dest＝exp_sour-Bias_sour+Bias_dest； (1)

wherein exp_sourThe value, Bias, which may represent the exponent field of a floating point number prior to bit width expansion_sourCan represent the bias of floating point number format before bit width expansionSetting, Bias_destMay represent a bias value, exp, in floating point number format after bit width expansion_destMay represent the value of the exponent field of the floating point number after bit width expansion. Bias_sourAnd Bias_destThe specific value of (2) is related to the format of the floating point number, for example, for a Single Precision (SP) floating point number, the Bias is⁷-1) ═ 127, for DP (Double Precision) floating point number, Bias is (2)¹⁰-1) 1023. For the EP format, the exponent bits are 17 bits when the instruction is actually executed (during implementation), so the Bias is (2)¹⁶-1)。

Table 2 shows an example of exponent field bit width extension (extended) of normalized numbers according to some embodiments of the present application, where 8'h7F is used as an example, 8' represents total 8 bits, h represents hexadecimal (b represents binary), and 7F represents its value.

TABLE 2

Fig. 5a shows a schematic diagram of bit width expansion of an exponent field according to an embodiment of the present application. As shown in FIG. 5a, if the input operand is in EP format, the value of the exponent field of the operand may be subtracted by 2¹⁴1, then 2¹⁶And 1, obtaining the value of the exponent field after bit width expansion.

For normalized numbers, 0 can be added directly after the original mantissa by increasing the number of bits as needed. For example, for an SP floating point number, if an EP is to be extended, 41 0's are added after the original mantissa; for a DP floating point number, 12 0's are added after the original mantissa if an EP is to be extended.

For an denormal number, the value of the exponent field after bit width expansion can be calculated from the value of the exponent field before bit width expansion by the following formula (2):

exp_dest＝-Bias_sour+Bias_dest-LZC_sour； (2)

wherein, LZC_sourThe number of leading zeros of the denormal floating-point number before bit width expansion can be represented, and since the value of the exponent field of the denormal number is 0, the value of the exponent field after bit width expansion can be calculated by expression (2).

Table 3 illustrates an example of exponent field bit width expansion for denormal numbers according to some embodiments of the present application

TABLE 3

Accuracy of measurement	sign	exp	man	exp_extend[16:0]
					SP[31:0]	sp[31]	8'h0	sp[22:0]	17'hFFFF-8'h7F-LZC_sp
DP[63:0]	dp[63]	11'h0	dp[51:0]	17'hFFFF-11'h3FF-LZC_dp
					EP[79:0]	ep[79]	15'h0	ep[62:0]	17'hFFFF-15'h3FFF-LZC_ep

For the mantissa field of the denormal number, 0 can also be added directly after the original mantissa according to the number of bits that need to be added.

Fig. 5b shows a schematic diagram of expanding the bit width of the mantissa field according to an embodiment of the present application. As shown in FIG. 5b, for SP floating point numbers (SP0), if we want to develop EP, we add 41 0 s after the original mantissa field (0: 22, 23 bits in total); for a DP floating point number (DP0), if extended to an EP, 12 0 s are added after the original mantissa field (0: 51, 52 bits total); for EP floating point numbers, bit width expansion is not needed.

It should be noted that the above way of expanding the bit width is only an example of the present application, and the present application is not limited in any way.

According to the floating point exception handling device provided by the embodiment of the application, the floating point exception of the operand is repaired inside the FPU, so that the process of repeatedly executing the loop repair can be avoided, the complex interaction among multiple modules is not required, and the operation performance can be improved. And different processing flows and modes are set according to whether the operand has floating point exception, so that the processing flexibility can be improved, and the operation efficiency is improved. The structures of the multiplier 22 and the divider 23 and the process of performing floating-point operations are described below, respectively.

Multiplier and multiplication operation

The multiplier 22 is configured to perform a multiplication operation, and in a possible implementation, as shown in fig. 2 or fig. 3, the multiplier 22 may include a multiplication unit 221 and a first underflow correction unit 222, where the multiplication unit 221 is configured to perform the multiplication operation to obtain a first multiplication result, and the first underflow correction unit 222 is configured to correct the first multiplication result if the first multiplication result is detected to overflow downwards.

In a possible implementation manner, the first multiplication result may include a first exponent result and a first mantissa result, and the first underflow modification unit 222 is configured to determine whether the first multiplication result overflows downwards according to the first exponent result and a minimum exponent, if the first exponent result is smaller than the minimum exponent, the first multiplication result overflows downwards, and if the first exponent result is not smaller than the minimum exponent, the first multiplication result does not overflow downwards.

In one possible implementation, the multiplier 22 may obtain a first exponent result by calculating an exponent corresponding to the value of the exponent field of the operand, the number of leading zeros, and an offset value corresponding to the operation result, where the exponent corresponding to the value of the exponent field of the operand may be a value obtained by subtracting the corresponding offset value from the value of the exponent field of the operand, and may also be referred to as an exponent of the operand; the offset value corresponding to the operation result may be an offset value in a floating point format corresponding to a preset operation result. The first exponent result may be obtained by summing the exponents of the operands, subtracting the leading zeros of the operands, and then adding the offset value corresponding to the result of the (input) operation.

In another possible implementation, the multiplier 22 may also calculate the first exponent result according to the exponent of the operand and the number of leading zeros. For example, the first exponent result may be obtained by summing the exponents of the operands and subtracting the leading zeros of the operands.

The two above manners of calculating the result of the first index may be different in determining whether the underflow is the corresponding minimum index. For example, in the first implementation, the minimum exponent may refer to the smallest number that the value of the number field can represent, and the minimum exponent may be 0. In a second implementation, the minimum exponent may be the minimum of the exponents in the format corresponding to a floating point number, for example, for an SP, the lowest exponent may be-127.

In one possible implementation, multiplier 22 may multiply the mantissa bits of the operand to obtain a first mantissa result.

In one possible implementation, in the case of a floating-point exception to an operand of a multiplication operation, if the first underflow modification unit 222 detects that the first multiplication result overflows downwards, the first underflow modification unit 222 may modify the first multiplication result according to a minimum exponent; in the case where there is no floating point exception to the operand of the multiplication operation, the first multiplication result does not overflow downward, and there is a possibility that the first mantissa result of the first multiplication result carries a carry, in which case the first exponent result may be adjusted according to the carry bit of the first mantissa result.

The procedure of the first overflow correction unit 222 correcting the first multiplication result will be described in each case.

(1) Operand presence floating point exceptions for multiply operations

FIG. 6 shows a flow diagram of a multiplication operation according to an embodiment of the present application. In this case, as shown in fig. 6, before the multiplication operation is performed, step S60 is performed, and the leading zero counter 21 counts the number of leading zeros of the operand in which the floating-point exception exists.

Assume that the multiplication operation includes two operands, respectively: operand a and operand B. The presence of a floating point exception in an operand of a multiply operation may refer to the presence of a floating point exception in either or both of the operands, for which the leading zero counter 21 counts the number of leading zeros of the operand. For example, if operand A has a floating point exception, leading zeros counter 21 may count the leading zeros of operand A to obtain LZC_AIf there is a floating point exception in operand B, leading zero counter 21 may count the leading zero number of operand B to obtain LZC_B。

In step S61, the FPU may expand the bit width of the operand of the multiplication operation to obtain an expanded operand. The FPU may perform bit width expansion on the operand a and the operand B respectively according to the above-described manner to obtain an operand a 'and an operand B', and the specific manner of bit width expansion may refer to the above description, and for an operand without floating point exception, an implementation manner of bit width expansion corresponding to a normalization number is used, and for an operand with floating point exception, an implementation manner of bit width expansion corresponding to a denormal number is used, which is not described again.

In step S62, the multiplication unit 221 performs a multiplication operation according to the expanded operands to obtain a first multiplication result, where the first multiplication result may include a first exponent result and a first mantissa result. The multiplication unit 221 performs a multiplication operation according to the operand a 'and the operand B' to obtain a first multiplication result, and a specific process of performing the multiplication operation may include: and calculating to obtain a first exponent result according to the value of the exponent field of the expanded operand, the offset value corresponding to the expanded operand, the leading zero number and the offset value corresponding to the input operand. The offset value corresponding to the input operand may refer to an offset value corresponding to a format of the input operand, that is, an offset value corresponding to a format of the operand without bit width expansion. And multiplying the Mantissa Mantissa A of the operand A 'and the Mantissa Mantissa B of the operand B' to obtain a first Mantissa result.

For example, the first exponential result ═ E_A–LZC_A+E_B–LZC_B+Bias_sourWherein, in the calculation process, E_AObtained by subtracting the corresponding offset value from ExpA, E_ASubtracting the corresponding Bias value from ExpB to obtain the Bias_sourAnd indicating the offset value corresponding to the format of the input operand.

In step S63, the first underflow correcting unit 222 determines whether the first exponent result is smaller than the minimum exponent.

The first underflow correction unit 222 may determine that the first multiplication result overflows downward if the first exponent result is less than the minimum exponent, that is, if the result of adding exponent bits of operands of the multiplication operation is less than 0. In case the first multiplication result overflows downward, step S64 may be performed, and the first underflow modification unit 222 calculates a first mantissa shift number and a second exponent result according to the minimum exponent and the first exponent result.

For example, in the case that the first multiplication result overflows downward, the first underflow correcting unit 222 may add 1 to a difference value of the minimum exponent and the first exponent result as a first mantissa shift number, and may calculate a second exponent result according to the first mantissa shift number and the first exponent result, where the second exponent result may be a sum of the first exponent result and the first mantissa shift number.

In one possible implementation, the first underflow modification unit 222 may calculate the first mantissa shift number according to the following equation (3):

S_underflow1＝MINExp-Exp₁+1； (3)

wherein S is_underflow1Representing the number of mantissa shifts when the first multiplication result overflows downward, MINExp representing the minimum exponent, Exp₁Representing the first exponential result.

In step S66, the first underflow modification unit 222 shifts the first mantissa result according to the first mantissa shift number and rounds the first mantissa result according to the rounding mode to obtain a second mantissa result.

The first mantissa result may be a denormal number that includes leading zeros, due to floating point exceptions in the operands of the multiply operation. The calculated first mantissa shift number is used to right shift the first mantissa result when the first multiplication result overflows downward. In this case, the first mantissa result may also be rounded according to a rounding mode during the right shift to obtain the second mantissa result.

In one possible implementation, before step S66, the method may further include: and determining the actual mantissa shift number according to the relation between the first mantissa shift number and the number of bits of the mantissa field. The number of bits of the mantissa field may refer to the number of bits of the mantissa field in the format of the floating point number after the bit width expansion, for example, the number of bits of the mantissa field in the EP floating point number is 64, DP is 52, and SP is 23.

Specifically, if the first mantissa shift count is less than the number of bits of the mantissa field, the actual mantissa shift count is the first mantissa shift count, and if the first mantissa shift count is greater than the number of bits of the mantissa field, the number of bits of the mantissa field is the actual mantissa shift count.

The number of bits to shift the first mantissa result to the right may not exceed the number of bits of the mantissa field, and therefore, after determining the actual mantissa shift number according to the above-described manner, step S66 may be performed in which the first underflow correcting unit 222 shifts the first mantissa result according to the actual mantissa shift number and rounds the first mantissa result according to the rounding mode to obtain a second mantissa result

Compared with a theoretical method, the method of the embodiment of the application reduces the number of shifts, namely, the implementation process of the operation method of the embodiment of the application is more friendly to operation time and circuit area.

The first underflow correcting unit 222 may determine that the first multiplication result does not overflow downwards if the first exponent result is not less than the minimum exponent, that is, if the result of adding exponent bits of operands of the multiplication operation is not less than 0, the first multiplication result does not overflow downwards. In case the first multiplication result does not overflow downwards, step S65 may be executed, and the first underflow correcting unit 222 calculates a second mantissa shift number according to the leading zero number of the first mantissa result and the leading zero number of the operand.

In one possible implementation, the first underflow modification unit 222 may calculate a first difference value between the leading zero number of the input operand and the leading zero number of the first mantissa result in a case that the first multiplication result does not overflow downwards.

If the first difference is greater than 0, the first underflow correction unit 222 may determine the first difference as a second mantissa shift number; if the first difference is equal to 0, the first underflow correcting unit 222 does not need to calculate the second mantissa shift number, or the second mantissa shift number is 0.

If the first difference is greater than 0, the first underflow correcting unit 222 may perform step S67, shift the first mantissa result according to the second mantissa shift number and the leading zero number of the input operand to obtain a second mantissa result, and calculate the second mantissa result according to the second mantissa shift number and the first exponent result.

Specifically, the first underflow correcting unit 222 may shift the first mantissa result to the left, and the number of bits shifted to the left may be the leading zero number of the input operand and the second mantissa shiftDifference in the number of bits. And adding the first exponent result to the second mantissa shift number to obtain a second exponent result. In another possible implementation, the second mantissa shift number may be based on ExpA + ExpB-LZC_A-LZC_BAnd (4) calculating.

And under the condition that the first multiplication result does not overflow downwards, the calculated second mantissa shift number is used for carrying out left shift on the first mantissa result. If the left carry of the second mantissa result in the process of left shift makes the most significant bit greater than 1, in this case, the process of left shift of the first mantissa result needs to be stopped to obtain the second mantissa result, and the second mantissa result is determined again according to the carry bit.

It should be noted that, since the number of bits of the first mantissa result obtained by calculation is greater than the number of bits of the mantissa bits of the operand, the first mantissa result may be rounded after the left shift to obtain a second mantissa result.

After calculating the second exponent result and the second mantissa result, the multiplier 22 may execute step S68, where the first underflow modification unit 222 converts the second mantissa result and the second mantissa result to obtain the second multiplication result in a floating point format.

(2) Operand non-floating point exception for multiply operation

FIG. 7 shows a flow diagram of a multiplication operation according to an embodiment of the present application. In this case, as shown in fig. 7, it is not necessary to calculate the number of leading zeros of the operand, and thus the delay can be reduced and the operation efficiency can be improved.

In step S71, the FPU may expand the bit width of the operand of the multiplication operation to obtain an expanded operand. The specific process may refer to the step S61 and the implementation manner of the normalized bit width expansion of the bit width expansion part, and is not described in detail again.

In step S72, the multiplication unit 221 may perform a multiplication operation according to the expanded operands to obtain the first multiplication result. The specific process can be seen from the description of step S62, and the leading zeros of the operands are all 0.

Since the operands of the floating-point operation are free of floating-point exceptions, the first exponent result of the computed first multiplication result must be greater than the minimum exponent and the first multiplication result will not overflow downward. If the first multiplication result does not overflow down, the first underflow correction unit 222 does not need to calculate the mantissa shift number because the first mantissa result of the first multiplication result must be greater than 1 and does not need to be normalized by a left shift operation in the absence of a floating point exception to the operands of the multiplication operation. The multiplier may perform step S73 to determine whether the first mantissa result is less than 2. If the first mantissa result is greater than 1 and less than 2, the multiplier may perform step S74 to obtain a second multiplication result in a floating point format directly according to the first exponent result and the first mantissa result.

However, the first mantissa result may be greater than or equal to 2, that is, a carry operation may be required, and in this case, a right shift operation may be required for normalizing the first multiplication result.

In step S75, the normalization unit of the multiplier may shift the first mantissa result according to the carry bit of the first mantissa result and round the first mantissa result according to the rounding mode to obtain a second mantissa result;

in step S76, the multiplier may further calculate a second exponent result according to the carry bit of the first mantissa result and the first exponent result.

Finally, step S77 may be executed to convert the second mantissa result and the second exponent result to obtain a second multiplication result in a floating point format.

According to the multiplication operation of the above embodiment, whether floating point abnormality exists in the operand of the floating point operation is detected, and the floating point operation process is flexibly selected for different input operands according to the detection result shunting processing, so that the operation efficiency can be improved.

Turning now to one implementation of the multiplier 22 of the present application, fig. 8 shows a block diagram of the multiplier 22 according to an embodiment of the present application. As shown in fig. 8, the multiplier 22 according to the embodiment of the present application may include an exponent expanding unit and a mantissa expanding unit, where the exponent expanding unit is configured to perform bit width expansion on an exponent field of an operand of a multiplication operation, and the mantissa expanding unit is configured to perform bit width expansion on a mantissa field of the operand of the multiplication operation.

After the bit width expansion is performed, a process of operation may be performed, and as shown in fig. 8, the Multiplier 22 according to the embodiment of the present application may include an Exponent Adder (exponentadder) and a Mantissa Multiplier (Mantissa Multiplier). The exponent adder is used for executing addition and subtraction operation of exponents of input operands, and the mantissa multiplier is used for executing multiplication operation of mantissas of the input operands.

In one possible implementation, the exponent adder and mantissa multiplier shown in fig. 8 may constitute the multiplication unit 221. In another possible implementation, the exponent extension unit, the exponent adder, the mantissa extension unit, and the mantissa multiplier shown in fig. 8 constitute the multiplication unit 221. The present application does not limit the specific partitioning manner of the units or modules.

The first multiplication result may be obtained after calculating exponents and mantissas of operands of the multiplication operation through an exponent adder and a mantissa multiplier, respectively, and may include a first exponent result and a first mantissa result.

In one possible implementation, as shown in fig. 8, the first underflow modification unit 222 may include a unit for exponent underflow prediction and mantissa shift number calculation, a Wallace-Tree Adder (Wallace-Tree-Adder), a normalization unit, a rounding control unit, and a plurality of multiplexers.

The unit for predicting exponent underflow and calculating mantissa shift numbers may predict whether to overflow downwards according to a first exponent result and a minimum exponent calculated by the exponent adder, calculate mantissa shift numbers (as shown in fig. 6) according to the predicted result, and send the calculated mantissa shift numbers (the first mantissa shift numbers, the second mantissa shift numbers, the actual mantissa shift numbers, and the like) to the mantissa normalizing unit.

The Wallace tree adder is used for rounding the first mantissa result, wherein the rounding process may include Round Up and Round Down, that is, rounding Up and rounding Down, and the result of rounding Up and rounding Down the first mantissa result is calculated to obtain rounded-Up mantissa and rounded-Down mantissa.

The mantissa normalization unit may perform normalization processing (shift left or shift right) on the rounded-up mantissa and the rounded-down mantissa according to the calculated mantissa shift number (first mantissa shift number, or second mantissa shift number), respectively, and a specific processing procedure may refer to step S66 or S67 in fig. 6, or to step S75 in fig. 7. If the rounded-up mantissa or the rounded-down mantissa is shifted to the right, the normalized mantissa may be rounded by selecting +1 or +0 according to the rounding mode. The normalized rounded-up mantissa and rounded-down mantissa may be obtained according to the above procedure, and then one of them is selected as the second mantissa result by the rounding control unit according to the rounding mode. The rounding mode may refer to a rounding mode employed by a software module running on the processor.

FIG. 9 shows a schematic diagram of an exponent adder and units for exponent underflow prediction and mantissa shift number calculation according to an embodiment of the present application. As shown in FIG. 9, the left two adders (Adder 1, Adder 2, hereinafter referred to as the first Adder and the second Adder) are used to perform subtraction operation on the operand and the leading zero number of the operand, for example, as described above, the multiplication operation includes an operand A and an operand B, the exponent field of the operand A has the value of ExpA, and the leading zero number of the mantissa bits can be LZC_AThe exponent field of operand B has the value of ExpB, and the leading zero number of mantissa bits can be LZC_BIn the embodiment of the present application, the leading zeros of the operand a and the operand B may be negated before being input to the first adder and the second adder. The first adder is used for calculating ExpA-LZC_A-Bias_AObtaining a first difference value, and calculating ExpB-LZC by using a second adder_B-Bias_BObtaining a second difference value, wherein, Bias_AAnd Bias_BRespectively, the offset value of operand a, the offset value of operand B. The two adders output the first difference and the second difference to a third Adder (Adder 3) connected thereto for adding the first difference and the second difference to each otherThe values are summed and added to the Bias_sourA first exponential result of the first multiplication result is obtained.

After the first exponent result is calculated, the unit for exponent underflow prediction and mantissa shift calculation may determine whether the first multiplication result overflows downwards according to the first exponent result and the minimum exponent, and may further calculate the mantissa shift according to the first exponent result, the minimum exponent and the number of leading zeros.

As shown in fig. 9, in one possible implementation, a comparator (not shown in fig. 9) may be disposed in the unit for exponent underflow prediction and mantissa shift number calculation, and the comparator may compare the calculated first exponent result Exp with the minimum exponent.

If the first exponent result is greater than the minimum exponent, then the first multiplication result does not overflow downward, at which time the mantissa shift number may be set to 0 as shown in FIG. 9.

If the first exponent result is less than the minimum exponent (MinExp), as shown in FIG. 9, a first mantissa shift number MinExp + -Exp +1 is calculated, and the relationship between the first mantissa shift number and the number of bits of the mantissa field is determined to determine the actual mantissa shift number. As shown in fig. 9, an example of the number of bits of the mantissa field may be 64. Specifically, if the first mantissa shift count is less than the number of bits of the mantissa field, the actual mantissa shift count is the first mantissa shift count, and if the first mantissa shift count is greater than the number of bits of the mantissa field, the number of bits of the mantissa field is the actual mantissa shift count. According to the example shown in fig. 9, it is possible to predict whether the operation result overflows downward for different input operands, and determine the calculation manner of calculating the mantissa shift number according to the prediction result, resulting in the mantissa shift number to shift the first mantissa result. Also, as shown in FIG. 8, if overflow occurs downward, the multiplexer connected thereafter may also calculate a second exponent result based on the prediction result, the first exponent result, and the minimum exponent. It should be noted that the example shown in fig. 9 is only one example of an exponent adder and a unit for exponent underflow prediction and mantissa shift number calculation, and does not limit the present application in any way.

Application example (multiplication)

The following illustrates the process of multiplication according to an actual application example.

Example 1 (operands A and B are normalized numbers)

LZC_A＝0，LZC_BWhen the value is 0, the LZC is not needed to be processed, and if the value is detected to be normalized, the LZC is directly set_A＝0，LZC_B＝0。

Assume operand A is 1.25 and operand B is 2.345, assuming the operands are all single precision floating point numbers. The gradual evolution of each operand during the operation is illustrated in tabular form below.

Operand A0 x3FA0000 (i.e. decimal 1.25)

Operand B:0x4016147B (i.e., decimal 2.345)

In the implementation process, not all channels need to be extended to 64-bit, that is, the bit width of the input operands of some channels can be expanded.

Note that in this example, the LZCs of the operands of the inputs are all 0.

First exponential result ExpA-LZC_A+ExpB–LZC_B+Bias sp

＝(17’hFFFF-17’hFFFF)–0+(17’h10000-17’hFFFF)–0+8’7F

＝8’h1+8’7F＝8’h80

Therefore, the calculated 8' h80 is greater than the minimum exponent, and therefore, the calculated multiplication result does not overflow downward.

First mantissa result ═ ManA × ManB

＝64’hA000000000000000*64’h96143B0000000000

＝128’h5dcccd20000000000000000000000000

No normalization is required at this time, because the result is 1 x, and the valid result in the first mantissa result is truncated.

First mantissa result:

the first multiplication result:

example 2 (operand A is a normalized number and operand B is an unnormalized number)

As shown in fig. 9, the first exponent result Exp and the first mantissa result are calculated.

If the first exponent result is less than the minimum exponent, indicating a downward overflow, the difference between the first exponent result and the minimum exponent is calculated to determine the actual mantissa shift counter (Underflow shift counter), which is performed as follows:

Underflow shift counter＝MinExp–Exp＝MinExp+～Exp+1；

If(Underflow shift counter>64)

Underflow shift counter＝64；

Else Underflow＝MinExp+～Exp+1。

non-normalized example

Operand A0 x3F7FFFFF

Operand B0 x00000001

In decimal system, the result of exponentiation in the theoretical operation result is ExpA-LZC_A+(ExpB–LZC_B)+Bias sp＝(-1)-0+(-127-22)+127＝-23<0 judgment of downward overflow

If in hexadecimal, according to an embodiment of the present application, the first exponential result is calculated by:

＝(17’hFFFF-17’hFFFF–0)+((0–8’h7F+17’hFFFF–8’h12)–17’hFFFF)+8’h7F

＝(17’hFFFF-17’hFFFF)+(17’hFF6A-17’hFFFF)+17’hFFFF

overflow was judged downward by-8 'h 23< 8' h0

SP Exponent range [ -127+127,128+127]

SP Min(32’h0000_0001)2^(-126-23)＝2^(-149)-149+Bias SP＝-149+127＝-22

First mantissa shift number: underflow Shift Counter (-22) - (-23) ═ 1

Underflow prediction and mantissa shift:

mantissa intermediate result 128' h000000ffffff00000000000000000000

Shifting the mantissa intermediate result by a first mantissa shift number (1-bit) to the right results in a mantissa result

128’h0000007f ffff80000000000000000000

Second index result-8 ' h23+ 8' h 1-8 ' h22< 0; set to 8' h0 in floating point number format.

Select a result (second mantissa result) according to a rounding mode:

if rounding up to 23' h 000001;

if rounding down to 23' h 000000;

index result 0x 0.

The final second multiplication result is 32 'h 00000001 (rounding mode Round Up or Round Near) or 32' h00000000 (rounding mode Round Down or Round).

Compared with the theoretical method, the method of the embodiment of the present application reduces the number of shifts (as described above, the calculation method according to the embodiment of the present application only needs to shift the mantissa by 1 bit, but needs to shift by 23 bits in the related art), that is, the implementation process of the operation method according to the embodiment of the present application is more friendly to the operation time and the circuit area. And the calculation efficiency is improved by selecting according to two cases (the case that the mantissa is added with 1 and the case that the mantissa is not added with 1) of the calculated rounding and finally according to the actual rounding mode.

Divider and division operation

The divider 23 is used for performing a division operation, and in one possible implementation, as shown in fig. 2 or fig. 3, the divider 23 may include a normalization unit 231, a division unit 232, and a second underflow correction unit 233; the normalization unit 231 is configured to, when the detection module 20 detects that a floating point abnormality exists in an operand of a division operation, perform normalization processing (normalization processing) on the operand according to a leading zero number of the operand; the division unit 232 is configured to perform a division operation according to the operand or the normalized operand to obtain a first division result; the second underflow correcting unit 233 is configured to correct the first division result according to a minimum exponent when the first division result is detected to overflow downwards.

In one possible implementation, the process of expanding the bit width of the operand of the division operation may be located after the normalization and before the division operation is performed. That is, if there is a floating point exception in the operand of the division operation, the leading zero number of the operand in which the floating point exception exists may be calculated by the leading zero counter 21, and then the operand may be normalized by the normalization unit 231 according to the leading zero number. And then, expanding the bit width of the normalized operand, and executing a division operation process according to the operand after the bit width is expanded.

For the division operation, if the detection module 20 detects that the operand of the division operation is not abnormal with a floating point, the normalization process may be skipped, that is, the normalization unit 231 does not need to normalize the operand, the division unit 232 directly performs the division operation according to the operand to obtain a first division result (or may perform bit width expansion on the operand before performing the division operation), and then the second underflow correction unit 233 is configured to correct the first division result according to the minimum exponent when detecting that the first division result overflows downwards.

In one possible implementation, the first division result may include a third exponent result and a third mantissa result. Suppose that the two operands after bit width expansion are respectively: operand A and operand B, assuming operand A is the dividend and operand B is the divisor. The specific process of performing the division operation may include: and calculating a third exponent result according to the value of the exponent field of the expanded operand, the offset value corresponding to the expanded operand and the offset value corresponding to the input operand. For example, the third exponential result ═ E_A-E_B+Bias_sourWherein, in the calculation process, E_ASubtracting the corresponding offset value from ExpA, which is the value of the exponent field of operand A, E_BSubtracting the corresponding offset value from ExpB, which is the value of the exponent field of operand B, Bias_sourAnd indicating the offset value corresponding to the format of the input operand.

In a possible implementation manner, when the extended two operands have the same offset value, the third exponent result may be calculated according to the value of the exponent field of the extended operand and the offset value corresponding to the input operand, for example, the difference value is calculated for the values of the exponent fields of the operand a and the operand B, and the offset value corresponding to the input operand is added to obtain the third exponent result.

The specific process of performing the division operation may further include: and carrying out quotient calculation on the mantissa belonging to the operation A and the mantissa of the operand B to obtain a third mantissa result.

The second underflow correcting unit 233 is configured to determine whether the first division result overflows downward according to the third exponent result and the minimum exponent, where if the third exponent result is smaller than the minimum exponent, the first division result overflows downward, and if the third exponent result is not smaller than the minimum exponent, the first division result does not overflow downward.

In one possible implementation, in case that the first division result overflows downward, the second underflow correcting unit 233 may calculate a fourth mantissa shift number according to the minimum exponent, the third exponent result, and the leading zero number of the third mantissa result, where the fourth mantissa shift number is a number of bits that the third mantissa result is shifted to the right.

In the case that the first division result does not overflow downwards, the second underflow correcting unit 233 may first determine whether normalization of the third mantissa result is required according to the leading zero number of the third mantissa result, and since the normalization process is performed on the operand of the division operation before the calculation, the normalized operand is 1.

If the third mantissa result obtained by calculation is not less than 1, the mantissa shift number can be directly determined to be 0, and the divider can be converted according to the third exponent result and the third mantissa result to obtain a second division result in a floating point format.

If the calculated third mantissa result is less than 1, then the third mantissa result only includes a leading zero, that is, the fourth mantissa result is obtained by shifting the third mantissa result by one bit to the left, and the fourth exponent result is obtained by subtracting 1 from the third exponent result. And the divider converts the fourth exponent result and the fourth mantissa result to obtain a second division result in a floating point format.

In one possible implementation, the number of mantissa shifts required for the third mantissa result is also related to the algorithm used for the division, and the number of mantissa shifts depends on the number of 0's in the quotient calculated in the first round of the algorithm used. The actual algorithm performs bit-filling operation on the operand before calculation, and ensures that the result of the first round calculates a number greater than or equal to 1 to truncate the calculation of subsequent 0, and at this time, the number of mantissa shifts can be determined according to the quotient of several 0 calculated in the first round.

For example, using the algorithm of SRT-r, the first round of calculated quotient has Log₂Bit (r), fixed, e.g. using SRT16, after algorithm fixing, each roundThe calculated quotient is 4-bit.

The number of 0 in the quotient is 4- (logarithm of the number of digits of the quotient calculated in the first round), for example, the possible value of the quotient that can be calculated in the first round is [2, 7]]The number of digits of a quotient having 1 is [ log ]₂2,log₂7]。

The following describes the process of a division operation and an example of a divider

(1) Floating point exceptions to operands of division operations

FIG. 10 shows a flow diagram of a division operation according to an embodiment of the present application. As shown in fig. 10, in this case, before the division operation is performed, step S100 is performed, and the leading zero counter 21 counts the number of leading zeros of the operand in which the floating-point exception exists.

Suppose a division operation includes two operands, respectively: operand A and operand B, assuming operand A is the dividend and operand B is the divisor. The presence of a floating point exception in an operand of a division operation may refer to the presence of a floating point exception in either or both of the operands, for which the leading zero counter 21 counts the number of leading zeros. For example, if operand A has a floating point exception, leading zeros counter 21 may count the leading zeros to obtain LZC_AIf the operand B has floating point exception, the leading zero counter 21 can calculate the leading zero number to obtain LZC_B。

In step S101, the normalization unit 231 may perform normalization processing (normalization processing) on the operand according to the number of leading zeros.

In one possible implementation, the normalization unit 231 may shift the mantissa of the operand left by the same number of bits as the leading zeros according to the leading zeros number, and subtract the same number as the leading zeros number from the exponent of the operand (where the exponent does not refer to a binary exponent bit, but refers to the exponent of the operand in floating-point format).

In another possible implementation, the normalization unit 231 may also determine whether the most significant bit of the mantissa of the operand is 1, and if not, shift the operand into the mantissa by one bit and subtract 1 from the exponent of the operand number, and repeat the above process until the most significant bit of the mantissa of the operand is 1.

For example, assuming operand A is a single precision floating point number, operand A is 0.001 x 2 x (-126), the mantissa of operand A may be left-shifted by three bits to obtain a mantissa of 1.000, and subtracting 3 from the exponent of operand A may obtain-129, so that the normalized operand A may be represented as 1.000 x 2 x (-129).

In step S102, the FPU may expand the bit width of the normalized operand to obtain an expanded operand.

The process of expanding bit width specifically may refer to the above description, and taking the above operand a as an example, the process of expanding single-precision floating point number into expanded double-precision floating point number is as follows:

the indexes after expansion are as follows: -129+(2¹⁶-1)＝2¹⁶-2⁷-2；

The expanded mantissa is expanded to 64 bits by adding 0 after the original mantissa.

Therefore, the operand a after bit width expansion can be expressed as follows in the format of expanding double-precision floating point number: 0(17'hEE6D) (64' h 000000000000).

In step S103, the division unit 232 executes a division operation according to the expanded operand to obtain a first division result, where the first division result includes a third exponent result and a third mantissa result. The specific process of performing the division operation may include: in a possible implementation manner, when the extended offset values corresponding to the two operands are the same, the third exponent result may be calculated according to the extended value of the operand and the input offset value corresponding to the operand, for example, the difference between the values of the exponent fields of the operand a and the operand B is calculated, and the offset value corresponding to the input operand is added to obtain the third exponent result. The specific process of performing the division operation may further include: and carrying out quotient calculation on the mantissa belonging to the operation A and the mantissa of the operand B to obtain a third mantissa result.

In step S104, the second underflow correcting unit 233 determines whether the third exponent result is smaller than the minimum exponent.

The first underflow correction unit 233 may determine that the first division result overflows downward if the third exponent result is less than the minimum exponent, that is, if the result of adding the exponent bits of the operands of the division operation is less than 0, the first division result overflows downward. In the case where the first division result overflows downward, the second underflow correcting unit 233 calculates a third mantissa shift number according to the minimum exponent and the third exponent result, and calculates a fourth exponent result according to the third exponent result and the third mantissa shift number at step S105.

For example, the second underflow correcting unit 233 is configured to, in case that the first division result overflows downwards, add 1 to a difference between the minimum exponent and the third exponent result to obtain a third mantissa shift number, and may calculate a fourth exponent result according to the third mantissa shift number and the third exponent result, where the fourth exponent result may be a sum of the third exponent result and the third mantissa shift number.

In one possible implementation, the second underflow correcting unit 233 may calculate the third mantissa shift number according to the following equation (6):

S_underflow4＝MINExp-Exp₃+1； (6)

wherein S is_underflow4Representing the number of mantissa shifts when the first division result overflows downward, MINExp representing the minimum exponent, Exp₃Representing the third exponential result.

After that, step S106 is executed, the second underflow correcting unit 233 shifts the third mantissa result according to the third mantissa shift number, and rounds the third mantissa result according to the rounding mode to obtain a fourth mantissa result.

In the event that the first division result overflows downward, the calculated third mantissa shift number is used to right shift the third mantissa result so that the third exponent result falls within the expression range of exponent bits. In this case, the third mantissa result may also be rounded according to a rounding mode during the right shift to obtain a fourth mantissa result.

In step S109, the divider 23 converts the fourth mantissa result and the fourth exponent result to obtain a second division result in a floating point format.

The second underflow correcting unit 233 may determine that the first division result does not overflow downwards if the third exponent result is not less than the minimum exponent, that is, if the result of adding the exponent bits of the operands of the division operation is not less than 0, the first division result does not overflow downwards. If the first division result does not overflow downwards, step S106 is executed, and the second underflow correcting unit 233 determines whether normalization processing is required for the third mantissa result according to the leading zero number of the third mantissa result (determines whether the third mantissa result is smaller than 1).

If the calculated third mantissa result is not less than 1, it may be directly determined that the mantissa shift number is 0, and the divider may perform step S107 to directly convert the third exponent result and the third mantissa result to obtain a second division result in a floating point format.

If the calculated third mantissa result is smaller than 1, the third mantissa result only includes a leading zero, that is, only step S108 needs to be executed, the third mantissa result is shifted to the left by one bit to obtain a fourth mantissa result, and the third exponent result is subtracted by 1 to obtain a fourth exponent result; and step S109, converting the divider according to the fourth exponent result and the fourth mantissa result to obtain a second division result in a floating point format.

(2) Absence of floating point exceptions in operands of division operations

FIG. 11 shows a flow diagram of a division operation according to an embodiment of the present application. As shown in fig. 11, when there is no floating point exception in the operand, it is not necessary to calculate the leading zero number of the operand, and it is also not necessary to normalize the operand according to the leading zero number.

Before executing the division operation, step S110 may be executed first, and the FPU may perform bit width expansion on the operand of the division operation to obtain an expanded operand. The specific process may refer to the implementation of the bit width extension part above.

In step S111, the division unit 232 performs a division operation according to the expanded operand to obtain a first division result, where the first division result includes a third exponent result and a third mantissa result.

In step S112, the second underflow correcting unit 233 determines whether the third exponent result is less than the minimum exponent.

The second underflow correcting unit 233 may determine that the first division result overflows downward if the third exponent result is less than the minimum exponent. In the case where the first division result overflows downward, the second underflow correcting unit 233 calculates a third mantissa shift number according to the minimum exponent and the third exponent result, and calculates a fourth exponent result according to the third exponent result and the third mantissa shift number, in step S113.

In step S115, the second underflow correcting unit 233 shifts the third mantissa result according to the third mantissa shift number, and rounds the third mantissa result according to the rounding mode to obtain a fourth mantissa result.

In step S118, the second underflow correcting unit 233 converts the fourth mantissa result and the fourth exponent result to obtain a second division result in a floating point format.

The second underflow correcting unit 233 may determine that the first division result does not overflow downwards if the third exponent result is not less than the minimum exponent. In the case that the first division result does not overflow downwards, step S114 is executed, and the second underflow correcting unit 233 determines whether normalization of the third mantissa result is required according to the leading zero number of the third mantissa result (determines whether the third mantissa result is smaller than 1).

If the calculated third mantissa result is not less than 1, it may be directly determined that the mantissa shift number is 0, and the divider may perform step S116 to directly convert the third exponent result and the third mantissa result to obtain a second division result in a floating point format.

If the calculated third mantissa result is smaller than 1, the third mantissa result only includes a leading zero, that is, only step S117 needs to be executed to shift the third mantissa result by one bit to the left to obtain a fourth mantissa result, and subtract 1 from the third exponent result to obtain a fourth exponent result; in step S118, the divider converts the fourth exponent result and the fourth mantissa result to obtain a second division result in a floating point format.

The processes of steps S112 to S118 are the same as the processes of steps S104 to S109 in fig. 10, and the specific processes may refer to the above description and are not repeated.

Turning now to one implementation of the divider 23, fig. 12 shows a block diagram of the divider 23 according to an embodiment of the present application. As shown in fig. 12, compared to the multiplier 22, the divider 23 includes an exponent adder and a mantissa shift unit for normalizing the operand, wherein the mantissa shift unit is used to shift the mantissa of the operand with floating point exception left until the most significant bit is 1, and the exponent adder for normalizing the operand is used to subtract the exponent of the operand with floating point exception from the number of bits of the mantissa shift.

The exponent expanding unit and the mantissa expanding unit in the divider 23 have the same functions as those of the exponent expanding unit and the mantissa expanding unit in the multiplier 22, and are not described again.

Through the shifting operation and the exponent subtraction operation of the mantissa of the operand and the bit width expansion of the exponent and the mantissa of the operand, the operation with floating point exception can be converted into a normalized floating point number, and the normalization processing of the operand is realized.

The exponent adder and the mantissa shift unit, the exponent extension unit and the mantissa extension unit for normalizing operands in the divider 23 together constitute dmfx (denormal Media Fix up), i.e., the normalization unit 231 described above.

The mantissa divider is used for performing division operation on mantissas of two operands of the division operation to obtain mantissas of a first division result.

The unit for exponential underflow prediction and mantissa shift number calculation may execute the partial contents in steps S104, S105 shown in fig. 10, and the partial contents in steps S112, S113 in fig. 11.

The mantissa normalization unit in the divider 23 has the same function as the mantissa normalization unit in the multiplier 22, except that no Wallace tree adder is provided in the divider 23, and the fourth mantissa result obtained by normalizing the mantissa in the first division result is directly rounded according to rounding control without selecting from the rounding-up result and the rounding-down result. Of course, in the same manner as in the multiplier 22, the divider 23 of the embodiment of the present application may also calculate the round-up result and the round-down result according to the third bit number result via the wallace tree adder, normalize both the round-up result and the round-down result, and select one of the round-up result and the round-down result normalized therefrom as the fourth mantissa result according to the rounding control.

A multiplexer connected to the lower side of the unit for exponent underflow prediction and mantissa shift calculation is used for calculating a fourth exponent result according to the third exponent result, the minimum exponent and the third mantissa shift.

Fig. 13 is a diagram illustrating a specific structure of a unit for exponent underflow prediction and mantissa shift count calculation and an exponent adder according to an embodiment of the present application. As shown in fig. 13, since the input operand has been normalized according to the leading zero number of the input operand, it is not necessary to calculate the exponent result according to the leading zero number when performing division operation. Therefore, the example in fig. 13 can be provided with two less adders than fig. 9, and the other structure is the same as fig. 9.

Application example (division operation)

The following illustrates the process of division operation according to an actual application example.

Example 3 (operands A and B are normalized numbers)

Operand A0 x3E80000 (i.e., decimal 0.25)

Operand B0 x3F00000 (i.e., decimal 0.5)

Exponential subtraction:

third exponential result (ExpA-LZC)_A)–(ExpB-LZC_B)+Bias SP

＝(17’hFFFD–17’hFFFF-0)–(17’FFFE-17’hFFFF-0)+8’h7F

8'h 7E > 8' h 0. Therefore, the third exponent result does not overflow downward.

Third mantissa result:

Mantissa A/Mantissa B＝

64’h8000000000000000/64’h8000000000000000

＝64’h8000000000000000

mantissa shift number of 0

Final mantissa result 24' h800000

The second division result:

Sign[31]	Exponent[30:23]	Imp.	Mantissa[22:0]
				0	01111110	1	00000000000000000000000

second division result is 0x3f000000 (i.e. decimal 0.5)

Example 4 (operand A is an denormal number and operand B is a normalized number)

Operand A0 x003 ffffff

Operand B:0x40800000

In decimal, the third exponential result is ═ (ExpA-LZC)_A)–(ExpB-LZC_B)+Bias SP

＝(-127-1)-(2-0)+127＝-3<0。

Therefore, the third exponent result does not overflow downward.

The same result can also be obtained in hexadecimal:

third index results (17' hff 80-17 ' hfffff-1) - (17' h 10001-17 ' hfffff-0) +17 ' hfffff

＝(17’hff7f-17’hffff)–(17’h10001–17’hffff-0)+17’hffff

＝17’hff7d

Third mantissa result:

Mantissa A/Mantissa B＝64’hfffffc0000000000/64’h8000000000000000

＝64’hfffffc0000000000

mantissa shift number of 1- (-3) ═ 4

Intermediate results of the index (17 'hff 7d +4) -17' hfffff + 8'h7 f-8' h1

Shifting the third mantissa result by mantissa shift number (4-bit) to the right to obtain mantissa result of 64' h0fffffc000000000

Imp	Mantissa	Round bit
				0	00011111111111111111111	11000000

At this time, Imp is 0, which corresponds to the mantissa digit being 0.

IEEE 754 specifies that the exponent bits of the denormal number are all 0's and that the exponent needs to be adjusted to get a fourth exponent result of 8' h 0.

After the exponent bits are adjusted, the mantissa bits are shifted and rounded to obtain a fourth mantissa result:

rounded-up mantissa results in: mantissa round up result 23' h 001000000000000000000000000

Rounded-down mantissa results in: mantissa round down result 23' h 00011111111111111111111111111111111111111

Thus, the Round up mantissa result is 0x00100000 and the Round down mantissa result is 0x000 fffffff.

One of the mantissa results may be selected as a fourth mantissa result according to the rounding mode, and the second division result may be converted according to the fourth exponent result 8' h0 and the fourth mantissa result, so as to obtain a floating point format second division result.

According to the floating point exception handling method and device in the above embodiments of the present application, the floating point exception handling for the operand is repaired inside the FPU, so that the process of repeatedly performing loop repair can be avoided, complex interaction among multiple modules is not required, and the operation performance can be improved. And different processing flows and modes are set according to whether the operand has floating point exception, so that the processing flexibility can be improved, and the operation efficiency is improved.

The processing system of the embodiment of the present application may include a Floating Point Unit (FPU) (float Point unit), where the FPU is configured to perform floating Point operations, and the FPU may include the floating Point exception handling apparatus of the embodiment of the present application.

FIG. 14 shows a schematic diagram of a processing system 200 according to an embodiment of the present application. The processing system 200 may include a processor 201 and a memory 202 connected to the processor 201, and the FPU may be disposed in the processor 201. Various other components of the processing system 200 have been omitted from the example shown in fig. 14 for clarity. For the processor 201 and the memory 202 in the processing system 200, the embodiment of the present application does not limit the type of the processor 201 and the type of the memory 202, for example, the processor 201 may be a general-purpose processor such as a CPU, a GPU, and the like, and may also be a special-purpose processor formed by combining one or more of a DSP (Digital Signal processing) chip and a Field Programmable Gate Array (FPGA) chip. The memory 202 is used to store data, and the memory 202 may be implemented by any type of volatile or non-volatile memory device or combination thereof, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic or optical disk, and so forth.

The present disclosure may be systems, methods, and/or computer program products. The computer program product may include a computer-readable storage medium having computer-readable program instructions embodied thereon for causing a processor to implement various aspects of the present disclosure.

The computer readable storage medium may be a tangible device that can hold and store the instructions for use by the instruction execution device. The computer readable storage medium may be, for example, but not limited to, an electronic memory device, a magnetic memory device, an optical memory device, an electromagnetic memory device, a semiconductor memory device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a Static Random Access Memory (SRAM), a portable compact disc read-only memory (CD-ROM), a Digital Versatile Disc (DVD), a memory stick, a floppy disk, a mechanical coding device, such as punch cards or in-groove projection structures having instructions stored thereon, and any suitable combination of the foregoing. Computer-readable storage media as used herein is not to be construed as transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., optical pulses through a fiber optic cable), or electrical signals transmitted through electrical wires.

The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to a respective computing/processing device, or to an external computer or external storage device via a network, such as the internet, a local area network, a wide area network, and/or a wireless network. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. The network adapter card or network interface in each computing/processing device receives computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium in the respective computing/processing device.

The computer program instructions for carrying out operations of the present disclosure may be assembler instructions, Instruction Set Architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider). In some embodiments, the electronic circuitry that can execute the computer-readable program instructions implements aspects of the present disclosure by utilizing the state information of the computer-readable program instructions to personalize the electronic circuitry, such as a programmable logic circuit, a Field Programmable Gate Array (FPGA), or a Programmable Logic Array (PLA).

Various aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.

These computer-readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a computer, programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer-readable medium storing the instructions comprises an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.

The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus or other devices implement the functions/acts specified in the flowchart and/or block diagram block or blocks.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Having described embodiments of the present disclosure, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein were chosen in order to best explain the principles of the embodiments, the practical application, or technical improvements to the techniques in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A floating-point exception handling method for floating-point operations, wherein the method is applied to a floating-point arithmetic unit FPU, and the method comprises:

Detecting the operation type of the floating-point operation and whether there is a floating-point exception in the operand of the floating-point operation;

If it is detected that the operand has a floating-point exception, determine the number of leading zeros of the operand with the floating-point exception, and use an operator corresponding to the operation type of the floating-point operation to perform a floating-point operation on the operand to obtain an operation. In the process of the result, modify the operand according to the number of leading zeros;

If it is detected that the operand does not have a floating-point exception, directly using an operator corresponding to the operation type of the floating-point operation to perform a floating-point operation on the operand to obtain an operation result;

If the operation result underflows, the operation result is corrected.

2. The method according to claim 1, wherein the floating point operation is a multiplication operation, and the operation result is a first multiplication result, and the first multiplication result comprises a first exponent result and a first mantissa result;

In the process of performing a floating-point operation on the operand using an operator corresponding to the operation type of the floating-point operation to obtain an operation result, modifying the operand according to the number of leading zeros includes:

The first exponent result is obtained by calculating the multiplier according to the exponent of the multiplication operand and the number of leading zeros, and the first mantissa result is obtained by multiplying the mantissas of the multiplication operand.

3. The method according to claim 2, wherein if the operation result underflows, revising the operation result, comprising:

Determine whether the first multiplication result underflows according to the magnitude relationship between the first exponent result and the minimum exponent;

If the first multiplication result underflows, calculating the first mantissa shift number and the second exponent result according to the minimum exponent and the first exponent result;

Shift the first mantissa result according to the first mantissa shift number to obtain the second mantissa result;

The second multiplication result in floating point format is obtained by converting the second mantissa result and the second exponent result.

4. The method according to claim 3, wherein calculating the first mantissa shift number and the second exponent result according to the minimum exponent and the first exponent result, comprising:

Calculate the first mantissa shift number according to the minimum exponent and the first exponent result;

A second exponent result is calculated based on the first exponent result and the first mantissa shift number.

5. The method according to claim 3, wherein if the operation result underflows, revising the operation result, further comprising:

If the first multiplication result does not underflow, calculate the second mantissa shift number according to the number of leading zeros of the first mantissa result and the number of leading zeros of the operand;

Shift the first mantissa result according to the second mantissa shift number and the number of leading zeros of the input operand to obtain the second mantissa result, and calculate the second mantissa result according to the second mantissa shift number and the first exponent result to obtain the second exponent result ;

6. The method according to claim 1, wherein the floating-point operation is a division operation, and the operation result is a first division result,

normalize the operand according to the number of leading zeros;

The first division result is obtained by dividing the normalized operand by a divider.

7. The method according to claim 6, wherein the first division result comprises a third exponent result and a third mantissa result;

If the operation result underflows, modify the operation result, including:

Determine whether the first division result underflows according to the magnitude relationship between the third exponent result and the smallest exponent;

In the case of underflow of the first division result, calculating a third mantissa shift number according to the minimum exponent and the third exponent result, and calculating a fourth exponent result according to the third exponent result and the third mantissa shift number ;

Shift the third mantissa result according to the third mantissa shift number, and round the third mantissa result according to the rounding mode to obtain the fourth mantissa result;

Convert the result of the fourth mantissa and the fourth exponent to obtain the second division result in floating point format.

8. The method according to claim 7, wherein if the operation result underflows, revising the operation result, further comprising:

In the case that the first division result does not underflow, judge whether the third mantissa result needs to be normalized according to the number of leading zeros of the third mantissa result;

If the third mantissa result does not need to be normalized, then directly convert the third exponent result and the third mantissa result to obtain the second division result in floating-point format;

If the third mantissa result needs to be normalized, shift the third mantissa result one place to the left to obtain the fourth mantissa result, and subtract 1 from the third exponent result to obtain the fourth exponent result. The four-exponential result is converted to obtain the second division result in floating-point format.

9. The method according to any one of claims 1-8, wherein the method further comprises:

Before using the operator corresponding to the operation type of the floating-point operation to perform the floating-point operation on the operand, expand the bit width of the operand.

10. A floating-point exception processing device, comprising: a detection module, a leading zero counter, a multiplier and a divider,

Among them, the detection module is connected to the leading zero counter, and the leading zero counter is respectively connected to the multiplier and the divider;

When the detection module detects that the floating-point operation is a multiplication operation or a division operation, and the operand of the floating-point operation is abnormal, the leading zero counter is used to calculate the number of leading zeros of the operand that has the floating-point abnormality, and the The multiplier and the divider are used to modify the operand according to the number of leading zeros in the process of performing the floating-point operation to obtain the operation result;

When the detection module detects that the floating-point operation is a multiplication operation or a division operation, and the operand of the floating-point operation is not abnormal, the multiplier and the divider are used to directly perform the floating-point operation on the operand to obtain the operation result;

If the operation result underflows, the multiplier and the divider are further used for revising the operation result.

11. The device according to claim 10, wherein the floating-point operation is a multiplication operation, the operation result is a first multiplication result, and the first multiplication result comprises a first exponent result and a first mantissa result;

The multiplier includes a multiplication unit, and the multiplication unit is configured to calculate and obtain the first exponent result according to the exponent of the operand and the number of leading zeros, and multiply the mantissas of the operands of the multiplication operation to obtain the first mantissa result. .

12. The apparatus of claim 11, wherein

When the detection module detects that the operand of the floating-point operation has a floating-point exception, the multiplying unit obtains the number of leading zeros of the operand from the leading zero counter;

When the detection module detects that there is no floating-point exception in the operand of the floating-point operation, the multiplication unit sets the number of leading zeros to 0.

13. The apparatus according to claim 11, wherein the multiplier further comprises a first underflow correction unit;

The first underflow correction unit is configured to correct the first multiplication result when it is determined that the first multiplication result underflows according to the first exponent result.

14. The apparatus of claim 13, wherein

The first underflow correction unit is configured to judge whether the first multiplication result underflows according to the magnitude relationship between the first exponent result and the minimum exponent;

If the first multiplication result underflows, the first underflow correction unit calculates a first mantissa shift number and a second exponent result according to the minimum exponent and the first exponent result, and shifts according to the first mantissa The number shifts the first mantissa result, and rounds the first mantissa result according to the rounding mode to obtain the second mantissa result.

15. The apparatus according to claim 14, wherein the first underflow correction unit is configured to calculate the first mantissa according to the minimum exponent and the first exponent result if the first multiplication result underflows A shift number, and a second exponent result is calculated based on the first exponent result and the first mantissa shift number.

16. The apparatus according to claim 14, wherein the first underflow correction unit is further configured to, if the first multiplication result does not underflow, according to the number of leading zeros of the first mantissa result and all The number of leading zeros of the above operands calculates the second mantissa shift number;

Shift the first mantissa result according to the second mantissa shift number and the number of leading zeros of the input operand to obtain the second mantissa result, and calculate the second mantissa result according to the second mantissa shift number and the first exponent result to obtain the second exponent result .

17. The apparatus according to claim 14 or 16, wherein the multiplier further comprises a first format conversion unit,

The first format conversion unit is configured to convert the second multiplication result in floating point format according to the second mantissa result and the second exponent result.

18. The apparatus according to claim 10, wherein the floating-point operation is a division operation, and the operation result is a first division result,

The divider includes a normalization unit, a division unit and a second underflow correction unit;

Wherein, the normalization unit is configured to normalize the abnormal operand according to the number of leading zeros of the operand when the detection module detects that the operand of the division operation is abnormal;

The division unit is used for performing division operation according to the normalized operand to obtain the first division result;

The second underflow correction unit is configured to correct the first division result when the first division result underflow is detected.

19. The apparatus of claim 18, wherein the first division result comprises a third exponent result and a third mantissa result;

The second underflow correction unit is configured to judge whether the first division result underflows according to the magnitude relationship between the third exponent result and the minimum exponent;

The third mantissa result is shifted according to the third mantissa shift number, and the fourth mantissa result is obtained by rounding the third mantissa result according to the rounding mode.

20. The apparatus according to claim 19, wherein the second underflow correction unit is further configured to judge according to the number of leading zeros of the third mantissa result when the first division result does not underflow Whether the third mantissa result needs to be normalized;

If the third mantissa result needs to be normalized, shift the third mantissa result to the left by one place to obtain the fourth mantissa result, and subtract 1 from the third exponent result to obtain the fourth exponent result.

21. The apparatus according to claim 18, wherein the division unit is further configured to directly perform division on the operand of the division operation when the detection module detects that the operand of the division operation does not have a floating-point exception The operation yields the first division result.

22. The device according to claim 19 or 20, wherein the divider further comprises a second format conversion unit,

The second format conversion unit is used to convert the second division result in floating point format according to the fourth mantissa result and the fourth exponent result;

Or, if the second underflow correction unit judges that the third mantissa result does not need to be normalized, then the second format conversion unit is used to directly convert the third exponent result and the third mantissa result to obtain the floating-point format. The result of the second division.

23. The device according to claim 10, wherein the multiplier and the divider both comprise a bit width expansion unit, and the bit width expansion unit is used to perform a floating-point operation on the operand before performing a floating-point operation on the operand. Expand the bit width.

24. A processing system, comprising:

processor;

The memory is used to store the floating-point operation instructions executable by the processor and the operands corresponding to the floating-point operation instructions;

The processor is configured to implement the method of any one of claims 1-9 when the processor is configured to execute the floating-point operation instruction to process the operand.