CN112202441B

CN112202441B - Buffer circuit and method thereof

Info

Publication number: CN112202441B
Application number: CN202010652833.1A
Authority: CN
Inventors: 陈佳惠; 林宛彦; 张家荣
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2019-07-08
Filing date: 2020-07-08
Publication date: 2024-09-06
Anticipated expiration: 2040-07-08
Also published as: CN112202441A; DE102020114004A1; KR20210006862A; KR102370950B1

Abstract

A circuit includes a first inverter and a second inverter. The first inverter is coupled to the input terminal. The input terminal receives an input signal that varies in a first voltage domain. The second inverter is coupled between the first inverter and the output terminal. The second inverter generates an output signal that varies in a second voltage domain. The first inverter includes a first PMOS transistor and a first NMOS transistor. The first PMOS transistor is biased by a first input tracking signal generated from the input signal. The first input tracking signal varies in a third voltage domain. The first NMOS transistor is biased by a second input tracking signal generated from the input signal. The second input tracking signal varies in a second voltage domain. Embodiments of the present disclosure also relate to buffer circuits and methods for operating buffer circuits.

Description

Buffer circuit and method thereof

Technical Field

The embodiment of the invention relates to a buffer circuit and a method thereof.

Background

With the advent of submicron technology, the device size of the core components in IC chips has become smaller and smaller to increase speed and cost. At the same time, the operating voltage of the core components must also be scaled down to accommodate the reduced dimensions, such as thinner oxides and narrower spaces. But at the board level (boardlevel), signals still travel under conventional high pressure to and from core components on the interface to interoperate with other chips and maintain signal integrity. For example, a core component in an IC chip may have an internal operating voltage of 1.0V, but may still interface with other devices at a 2.5V level. For such IC chips, the input buffer must convert an external signal with a large voltage swing into an internal signal with a narrow voltage swing.

Disclosure of Invention

According to some embodiments of the invention, there is provided a buffer circuit comprising: a first inverter coupled to an input terminal that receives an input signal that changes from a negative power supply level to a first positive power supply level in a first voltage domain; and a second inverter coupled between the first inverter and the output terminal, the second inverter generating an output signal that varies from a negative power supply level to a second positive power supply level in a second voltage domain, wherein the first inverter comprises: a first PMOS transistor biased by a first input tracking signal generated from an input signal that varies in a third voltage domain from a reference level to a first positive power supply level, the reference level being higher than the negative power supply level; and a first NMOS transistor biased by a second input tracking signal generated from the input signal, the second input tracking signal varying in a second voltage domain.

According to further embodiments of the present invention, there is provided a buffer circuit including: a first PMOS transistor biased by a first input tracking signal generated from an input signal that varies from a negative power supply level to a first positive power supply level in a first voltage domain, the first input tracking signal varying from a reference level to the first positive power supply level in a third voltage domain, the reference level being higher than the negative power supply level; a second PMOS transistor having a source terminal coupled to the first positive power supply level, a gate terminal biased by the reference level, and a drain terminal coupled to the source terminal of the first PMOS transistor; a third PMOS transistor having a source terminal coupled to the drain terminal of the first PMOS transistor, a gate terminal biased by a reference level, and a drain terminal coupled to the first node; a first NMOS transistor biased by a second input tracking signal generated from the input signal that varies in a second voltage domain from a negative power supply level to a second positive power supply level, a source terminal of the first NMOS transistor coupled to the negative power supply level; and a second NMOS transistor having a drain terminal coupled to the first node, a gate terminal biased by a second positive power supply level, a source terminal coupled to the drain terminal of the first NMOS transistor, wherein a first inverted signal that varies in the first voltage domain is generated on the first node.

According to still further embodiments of the present invention, there is provided a method for operating a buffer circuit, comprising: generating a first input tracking signal that changes from a reference level to a first positive power supply level in a third voltage domain based on an input signal that changes from a negative power supply level to the first positive power supply level in the first voltage domain; generating a second input tracking signal that varies from a negative power supply level to a second positive power supply level in a second voltage domain based on the input signal; biasing the pull-up transistor with a first input tracking signal; and biasing the pull-down transistor with the second input tracking signal.

Drawings

The various aspects of the invention are best understood from the following detailed description when read in connection with the accompanying drawings. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1 is a schematic diagram illustrating an input buffer circuit according to various embodiments of the present disclosure.

Fig. 2 is a signal waveform illustrating an input signal into the input buffer circuit of fig. 1 and an output signal generated by the input buffer circuit according to various embodiments of the present disclosure.

Fig. 3A is a signal relationship diagram illustrating a relationship between an input signal and a first input tracking signal according to various embodiments of the present disclosure.

Fig. 3B is a signal relationship diagram illustrating a relationship between an input signal and a second input tracking signal according to various embodiments of the present disclosure.

Fig. 4A is a signal waveform illustrating a relationship between an input signal and a first input tracking signal according to various embodiments of the present disclosure.

Fig. 4B is a signal waveform illustrating a relationship between an input signal and a second input tracking signal according to various embodiments of the present disclosure.

Fig. 4C is a signal waveform illustrating a relationship between an input signal SIN and a first inverted signal according to various embodiments of the present disclosure.

Fig. 4D is a signal waveform illustrating a relationship between an input signal and a second inverted signal according to various embodiments of the present disclosure.

Fig. 5A is a schematic diagram showing another structure of the track-high circuit in fig. 1.

Fig. 5B is a schematic diagram showing another structure of the track-high circuit in fig. 3.

Fig. 6 is a schematic diagram illustrating an input buffer circuit according to various embodiments of the present disclosure.

Fig. 7 is a signal waveform illustrating an input signal into the input buffer circuit in fig. 6 and an output signal generated by the input buffer circuit according to various embodiments of the present disclosure.

Fig. 8 is a schematic diagram illustrating an input buffer circuit according to various embodiments of the present disclosure.

Fig. 9 is a signal waveform illustrating an input signal SIN entering the input buffer circuit of fig. 7 and an output signal generated by the input buffer circuit, according to various embodiments of the present disclosure.

Fig. 10 is a schematic diagram illustrating an input buffer circuit according to various embodiments of the present disclosure.

Fig. 11 is a flow chart illustrating a method according to various embodiments of the present disclosure.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

The terms used in the present specification generally have the ordinary meaning in the art and in the specific context in which each term is used. Examples used in this specification, including examples of any terms discussed herein, are illustrative only and in no way limit the scope and meaning of the disclosure or any exemplary terms. Also, the present disclosure is not limited to the various embodiments presented in this specification.

It will be understood that, although the terms "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the embodiments. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

As used herein, the terms "comprising," "including," "having," "containing," "involving," and the like are to be construed as open-ended, i.e., to mean including but not limited to.

Reference throughout this specification to "one embodiment," "an embodiment," or "some embodiments" means that a particular feature, structure, implementation, or characteristic described in connection with the embodiment is included in at least one embodiment of the present invention. Thus, the use of the phrases "in one embodiment" or "in an embodiment" or "in some embodiments" in various places throughout this specification is not necessarily all referring to the same embodiment. Furthermore, the particular components, structures, implementations, or characteristics may be combined in any suitable manner in one or more embodiments.

Fig. 1 is a schematic diagram illustrating an input buffer circuit 100a according to various embodiments of the present disclosure. In some embodiments, input buffer circuit 100a is coupled between input terminal N0 and output terminal N2. Based on the input signal SIN at the input terminal N0, the input buffer circuit 100a is configured to generate the output signal SOUT at the output terminal N2.

With further reference to fig. 2. Fig. 2 is a signal waveform illustrating an input signal SIN input to the input buffer circuit 100a and an output signal SOUT generated by the input buffer circuit 100a in fig. 1 according to various embodiments of the present disclosure. For ease of understanding, with respect to the embodiment of fig. 1, like elements in fig. 2 are labeled with like reference numerals.

Fig. 2 shows a simulation result of the output signal SOUT in response to the voltage level of the input signal SIN rising from the negative power supply level VSS to the first positive power supply level VDDH and then falling from the first positive power supply level VDDH back to the negative power supply level VSS. As shown in fig. 2, when the input signal SIN is higher than the threshold voltage Vt, the output signal SOUT generated by the input buffer circuit 100a is at a logic "1" or high level; when the input signal SIN is lower than the threshold voltage Vt, the output signal SOUT generated by the input buffer circuit 100a is also at a logic "0" or low level. In other words, the output signal SOUT has the same logic as the input signal SIN.

As shown in fig. 1 and 2, the input signal SIN and the output signal SOUT operate in different voltage domains. In some embodiments, the input signal SIN is a signal from an external circuit or interface circuit (not shown) on the I/C chip, and the input signal SIN varies in a first voltage domain having a large voltage difference window from the negative power supply level VSS to the first positive power supply level VDDH. For example, the input signal SIN varies between about 0V to about 1.8V. In some embodiments, the output signal SOUT is a signal transmitted toward a core component (not shown in the figure) in the I/C chip, and the output signal SOUT varies in a second voltage domain having a narrower voltage difference window from the negative power supply level VSS to a second positive power supply level VDDM lower than the first positive power supply level VDDH. For example, the output signal SOUT varies between about 0V to about 1.2V.

In some embodiments, the core components are implemented in smaller dimensions, such as thinner oxides and narrower spaces, making the core components susceptible to overdrive voltages and require operation at voltage domains within a narrower voltage difference window. In some embodiments, the input buffer circuit 100a is configured to convert an input signal SIN varying in a first voltage domain into an output signal SOUT varying in a second voltage domain to protect a core component driven by the output signal SOUT.

As shown in fig. 1, the input buffer circuit 100a includes a first inverter 110, a second inverter 120, a track high circuit 131, a track low circuit 132, and another track low circuit 134. In some embodiments, the first inverter 110 is configured to generate the first inverted signal INB1 in response to the input signal SIN, and the second inverter 120 is configured to generate the output signal SOUT in response to the first inverted signal INB 1.

As shown in fig. 1, the tracking high circuit 131 is configured to convert the input signal SIN into a first input tracking signal INH. With further reference to fig. 3A, fig. 3A is a signal relationship diagram illustrating a relationship between an input signal SIN and a first input tracking signal INH according to various embodiments of the present disclosure. For ease of understanding, with respect to the embodiments of fig. 1 and 2, like elements in fig. 3A are labeled with like reference numerals. As shown in fig. 3A, when the input signal SIN is higher than the reference level VDDL, the tracking high circuit 131 copies the input signal SIN as the first input tracking signal INH. As shown in fig. 3A, when the input signal SIN is lower than the reference level VDDL, the tracking high circuit 131 keeps the first input tracking signal INH fixed at the reference level VDDL. In other words, in response to the input signal SIN varying in the first voltage domain (from VSS to VDDH), the track-high circuit 131 generates the first input track signal INH varying in the third voltage domain (from VDDL to VDDH).

In some embodiments, the reference level VDDL is a voltage level between the negative power supply level VSS and the second positive power supply level VDDM. In some embodiments, the reference level VDDL may be configured as the first positive power supply level VDDH minus the second positive power supply level VDDM. For example, when the first positive power supply level VDDH is about 1.8V and the second positive power supply level VDDM is about 1.2V, the reference level VDDL may be configured to be about 0.6V.

As shown in fig. 1, the tracking low circuit 132 is configured to convert the input signal SIN into a second input tracking signal INL. With further reference to fig. 3B, fig. 3B is a signal relationship diagram illustrating a relationship between an input signal SIN and a second input tracking signal INL according to various embodiments of the present disclosure. For ease of understanding, with respect to the embodiment of fig. 3A, like elements in fig. 3B are labeled with like reference numerals. As shown in fig. 3B, when the input signal SIN is lower than the second positive power supply level VDDM, the tracking high circuit 132 copies the input signal SIN as the second input tracking signal INL. As shown in fig. 3B, when the input signal SIN exceeds the second positive power supply level VDDM, the tracking high circuit 132 keeps the second input tracking signal INL fixed at the second positive power supply level VDDM. In other words, in response to the input signal SIN varying in a first voltage domain (from VSS to VDDH), the track-high circuit 132 generates a second input track signal INH varying in a second voltage domain (from VSS to VDDM).

As shown in fig. 1, in some embodiments, the first inverter 110 includes five transistors connected in series between a first positive power supply level VDDH and a negative power supply level VSS. In the embodiment shown in fig. 1, there are three PMOS transistors MP1 to MP3 and two NMOS transistors MN1 to MN2 in the first inverter 110.

As shown in fig. 1, in some embodiments, the source terminal of PMOS transistor MP2 is coupled to a first positive power supply level VDDH. The gate terminal of PMOS transistor MP2 is biased by reference level VDDL. Since the reference level VDDL is lower than the first positive power supply level VDDH, the PMOS transistor MP2 is normally turned on. The drain terminal of PMOS transistor MP2 is coupled to the source terminal of PMOS transistor MP 1. The source terminal of PMOS transistor MP1 is coupled to the drain terminal of PMOS transistor MP 2. The gate terminal of the PMOS transistor MP1 is biased by the first input tracking signal INH varying in the third voltage domain. The drain terminal of PMOS transistor MP1 is coupled to the source terminal of PMOS transistor MP 3. The gate terminal of PMOS transistor MP3 is biased by reference level VDDL. The drain terminal of PMOS transistor MP3 is coupled to first node N1.

The PMOS transistors MP 1-MP 3 are configured to pull up the voltage level of the first inversion signal INBl at the first node Nl (i.e., the output node of the first inverter 110) in response to the first input tracking signal INH.

With further reference to fig. 4A-4D. Fig. 4A is a signal waveform illustrating a relationship between an input signal SIN and a first input tracking signal INH according to various embodiments of the present disclosure. Fig. 4B is a signal waveform illustrating a relationship between an input signal SIN and a second input tracking signal INL according to various embodiments of the present disclosure. Fig. 4C is a signal waveform illustrating a relationship between an input signal SIN and a first inverted signal INB1 according to various embodiments of the present disclosure. Fig. 4D is a signal waveform illustrating a relationship between the input signal SIN and the second inverted signal INB2 according to various embodiments of the present disclosure. For ease of understanding, with respect to the embodiments of fig. 1 and 2, like elements in fig. 4A-4D are labeled with like reference numerals.

As shown in fig. 4A and 4C, when the input signal SIN is lower than the threshold voltage Vt, the first input tracking signal INH is correspondingly lower than the threshold voltage Vt and turns on the PMOS transistor MP1. Accordingly, the PMOS transistor MP3 is also turned on (MP 2 is also turned on), so that the first inversion signal INB1 is pulled up to the first positive power supply level VDDH.

Note that the terminals of the PMOS transistors MP1 to MP3 operate in the third voltage domain (from VDDL to VDDH). The third voltage difference window (VDDH-VDDL) of the third voltage domain is smaller than the first voltage difference window (VDDH-VSS) of the first voltage domain. For example, when vddh=1.8v, vddl=0.6V, and vss=0v, the third voltage difference window 1.2V is smaller than the first voltage difference window 1.8V. In this case, since the terminals of the PMOS transistors MP1 to MP3 operate in the third voltage domain, the PMOS transistors MP1 to MP3 in the first inverter 110 may be implemented with smaller-sized transistors having relatively lower voltage margins (compared to transistors operating in the first voltage domain having a larger voltage difference window), and the smaller-sized transistors MP1 to MP3 may be operated with lower leakage currents and lower power consumption.

As shown in fig. 1, the drain terminal of the NMOS transistor MN2 is coupled to the first node N1. The gate terminal of the NMOS transistor is biased by the second positive power supply level VDDM. The source terminal of NMOS transistor MN2 is coupled to the drain terminal of NMOS transistor MN 1. The gate terminal of the NMOS transistor MN1 is biased by the second input tracking signal INL, which is generated from the input signal by the second tracking circuit 132. The source terminal of NMOS transistor MN1 is coupled to negative supply level VSS.

The NMOS transistors MN1 to MN2 are configured to pull down the voltage level of the first inversion signal INB1 at the first node N1 in response to the second input tracking signal INL.

As shown in fig. 4A and 4C, when the input signal SIN is higher than the threshold voltage Vt, the second input tracking signal INL is correspondingly higher than the threshold voltage Vt and turns on the NMOS transistor MN1. Accordingly, the NMOS transistor MN2 is also turned on, so that the first inverted signal INB1 is pulled down to the negative power supply level VSS.

Note that the terminals of the NMOS transistors MN1 to MN2 operate in the second voltage domain (from VSS to VDDM). The second voltage difference window (VDDM-VSS) of the second voltage domain is smaller than the first voltage difference window (VDDH-VSS) of the first voltage domain. For example, when vddh=1.8v, vddm=1.2V, and vss=0v, the second voltage difference window 1.2V is smaller than the first voltage difference window 1.8V. In some embodiments, the second voltage difference window (VDDM-VSS) may be substantially equal to the third voltage difference window (VDDH-VDDL) described above. In this case, since the terminals of the NMOS transistors MN1 to MN2 operate in the second voltage domain, the NMOS transistors MN1 to MN2 in the first inverter 110 may be implemented with smaller-sized transistors having relatively lower voltage margins (compared to transistors operating in the first voltage domain having a larger voltage difference window), and the smaller-sized transistors MN1 to MN2 may be operated with lower leakage currents and lower power consumption.

In some examples, if the pull-up transistors (e.g., MP 1-MP 3) and pull-down transistors (e.g., MN 1-MN 2) are driven by the same input tracking signal, such as a second input tracking signal INL that varies in a second voltage domain (from VSS to VDDM), the bias voltages of the pull-up transistors (e.g., MP 1-MP 3) and pull-down transistors (e.g., MN 1-MN 2) will shift to a lower voltage range (from VSS to VDDM) than the full voltage range (from VSS to VDDH). Shifting these bias voltages to a lower voltage range is undesirable because it is desirable that the threshold voltage Vt of the input buffer circuit 100a may be near an intermediate level between VSS to VDDH of the input signal SIN. To compensate for the bias voltage shifted to the lower voltage range and maintain the threshold voltage Vt, the size of the pull-up transistors (e.g., MP 1-MP 3) needs to be larger than the pull-down transistors (e.g., MN 1-MN 2) in order to allow the pull-up transistors (e.g., MP 1-MP 3) to operate in a larger voltage difference window from VSS to VDDH. In some examples, the ratio between the size of the pull-up transistors (MP 1-MP 3) and the size of the pull-down transistors (e.g., MN 1-MN 2) may reach 50:1 to 100:1. it is difficult to implement PMOS transistors and NMOS transistors on circuit layouts having such large size differences. In other words, the first inverter may have a reasonable size ratio between the PMOS transistor and the NMOS transistor.

As shown in fig. 1, since the pull-up transistors (e.g., MP 1-MP 3) and the pull-down transistors (e.g., MN 1-MN 2) are driven by different input tracking signals INH and INL. The first input tracking signal INH of the pull-up transistors (e.g., MP 1-MP 3) and the second input tracking signal INL of the pull-down transistors (e.g., MN 1-MN 2) will cover the full voltage range (from VSS to VDDH) of the input signal SIN. In some embodiments, the input buffer circuit 100a in FIG. 1 does not need to compensate for the offset of the bias voltage, so that the dimensions of the pull-up transistors (e.g., MP 1-MP 3) may be similar to the dimensions of the pull-down transistors (e.g., MN 1-MN 2). In some embodiments, the ratio between the size of the pull-up transistors (MP 1-MP 3) and the size of the pull-down transistors (e.g., MN 1-MN 2) may be about 1: 1. 2:1 or 3:2. PMOS transistors and NMOS transistors are easier to implement on circuit layouts having similar dimensions.

Note that the above voltage values of the input signal SIN (from about 0V to about 1.8V) and the above voltage values of the output signal SOUT (from about 0V to about 1.2V) are given for demonstration. The present disclosure is not limited thereto. In some embodiments, second positive power supply level VDDM may be equal to or higher than half of first positive power supply level VDDH. For example, when the first positive power supply level VDDH is set to 3.6V, the second positive power supply level VDDM may be equal to or higher than 1.8V. If the second positive power supply level VDDM is lower than half the first positive power supply level VDDH, the first input tracking signal INH and the second input tracking signal INL will not be able to cover the full voltage range (from VSS to VDDH) of the input signal SIN.

As shown in fig. 1 and 4C, the first inversion signal INB1 at the first node N1 may be pulled up to the first positive power supply level VDDH through MP 1-MP 3 or may be pulled down to the negative power supply level VSS through MN 1-MN 2 to vary the first inversion signal INB1 in the first voltage domain.

As shown in fig. 1, 4C, and 4D, the first inverted signal INB1 is converted into a second inverted signal INB2 varying in the second voltage domain by the tracking low circuit 134. The tracking low circuit 134 behaves similarly to the tracking low circuit 132 described above, and the relationship between the first inverted signal INB1 and the second inverted signal INB2 is similar to the relationship between the input signal SIN and the second input tracking signal INL, as shown in fig. 3B. As shown in fig. 4C and 4C, when the first inversion signal INB1 is lower than the second positive power supply level VDDM, the tracking high circuit 134 copies the first inversion signal INB1 to the second inversion signal INB2. As shown in fig. 4C and 4D, when the first inverted signal INB1 exceeds the second positive power supply level VDDM, the tracking high circuit 134 keeps the second inverted signal INB2 fixed at the second positive power supply level VDDM. In other words, the track-high circuit 134 generates the second inverted signal INB2 that varies in the second voltage domain (from VSS to VDDM) from the first inverted signal INB1 that varies in the first voltage domain (from VSS to VDDH).

As shown in fig. 1, 2 and 4D, the second inverter 120 is configured to invert the second inversion signal INB2 in the second voltage domain into an output signal SOUT (as shown in fig. 2) also in the second voltage domain. In some embodiments, the second inverter 120 is configured to invert the signal in the same voltage domain, such that the second inverter 120 may be implemented with a CMOS inverter.

In the embodiment shown in fig. 1, the track-high circuit 131 includes two PMOS transistors MP4 and MP5. The source terminal of PMOS transistor MP4 is coupled to the gate terminal of PMOS transistor MP 1. The gate terminal of PMOS transistor MP4 is coupled to input terminal N0. The drain terminal of PMOS transistor MP4 is coupled to reference level VDDL. The source terminal of PMOS transistor MP5 is coupled to the gate terminal of PMOS transistor MP 1. The gate terminal of PMOS transistor MP5 is coupled to reference level VDDL. The drain terminal of PMOS transistor MP5 is coupled to input terminal N0. When the input signal SIN is high, the PMOS transistor MP4 is turned off and the PMOS transistor MP5 is turned on, thereby reproducing the input signal SIN as the first input track signal INH. When the input signal SIN is low, the PMOS transistor MP4 is turned on, and the PMOS transistor MP4 pulls the first input tracking signal INH down to the reference level VDDL.

In the embodiment shown in fig. 1, the tracking low circuit 132 includes two NMOS transistors MN3 and MN4. The source terminal of NMOS transistor MN3 is coupled to the second positive power supply level VDDM. The gate terminal of the NMOS transistor MN3 is coupled to the input terminal N0. The drain terminal of NMOS transistor MN3 is coupled to the gate terminal of NMOS transistor MN 1. The source terminal of NMOS transistor MN4 is coupled to the gate terminal of NMOS transistor MN 1. The gate terminal of NMOS transistor MN4 is coupled to the second positive power supply level VDDM. The drain terminal of NMOS transistor MN4 is coupled to input terminal N0. When the input signal SIN is low, the NMOS transistor MN3 is turned off and the NMOS transistor MN4 is turned on, thereby reproducing the input signal SIN as the second input tracking signal INL. When the input signal SIN is high, the NMOS transistor MN3 is turned on, and the NMOS transistor MN3 keeps the second input tracking signal INL fixed at the second positive power supply level VDDM. In some embodiments, the structure of the tracking low circuit 134 is similar to the structure of the tracking low circuit 132.

Note that the tracking high circuit 131, the tracking low circuits 132 and 134 are not limited to the structure shown in fig. 1. With further reference to fig. 5A and 5B. Fig. 5A is a schematic diagram showing another structure of the track-high circuit 131 in fig. 1. Fig. 5B is a schematic diagram showing another structure of the track-high circuit 132 in fig. 1. With respect to the embodiment of fig. 1. For ease of understanding, with respect to the embodiment of fig. 1, like elements in fig. 5A-5B are labeled with like reference numerals.

In the embodiment shown in fig. 5A, the track-high circuit 131 includes a PMOS transistor MP4a and a resistor R1. The source terminal of the PMOS transistor MP4a is coupled to the gate terminal of the PMOS transistor MP1 for outputting the first input track signal INH (refer to fig. 1). The gate terminal of the PMOS transistor MP4a is coupled to an input terminal N0 (refer to fig. 1) for receiving the input signal SIN. The drain terminal of the fourth PMOS transistor is coupled to the reference level VDDL. The first terminal of resistor R1 is coupled to a first positive power supply level VDDH. A second terminal of the resistor R1 is coupled to a gate terminal of the PMOS transistor MP1 for outputting the first input track signal INH (refer to fig. 1). Similar to the relationship shown in fig. 3A, the structure of the tracking high circuit 131 in fig. 5A will generate the first input tracking signal INH in response to the input signal SIN.

In the embodiment shown in fig. 5B, the tracking low circuit 132 includes an NMOS transistor MN3a and a resistor R2. The source terminal of the NMOS transistor MN3a is coupled to the gate terminal of the NMOS transistor MN1 for outputting the second input tracking signal INL (refer to fig. 1). The gate terminal of the NMOS transistor MN3a is coupled to an input terminal N0 (refer to fig. 1) for receiving the input signal SIN. The drain terminal of the NMOS transistor MN3a is coupled to the second positive power supply level VDDM. The first terminal of the resistor R2 is coupled to the gate terminal of the NMOS transistor MN1 for outputting the second input tracking signal INL (refer to fig. 1). A second terminal of resistor R2 is coupled to a negative supply level VSS. Similar to the relationship shown in fig. 3A, the structure of the tracking low circuit 132 in fig. 5B will generate the second input tracking signal INL in response to the input signal SIN.

In other words, the tracking high circuit 131, the tracking low circuits 132 and 134 are not limited to the structure shown in fig. 1. Any equivalent circuit capable of generating a tracking signal (refer to the correspondence shown in fig. 3A and 3B) corresponding to an input signal may be used in the input buffer circuit 100 a.

In some embodiments, the input buffer circuit 100a shown in fig. 1 includes PMOS and NMOS transistors connected in cascade, and each of the PMOS and NMOS transistors is biased by a gate signal in a suitable voltage domain, so that the PMOS and NMOS transistors can be formed in a small size and have a small standby leakage power. In addition, the first inverter 110 in the input buffer circuit 100a may have a reasonable size ratio between PMOS transistors and NMOS transistors. As shown in fig. 2, the duty cycle of the output signal SOUT generated by the input buffer circuit 100a in response to the input signal SIN is about 50%. Because the first inverter 110 is capable of detecting the full voltage range of the input signal SIN, the duty cycle of the output signal SOUT generated by the input buffer circuit 100a under different process/voltage/temperature (PVT) conditions may be approximately 50% (e.g., about 40% to about 60%) compared to biasing the first inverter with a partial voltage range of the input signal SIN. In the foregoing embodiment, the input buffer circuit 100a changes the level of the output signal SOUT in response to the input signal SIN with respect to the threshold voltage.

In some other embodiments, the input buffer circuit may include a schmitt trigger function that may have different threshold voltages, one for the input signal SIN from low to high and another for the input signal SIN from high to low.

With further reference to fig. 6. Fig. 6 is a schematic diagram illustrating an input buffer circuit 100b according to various embodiments of the present disclosure. In some embodiments, input buffer circuit 100b is coupled between input terminal N0 and output terminal N2. Based on the input signal SIN at the input terminal N0, the input buffer circuit 100b is configured to generate the output signal SOUT at the output terminal N2. For ease of understanding, with respect to the embodiments of fig. 1-5B, like elements in fig. 6 are labeled with like reference numerals.

In contrast to the input buffer circuit 100a in fig. 1, the input buffer circuit 100b in fig. 6 further comprises a feedback loop 141 coupled between the output terminal N2 and the first node N1. The feedback loop 141 includes NMOS transistors MN5 and MN6. The drain terminal of the NMOS transistor MN5 is coupled to the first node N1. The gate terminal of the NMOS transistor MN5 is coupled to the second positive power supply level VDDM. The drain terminal of NMOS transistor MN6 is coupled to the source terminal of NMOS transistor MN 5. The gate terminal of NMOS transistor MN6 is coupled to output terminal N2. The source terminal of NMOS transistor MN6 is coupled to negative supply level VSS. In the embodiment shown in fig. 6, the feedback loop 141 is another pull-down path with respect to the first node N1 in addition to the NMOS transistors MN1 to MN2 in the first inverter 110.

With further reference to fig. 7. Fig. 7 is a signal waveform illustrating an input signal SIN entering the input buffer circuit 100b in fig. 6 and an output signal SOUT generated by the input buffer circuit 100b according to various embodiments of the present disclosure. For ease of understanding, with respect to the embodiment of fig. 6, like elements in fig. 7 are labeled with like reference numerals.

As shown in fig. 6 and 7, during a transition of the input signal SIN from logic "1" to logic "0", for example, from the first positive power supply level VDDH to the negative power supply level VSS, the input signal SIN is initially at the first positive power supply level VDDH (logic "1"), the first inverted signal INB1 is initially at the negative power supply level VSS (logic "0"), and the output signal SOUT is initially at the second positive power supply level VDDM (logic "1"). The NMOS transistors MN1 to MN2 in the first inverter 110 are turned on to pull down the first inversion signal INB1 at the first node N1. In addition, the output signal SOUT is fed back to turn on the NMOS transistor MN6 in the feedback loop 141. Accordingly, the NMOS transistors MN5 and MN6 are also turned on to pull the low voltage level at the first node N1.

During the gradual transition of the input signal SIN from the first positive power level VDDH to the negative power level VSS, the first inversion signal INB1 and the output signal SOUT will flip later than the original threshold voltage Vt because there are two pull-up low paths (MN 1-MN 2 and MN 5-MN 6) with respect to one pull-up path (MP 1-MP 3). As shown in fig. 7, when the input signal SIN reaches the low threshold voltage Vt-, the output signal SOUT is flipped from the second positive power supply level VDDM to the negative power supply level VSS. In this case, the input buffer circuit 100b has a schmitt trigger function having one threshold voltage Vt related to the input signal SIN from logic "0" to logic "1" and another threshold voltage Vt-related to the input signal SIN from logic "1" to logic "0".

In other words, when the input signal SIN changes from logic "1" to logic "0", the feedback loop 141 in the input buffer circuit 100b is utilized to lower the low threshold voltage Vt-of the input buffer circuit 100 b.

In some other embodiments, the input buffer circuit may include schmitt trigger functionality in both aspects of the threshold voltage when the input signal SIN changes from a logic "1" to a logic "0" and when the input signal SIN changes from a logic "0" to a logic "1". With further reference to fig. 8. Fig. 8 is a schematic diagram illustrating an input buffer circuit 100c according to various embodiments of the present disclosure. In some embodiments, input buffer circuit 100c is coupled between input terminal N0 and output terminal N2. Based on the input signal SIN at the input terminal N0, the input buffer circuit 100c is configured to generate the output signal SOUT at the output terminal N2. For ease of understanding, with respect to the embodiments of fig. 1 and 6, like elements in fig. 8 are labeled with like reference numerals.

In comparison to the input buffer circuit 100b of fig. 6, the input buffer circuit 100c of fig. 8 further comprises a tracking high circuit 133, a third inverter 150 and a further feedback loop 142 (in addition to the feedback loop 141). In some embodiments, the structure of the track-high circuit 133 is similar to the track-high circuit 131 discussed in fig. 1-5A, and the track-high circuit 133 behaves similar to the track-high circuit 131 discussed in fig. 3A and 4A. Therefore, the structure and behavior of the tracking high circuit 133 are not described in detail. The tracking high circuit 133 is used to convert the first inverted signal INB1 varying in the first voltage domain into a third inverted signal INBH varying in the third voltage domain. The third inverting signal INBH is inverted by the third inverter 150 to a high output signal OUTH varying in the third voltage domain. The high output signal OUTH is fed back to the feedback loop 142.

As shown in fig. 8, the feedback loop 142 includes PMOS transistors MP6 and MP7. The source terminal of PMOS transistor MP6 is coupled to a first positive power supply level VDDH. The gate terminal of PMOS transistor MP6 is coupled to third inverter 150. The source terminal of PMOS transistor MP7 is coupled to the drain terminal of PMOS transistor MP 6. The gate terminal of PMOS transistor MP7 is coupled to reference level VDDL. The drain terminal of PMOS transistor MP7 is coupled to first node N1.

In the embodiment shown in fig. 8, the feedback loop 141 is another pull-up path with respect to the first node N1 in addition to the PMOS transistors MP 1-MP 3 in the first inverter 110.

With further reference to fig. 9. Fig. 9 is a signal waveform illustrating an input signal SIN entering the input buffer circuit 100c in fig. 6 and an output signal SOUT generated by the input buffer circuit 100c, according to various embodiments of the present disclosure. For ease of understanding, with respect to the embodiment of fig. 8, like elements in fig. 9 are labeled with like reference numerals.

As shown in fig. 8 and 9, during the transition of the input signal SIN from logic "0" to logic "1", for example, from the negative power supply level VSS to the first positive power supply level VDDH, the input signal SIN is initially at the negative power supply level VSS (logic "0"), the first inverted signal INB1 is initially at the first positive power supply level VDDH (logic "1"), and the output signal SOUT is initially at the negative power supply level VSS (logic "0"). The PMOS transistors MP1 to MP3 in the first inverter 110 are turned on to pull up the first inversion signal INB1 at the first node N1. In addition, the high output signal OUTH is fed back to turn on the PMOS transistor MN6 in the feedback loop 142. Thus, PMOS transistors MN6 and MN7 are also turned on to pull the voltage level high at the first node N1.

During the gradual transition of the input signal SIN from the negative power supply level VSS to the first positive power supply level VDDH, the first inversion signal INB1 and the output signal SOUT will flip later than the original threshold voltage Vt because there are two pull-down paths (MP 1-MP 3 and MP 6-MP 7). As shown in fig. 9, when the input signal SIN reaches the high threshold voltage vt+, the output signal SOUT is flipped from the second positive power supply level VDDM to the negative power supply level VSS. In this case, the input buffer circuit 100c has a schmitt trigger function having one high threshold voltage vt+ associated with the input signal SIN from logic "0" to logic "1" and one low threshold voltage vt+ associated with the input signal SIN from logic "1" to logic "0". The high threshold voltage Vt+ is higher than the threshold voltage Vt, and the low threshold voltage Vt-is lower than the threshold voltage Vt.

In other words, when the input signal SIN changes from logic "1" to logic "0", the feedback loop 141 in the input buffer circuit 100b is utilized to lower the low threshold voltage Vt-of the input buffer circuit 100 b. In other words, the input buffer circuit 100c has a schmitt trigger function in both aspects of the threshold voltage when the input signal SIN changes from logic "1" to logic "0" and when the input signal SIN changes from logic "0" to logic "1".

With further reference to fig. 10. Fig. 10 is a schematic diagram illustrating an input buffer circuit 100d according to various embodiments of the present disclosure. In some embodiments, input buffer circuit 100d is coupled between input terminal N0 and output terminal N2. Based on the input signal SIN at the input terminal N0, the input buffer circuit 100d is configured to generate the output signal SOUT at the output terminal N2. For ease of understanding, with respect to the embodiments of fig. 1-9, like elements in fig. 10 are labeled with like reference numerals.

In some embodiments, the input buffer circuit 100d in fig. 10 further includes an input enable function controlled by an enable signal. When the enable signal is high or logic "1", the input buffer circuit 100d is activated in response to the input signal SIN to generate the output signal SOUT. On the other hand, when the input enable signal is low or logic "0", the input buffer circuit 100d is deactivated and does not respond to the input signal SIN.

In comparison with the input buffer circuit 100b in fig. 6, the input buffer circuit 100d in fig. 10 further includes a PMOS transistor MP8, an NMOS transistor MN7, another NMOS transistor MN8, AND an AND (AND) logic gate 142. In addition, the second inverter 120 in the input buffer circuit 100d is implemented with a NOR (NOR) logic inverter. The second inverter 120 performs nor logic between the second inversion signal INB2 varying in the second voltage domain and the inversion enable signal IEB varying in the second voltage domain.

The source terminal of PMOS transistor MP8 is coupled to the first positive power supply level VDDH. The gate terminal of PMOS transistor MP8 is coupled to the first enable signal IEH in the third voltage domain. The drain terminal of PMOS transistor MP8 is coupled to the source terminal of PMOS transistor MP 3.

The source terminal of NMOS transistor MN7 is coupled to negative supply level VSS. The gate terminal of the seventh NMOS transistor is coupled to the second enable signal IE that varies in the second voltage domain. The drain terminal of NMOS transistor MN7 is coupled to the source terminal of NMOS transistor MN 1.

The source terminal of NMOS transistor MN8 is coupled to negative supply level VSS. The gate terminal of the seventh NMOS transistor is coupled to and logic gate 142. The drain terminal of NMOS transistor MN8 is coupled to the source terminal of NMOS transistor MN 6.

The and logic gate 142 is configured to perform an and logic between the second enable signal IE varying in the second voltage domain and the schmitt trigger enable signal ST varying in the second voltage domain.

When the input enable function is on and the schmitt trigger function is on, the first enable signal IEH and the second enable signal IE are configured to be at logic "1"; the inverted enable signal IEB is configured to be at logic "0"; the schmitt trigger enable signal ST is at logic "1". PMOS transistor MP8 is turned off. The NMOS transistors MN7 and MN8 are turned on. The input buffer circuit 100d is activated with the schmitt trigger function.

When the input enable function is on and the schmitt trigger function is off, the first enable signal IEH and the second enable signal IE are configured to be at logic "1"; the inverted enable signal IEB is configured to be at logic "0"; the schmitt trigger enable signal ST is at logic "0". PMOS transistor MP8 is turned off. The NMOS transistor MN7 is turned on and the NMOS transistor MN8 is turned off. The input buffer circuit 100d is activated without the schmitt trigger function.

When the input enable function is turned off, the first enable signal IEH and the second enable signal IE are configured to be at logic "0"; the inverted enable signal IEB is configured to be at a logic "1". PMOS transistor MP8 is turned on. The NMOS transistor MN7 is turned off. The input buffer circuit 100d is deactivated.

In some embodiments, the second enable signal IE, the inverted enable signal IEB, and the schmitt trigger enable signal ST vary in the second voltage domain, and the first enable signal IEH varies in the third voltage domain, such that the transistors in the input buffer circuit 100d may operate in an appropriate voltage variation window.

In the embodiment shown in fig. 10, the input buffer circuit 100d illustrates how the input enable function is integrated onto the input buffer circuit 100b shown in fig. 6. In some other embodiments, the input enable function shown in the input buffer circuit 100d shown in fig. 10 may also be integrated onto the input buffer circuit 100a shown in fig. 1 or the input buffer circuit 100c shown in fig. 8.

Fig. 11 is a flow chart illustrating a method 200 according to various embodiments of the present disclosure. In some embodiments, the method 200 of FIG. 11 may be utilized on the input buffer circuits 100 a-100 d discussed in the previous embodiments shown in FIGS. 1, 6, 8, and/or 10. For ease of understanding, with respect to the embodiments of fig. 1-10, like elements in fig. 11 are labeled with like reference numerals. For brevity, the method 200 in the following paragraphs will be discussed with the embodiment of the input buffer circuit 100a shown in FIG. 1 and the related embodiments in FIGS. 2-5B. It should be noted that the method 200 is also suitable for use in other embodiments of the input buffer circuits 100 b-100 d shown in fig. 6, 8 or 10.

In some embodiments, the method 200 in fig. 11 may be used to generate an output signal SOUT (such as from VSS to VDDM) that varies in a second voltage domain from an input signal SIN (such as from VSS to VDDH) that varies in a first voltage domain.

As shown in fig. 1, 4A and 11, in response to the input signal SIN varying in the first voltage domain (e.g., VSS to VDDH), operation S211 is performed by the trace high circuit 131 to generate the first input trace signal INH varying in the third voltage domain (e.g., from VDDL to VDDH).

As shown in fig. 1, 4B, and 11, in response to the input signal SIN varying in a first voltage domain (e.g., VSS-VDDH), operation S212 is performed by the tracking low circuit 132 to generate a second input tracking signal INL varying in a second voltage domain (e.g., from VSS to VDDM).

In some embodiments, the first voltage domain has a larger voltage difference window, ranging from the negative power supply level VSS to the first positive power supply level VDDH. For example, the first voltage domain covers about 0V to about 1.8V. In some embodiments, the second voltage domain has a narrower window of voltage differences ranging from the negative power supply level VSS to the second positive power supply level VDDM. For example, the second voltage domain covers about 0V to about 1.2V. In some embodiments, the third voltage domain has another narrower window of voltage differences ranging from the reference level VDDL to the first positive power supply level VDDH. For example, the third voltage domain covers about 0.6V to about 1.8V. Note that the above voltage values are for demonstration.

As shown in fig. 1 and 11, operation S221 is performed to bias a pull-up transistor (e.g., PMOS transistor MP 1) with a first input tracking signal INH. As shown in fig. 1 and 11, operation S222 is performed to bias a pull-down transistor (e.g., an NMOS transistor MN 1) with a second input tracking signal INL.

As shown in fig. 1, 4C, and 11, operation S230 is performed to generate a first inversion signal INB1 varying in a first voltage domain through a pull-up transistor and a pull-down transistor in the first inverter 110.

As shown in fig. 1, 4D, and 11, operation S240 is performed to convert the first inverted signal INB1 into the second inverted signal INB2 varying in the second voltage domain by the tracking low circuit 134.

As shown in fig. 1, 2, 4D, and 11, operation S250 is performed to invert the second inversion signal INB2 into the output signal SOUT varying in the second voltage domain through the second inverter 120. In some embodiments, the output signal SOUT is a signal transmitted to a core component (not shown) in the integrated circuit chip.

In some embodiments, the circuit includes a first inverter and a second inverter. The first inverter is coupled to the input terminal. The input terminal receives an input signal that changes from a negative power supply level to a first positive power supply level in a first voltage domain. The second inverter is coupled between the first inverter and the output terminal. The second inverter generates an output signal that changes from a negative power supply level to a second positive power supply level in a second voltage domain. The first inverter includes a first PMOS transistor and a first NMOS transistor. The first PMOS transistor is biased by a first input tracking signal generated from the input signal. The first input tracking signal changes from the reference level to the first positive power supply level in the third voltage domain. The reference level is higher than the negative supply level. The first NMOS transistor is biased by a second input tracking signal generated from the input signal. The second input tracking signal varies in a second voltage domain.

In some embodiments, the first voltage difference window of the first voltage domain is greater than the second voltage difference window of the second voltage domain. The first voltage difference window is greater than a third voltage difference window of the third voltage domain. In some embodiments, the second voltage difference window is substantially equal to the third voltage difference window.

In some embodiments, the first inverter further comprises a second PMOS transistor, a third PMOS transistor, and a second NMOS transistor. The source terminal of the second PMOS transistor is coupled to the first positive power supply level. The gate terminal of the second PMOS transistor is biased by a reference level. The drain terminal of the second PMOS transistor is coupled to the source terminal of the first PMOS transistor. The source terminal of the third PMOS transistor is coupled to the drain terminal of the first PMOS transistor. The gate terminal of the third PMOS transistor is biased by a reference level. The drain terminal of the third PMOS transistor is coupled to the first node. The drain terminal of the second NMOS transistor is coupled to the first node. The gate terminal of the second NMOS transistor is biased by a second positive power supply level. The source terminal of the second NMOS transistor is coupled to the drain terminal of the first NMOS transistor. The source terminal of the first NMOS transistor is coupled to a negative supply level. The first inverter is configured to generate a first inverted signal on the first node that varies in a first voltage domain.

In some embodiments, the circuit further comprises a first tracking high circuit, a first tracking low circuit, and a second tracking low circuit. The first tracking high circuit is coupled between the input terminal and a gate terminal of the first PMOS transistor. The first tracking high circuit is configured to convert an input signal into a first input tracking signal. The first tracking low circuit is coupled between the input terminal and a gate terminal of the first NMOS transistor. The first tracking low circuit is configured to convert an input signal to a second input tracking signal. The second tracking low circuit is coupled between the first node and the second inverter. The second tracking low circuit is configured to convert the first inverted signal to a second inverted signal that varies in the second voltage domain. The second inverter is configured to invert the second inverted signal into an output signal.

In some embodiments, the first track-high circuit includes a fourth PMOS transistor and a fifth PMOS transistor. The source terminal of the fourth PMOS transistor is coupled to the gate terminal of the first PMOS transistor. The gate terminal of the fourth PMOS transistor is coupled to the input terminal. The drain terminal of the fourth PMOS transistor is coupled to the reference level. The source terminal of the fifth PMOS transistor is coupled to the gate terminal of the first PMOS transistor. The gate terminal of the fifth PMOS transistor is coupled to the reference level. The drain terminal of the fifth PMOS transistor is coupled to the input terminal. The first tracking low circuit includes a third NMOS transistor and a fourth NMOS transistor. The source terminal of the third NMOS transistor is coupled to the second positive power supply level. The gate terminal of the third NMOS transistor is coupled to the input terminal. The drain terminal of the third NMOS transistor is coupled to the gate terminal of the first NMOS transistor. The source terminal of the fourth NMOS transistor is coupled to the gate terminal of the first NMOS transistor. The gate terminal of the fourth NMOS transistor is coupled to the second positive power supply level. The drain terminal of the fourth NMOS transistor is coupled to the input terminal.

In some embodiments, the first track-high circuit includes a fourth PMOS transistor and a first resistor. The source terminal of the fourth PMOS transistor is coupled to the gate terminal of the first PMOS transistor. The gate terminal of the fourth PMOS transistor is coupled to the input terminal. The drain terminal of the fourth PMOS transistor is coupled to the reference level. The first terminal of the first resistor is coupled to a first positive power supply level. A second terminal of the first resistor is coupled to a gate terminal of the first PMOS transistor. The first tracking low circuit includes a third NMOS transistor and a second resistor. The source terminal of the third NMOS transistor is coupled to the gate terminal of the first NMOS transistor. The gate terminal of the third NMOS transistor is coupled to the input terminal. The drain terminal of the third NMOS transistor is coupled to the second positive power supply level. The first terminal of the second resistor is coupled to the gate terminal of the first NMOS transistor. A second terminal of the second resistor is coupled to a negative supply level.

In some embodiments, the circuit includes a first feedback loop. The first feedback loop includes a fifth NMOS transistor and a sixth NMOS transistor. The drain terminal of the fifth NMOS transistor is coupled to the first node. The gate terminal of the fifth NMOS transistor is coupled to the second positive power supply level. The drain terminal of the sixth NMOS transistor is coupled to the source terminal of the fifth NMOS transistor. The gate terminal of the sixth NMOS transistor is coupled to the output terminal. The source terminal of the sixth NMOS transistor is coupled to the negative supply level.

In some embodiments, the circuit further comprises a third inverter, a second tracking high circuit, and a second feedback loop. The second tracking high circuit is coupled between the first node and the third inverter. The second tracking low circuit is configured to convert the first inverted signal to a third inverted signal that varies in a third voltage domain. The second feedback loop includes a sixth PMOS transistor and a seventh PMOS transistor. The source terminal of the sixth PMOS transistor is coupled to the first positive power supply level. The gate terminal of the sixth PMOS transistor is coupled to the third inverter. The source terminal of the seventh PMOS transistor is coupled to the drain terminal of the sixth PMOS transistor. The gate terminal of the seventh PMOS transistor is coupled to the reference level. The drain terminal of the seventh PMOS transistor is coupled to the first node.

In some embodiments, the circuit further comprises an eighth PMOS transistor and a seventh NMOS transistor. The source terminal of the eighth PMOS transistor is coupled to the first positive power supply level. The gate terminal of the eighth PMOS transistor is coupled to the first enable signal in the third voltage domain. The drain terminal of the eighth PMOS transistor is coupled to the source terminal of the third PMOS transistor. The source terminal of the seventh NMOS transistor is coupled to the negative supply level. The gate terminal of the seventh NMOS transistor is coupled to the second enable signal in the second voltage domain. The drain terminal of the seventh NMOS transistor is coupled to the source terminal of the first NMOS transistor.

In some embodiments, the reference level is substantially equal to the first positive power supply level minus the second positive power supply level.

In some embodiments, the circuit includes a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, and a second NMOS transistor. The first PMOS transistor is biased by a first input tracking signal generated from the input signal. The input signal changes from a negative power supply level to a first positive power supply level in a first voltage domain. The first input tracking signal changes from the reference level to the first positive power supply level in the third voltage domain. The reference level is higher than the negative supply level. The source terminal of the second PMOS transistor is coupled to the first positive power supply level. The gate terminal of the second PMOS transistor is biased by a reference level. The drain terminal of the second PMOS transistor is coupled to the source terminal of the first PMOS transistor. The source terminal of the third PMOS transistor is coupled to the drain terminal of the first PMOS transistor. The gate terminal of the third PMOS transistor is biased by a reference level. The drain terminal of the third PMOS transistor is coupled to the first node. The first NMOS transistor is biased by a second input tracking signal generated from the input signal. The second input tracking signal changes from a negative power supply level to a second positive power supply level in a second voltage domain. The source terminal of the first NMOS transistor is coupled to a negative supply level. The drain terminal of the second NMOS transistor is coupled to the first node. The gate terminal of the second NMOS transistor is biased by a second positive power supply level. The source terminal of the second NMOS transistor is coupled to the drain terminal of the first NMOS transistor. A first inverted signal that varies in a first voltage domain is generated on a first node.

In some embodiments, the circuit further comprises a first track high circuit and a first track low circuit. The first tracking high circuit is coupled between the input terminal and a gate terminal of the first PMOS transistor. The first tracking high circuit is configured to convert an input signal into a first input tracking signal. The first tracking low circuit is coupled between the input terminal and a gate terminal of the first NMOS transistor. The first tracking low circuit is configured to convert an input signal to a second input tracking signal.

In some embodiments, the circuit further includes a second tracking low circuit coupled to the first node. The second tracking low circuit is configured to convert the first inverted signal to a second inverted signal that varies in the second voltage domain. In some embodiments, the circuit further includes an inverter coupled between the second tracking low circuit and the output terminal. The inverter generates an output signal varying in a second voltage domain from the second inverted signal.

In some embodiments, a method comprises: generating a first input tracking signal that changes from a reference level to a second power supply level in a third voltage domain based on the input signal that changes from the negative power supply level to the first positive power supply level in the first voltage domain; generating a second input tracking signal that varies from a negative power supply level to a second positive power supply level in a second voltage domain based on the input signal; biasing the pull-up transistor with a first input tracking signal; and biasing the pull-down transistor with the second input tracking signal.

In some embodiments, the first voltage difference window of the first voltage domain is greater than the second voltage difference window of the second voltage domain, and the first voltage difference window is greater than the third voltage difference window of the third voltage domain. In some embodiments, the second voltage difference window is substantially equal to the third voltage difference window.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A buffer circuit, comprising:

a first inverter coupled to an input terminal that receives an input signal that changes from a negative power supply level to a first positive power supply level in a first voltage domain;

A second inverter coupled between the first inverter and an output terminal, the second inverter generating an output signal that varies from the negative power supply level to a second positive power supply level in a second voltage domain,

Wherein the first inverter includes:

A first PMOS transistor biased by a first input tracking signal generated from the input signal, the first input tracking signal varying in a third voltage domain from a reference level to the first positive power supply level, the reference level being higher than the negative power supply level; and

A first NMOS transistor biased by a second input tracking signal generated from the input signal, the second input tracking signal varying in the second voltage domain; and

A first feedback loop is coupled between the output of the first inverter and the output of the second inverter and is configured to receive the output signal from the second inverter and to operate in response to the output signal.

2. The buffer circuit of claim 1, wherein a first voltage difference window of the first voltage domain is greater than a second voltage difference window of the second voltage domain, and the first voltage difference window is greater than a third voltage difference window of the third voltage domain.

3. The buffer circuit of claim 2, wherein the second voltage difference window is equal to the third voltage difference window.

4. The buffer circuit of claim 1, wherein the first inverter further comprises:

A second PMOS transistor having a source terminal coupled to the first positive power supply level, a gate terminal biased by a reference level, a drain terminal coupled to a source terminal of the first PMOS transistor;

A third PMOS transistor having a source terminal coupled to the drain terminal of the first PMOS transistor, a gate terminal of the third PMOS transistor biased by the reference level, a drain terminal of the third PMOS transistor coupled to a first node; and

A second NMOS transistor having a drain terminal coupled to the first node, a gate terminal biased by the second positive power supply level, a source terminal coupled to the drain terminal of the first NMOS transistor,

Wherein a source terminal of the first NMOS transistor is coupled to the negative supply level, the first inverter configured to generate a first inverted signal on the first node that varies in the first voltage domain.

5. The buffer circuit of claim 4, further comprising:

A first track-high circuit coupled between the input terminal and a gate terminal of the first PMOS transistor, the first track-high circuit configured to convert the input signal to the first input track signal;

a first tracking low circuit coupled between the input terminal and a gate terminal of the first NMOS transistor, the first tracking low circuit configured to convert the input signal to the second input tracking signal; and

A second tracking low circuit coupled between the first node and the second inverter, the second tracking low circuit configured to convert the first inverted signal to a second inverted signal that varies in the second voltage domain;

Wherein the second inverter is configured to invert the second inverted signal into the output signal.

6. The buffer circuit of claim 5, wherein,

The first track-high circuit includes:

a fourth PMOS transistor having a source terminal coupled to the gate terminal of the first PMOS transistor, a gate terminal coupled to the input terminal, a drain terminal coupled to the reference level; and

A fifth PMOS transistor having a source terminal coupled to the gate terminal of the first PMOS transistor, a gate terminal coupled to the reference level, a drain terminal coupled to the input terminal;

the first tracking low circuit includes:

A third NMOS transistor, a source terminal of the third NMOS transistor coupled to the second positive power supply level, a gate terminal of the third NMOS transistor coupled to the input terminal, a drain terminal of the third NMOS transistor coupled to the gate terminal of the first NMOS transistor; and

A fourth NMOS transistor, a source terminal of the fourth NMOS transistor coupled to the gate terminal of the first NMOS transistor, a gate terminal of the fourth NMOS transistor coupled to the second positive power supply level, a drain terminal of the fourth NMOS transistor coupled to the input terminal.

7. The buffer circuit of claim 5, wherein,

The first track-high circuit includes:

A first resistor having a first terminal coupled to the first positive power supply level and a second terminal coupled to the gate terminal of the first PMOS transistor;

the first tracking low circuit includes:

A third NMOS transistor, a source terminal of the third NMOS transistor coupled to the gate terminal of the first NMOS transistor, a gate terminal of the third NMOS transistor coupled to the input terminal, a drain terminal of the third NMOS transistor coupled to the second positive power supply level; and

A second resistor having a first terminal coupled to the gate terminal of the first NMOS transistor and a second terminal coupled to the negative supply level.

8. The buffer circuit of claim 5, wherein the first feedback loop comprises:

A fifth NMOS transistor, a drain terminal of the fifth NMOS transistor coupled to the first node, a gate terminal of the fifth NMOS transistor coupled to the second positive power supply level; and

A sixth NMOS transistor, the drain terminal of the sixth NMOS transistor coupled to the source terminal of the fifth NMOS transistor, the gate terminal of the sixth NMOS transistor coupled to the output terminal, the source terminal of the sixth NMOS transistor coupled to the negative supply level.

9. The buffer circuit of claim 8, further comprising:

A third inverter;

A second tracking high circuit coupled between the first node and the third inverter, the second tracking low circuit configured to convert the first inverted signal to a third inverted signal that varies in the third voltage domain; and

A second feedback loop, wherein the second feedback loop comprises:

A sixth PMOS transistor, a source terminal of said sixth PMOS transistor coupled to said first positive power supply level, a gate terminal of said sixth PMOS transistor coupled to said third inverter; and

A seventh PMOS transistor, a source terminal of the seventh PMOS transistor coupled to the drain terminal of the sixth PMOS transistor, a gate terminal of the seventh PMOS transistor coupled to the reference level, a drain terminal of the seventh PMOS transistor coupled to the first node.

10. The buffer circuit of claim 4, further comprising:

An eighth PMOS transistor, wherein a source terminal of the eighth PMOS transistor is coupled to the first positive power supply level, a gate terminal of the eighth PMOS transistor is coupled to a first enable signal in the third voltage domain, a drain terminal of the eighth PMOS transistor is coupled to the source terminal of the third PMOS transistor; and

A seventh NMOS transistor, wherein a source terminal of the seventh NMOS transistor is coupled to the negative supply level, a gate terminal of the seventh NMOS transistor is coupled to a second enable signal in the second voltage domain, and a drain terminal of the seventh NMOS transistor is coupled to the source terminal of the first NMOS transistor.

11. The buffer circuit of claim 1, wherein the reference level is equal to the first positive power supply level minus the second positive power supply level.

12. A buffer circuit, comprising:

A first PMOS transistor biased by a first input tracking signal generated from an input signal that varies in a first voltage domain from a negative power supply level to a first positive power supply level, the first input tracking signal varying in a third voltage domain from a reference level to the first positive power supply level, the reference level being higher than the negative power supply level;

A second PMOS transistor having a source terminal coupled to the first positive power supply level, a gate terminal biased by the reference level, a drain terminal coupled to a source terminal of the first PMOS transistor;

A third PMOS transistor having a source terminal coupled to the drain terminal of the first PMOS transistor, a gate terminal of the third PMOS transistor biased by the reference level, a drain terminal of the third PMOS transistor coupled to a first node;

a first NMOS transistor biased by a second input tracking signal generated from the input signal, the second input tracking signal varying in a second voltage domain from the negative power supply level to a second positive power supply level, a source terminal of the first NMOS transistor coupled to the negative power supply level; and

A second NMOS transistor, a drain terminal of the second NMOS transistor coupled to the first node, a gate terminal of the second NMOS transistor biased by the second positive power supply level, a source terminal of the second NMOS transistor coupled to a drain terminal of the first NMOS transistor; and

A first track-high circuit coupled between an input terminal receiving the input signal and a gate terminal of the first PMOS transistor, wherein the first track-high circuit is configured to convert the input signal to the first input track signal and includes a resistor, wherein a first terminal of the resistor is coupled to the first positive power supply level and a second terminal of the resistor is coupled to a gate terminal of the first PMOS transistor,

Wherein a first inverted signal varying in the first voltage domain is generated on the first node.

13. The buffer circuit of claim 12, wherein a first voltage difference window of the first voltage domain is greater than a second voltage difference window of the second voltage domain, and the first voltage difference window is greater than a third voltage difference window of the third voltage domain.

14. The buffer circuit of claim 13, wherein the second voltage difference window is equal to the third voltage difference window.

15. The buffer circuit of claim 12, further comprising:

a first tracking low circuit is coupled between the input terminal and a gate terminal of the first NMOS transistor, the first tracking low circuit configured to convert the input signal to the second input tracking signal.

16. The buffer circuit of claim 12, further comprising:

A second tracking low circuit is coupled to the first node, the second tracking low circuit configured to convert the first inverted signal to a second inverted signal that varies in the second voltage domain.

17. The buffer circuit of claim 16, further comprising:

An inverter coupled between the second tracking low circuit and an output terminal, the inverter generating an output signal varying in the second voltage domain from the second inverted signal.

18. A method for operating a buffer circuit, comprising:

Generating a first input tracking signal that changes from a reference level to a first positive power supply level in a third voltage domain based on an input signal that changes from a negative power supply level to the first positive power supply level in the first voltage domain;

generating a second input tracking signal that varies from a reference level to the first positive power supply level in a second voltage domain based on the input signal;

biasing a pull-up transistor of a first inverter with the first input tracking signal;

biasing a pull-down transistor of the first inverter with the second input tracking signal;

generating, by a second inverter, an output signal based on an output of the first inverter; and

A first feedback loop receives the output signal from the second inverter and operates in response to the output signal from the second inverter.

19. The method of claim 18, wherein a first voltage difference window of the first voltage domain is greater than a second voltage difference window of the second voltage domain, and the first voltage difference window is greater than a third voltage difference window of the third voltage domain.

20. The method of claim 19, wherein the second voltage difference window is equal to the third voltage difference window.