CN112202159A - Balanced current circuit, charger and mobile terminal - Google Patents
Balanced current circuit, charger and mobile terminal Download PDFInfo
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- CN112202159A CN112202159A CN202011040099.XA CN202011040099A CN112202159A CN 112202159 A CN112202159 A CN 112202159A CN 202011040099 A CN202011040099 A CN 202011040099A CN 112202159 A CN112202159 A CN 112202159A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J1/00—Circuit arrangements for DC mains or DC distribution networks
- H02J1/10—Parallel operation of DC sources
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/34—Parallel operation in networks using both storage and other DC sources, e.g. providing buffering
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- Charge And Discharge Circuits For Batteries Or The Like (AREA)
Abstract
The invention discloses an equalizing current circuit, a charger and a mobile terminal, wherein the equalizing current circuit is provided, and comprises: the current detection circuit comprises current detection resistors R1 and R2 connected with input ends, wherein the other end of the current detection resistor R1 is connected to the negative electrode of an operational amplifier U2 and the input end of a power chip D1, the other end of the current detection resistor R is connected to the positive electrode of the operational amplifier U2 and the input end of a power chip D2, the output end of the operational amplifier U2 is connected with the voltage feedback end of the power chip D1 through a resistor R3, the output ends of the power chip D1 and the power chip D2 are respectively connected with the output end of the circuit, and the voltage feedback end of the power chip D2 is connected with the output end through a resistor R7. The current balance output control scheme with simple structure and low cost is realized, so that the current output can be balanced in time when the power consumption of the equipment is large, and the output capacity and the heat dissipation performance of the current are balanced.
Description
Technical Field
The invention relates to the field of mobile communication, in particular to an equalizing current circuit, a charger and a mobile terminal.
Background
In the prior art, with the rapid development of intelligent terminal equipment, the power consumption requirement of the intelligent terminal equipment is higher and higher, and the accompanying power consumption and heat dissipation problems are urgently needed to be solved. In the prior art, the current consumption of the intelligent terminal device is considered to be large, and the dual power supply chips are generally used for supplying power to the circuit or the battery, however, in the scheme, the current distribution is not accurate enough, and the current distribution effect is not good, so that the power consumption and the heat dissipation problem of the intelligent terminal device are not well solved.
Disclosure of Invention
In order to solve the technical defects in the prior art, the invention provides an equalizing current circuit, which comprises: a current detecting resistor R1 and R2 connected with the input end, wherein the other end of the current detecting resistor R1 is connected with the negative electrode of the operational amplifier U2 and the input end of the power supply chip D1, the other end of the current detection resistor R is connected to the anode of the operational amplifier U2 and the input end of the power chip D2, the output end of the operational amplifier U2 is connected with the voltage feedback end of the power supply chip D1 through a resistor R3, the output terminals of the power supply chip D1 and the power supply chip D2 are respectively connected with the output terminal of the circuit, the voltage feedback end of the power supply chip D2 is connected with the output end through a resistor R7, the output end of the power supply chip D1 is grounded through a resistor R4 and a resistor R5, the voltage feedback end of the power chip D1 is grounded through the resistor R5, the output end of the operational amplifier U2 is grounded through the resistor R3 and the resistor R5, and the voltage feedback end of the power chip D2 is grounded through the resistor R6.
Alternatively, when the current passing through the power chip D1 is greater than the current of the power chip D2, the voltage of the negative electrode of the operational amplifier U2 is less than the voltage of the positive electrode of the operational amplifier U2.
Optionally, a high voltage is output through the output terminal of the operational amplifier U2, and the voltage of the voltage feedback terminal of the power chip D1 is increased by the high voltage.
Alternatively, by decreasing the output voltage of the output terminal of the power chip D1, the current through the power chip D1 is decreased, so that the current through the power chip D1 and the current through the power chip D2 reach an equilibrium state.
Alternatively, when the current passing through the power chip D2 is greater than the current of the power chip D1, the voltage of the negative electrode of the operational amplifier U2 is greater than the voltage of the positive electrode of the operational amplifier U2.
Optionally, a low voltage is output through the output terminal of the operational amplifier U2, and the voltage of the voltage feedback terminal of the power chip D1 is reduced through the low voltage.
Alternatively, by increasing the output voltage of the output terminal of the power chip D1, the current passing through the power chip D1 is increased, so that the current passing through the power chip D1 and the current passing through the power chip D2 reach an equilibrium state.
The present invention also provides a charger including an equalizing current circuit, the circuit including: the current detection circuit comprises current detection resistors R1 and R2 connected with input ends, wherein the other end of the current detection resistor R1 is connected to the anode of an operational amplifier U2 and the input end of a power chip D1, the other end of the current detection resistor R is connected to the cathode of the operational amplifier U2 and the input end of the power chip D2, the output end of the operational amplifier U2 is connected with the battery detection end of the power chip D1 through a resistor R3, the output ends of the power chip D1 and the power chip D2 are respectively connected with the charging battery end of the circuit, the battery detection end of the power chip D2 is connected with the charging battery end, the battery detection end of the power chip D1 is connected with the charging battery end through a resistor R4, and the battery detection end of the power chip D1 is grounded through a resistor R5.
Alternatively, when the current passing through the power chip D1 is greater than the current passing through the power chip D2, the voltage of the positive electrode of the operational amplifier U2 is less than the voltage of the negative electrode of the operational amplifier U2, a negative voltage is output through the output terminal of the operational amplifier U2, the voltage of the battery detection terminal of the power chip D1 is reduced through the negative voltage, and the current passing through the power chip D1 is reduced through the reduction of the output voltage of the output terminal of the power chip D1, so that the current passing through the power chip D1 and the current passing through the power chip D2 reach an equilibrium state;
when the current passing through the power chip D2 is greater than the current passing through the power chip D1, the positive voltage of the operational amplifier U2 is greater than the negative voltage of the operational amplifier U2, a positive voltage is output through the output end of the operational amplifier U2, the voltage of the battery detection end of the power chip D1 is increased through the positive voltage, and the current passing through the power chip D1 is increased through increasing the output voltage of the output end of the power chip D1, so that the current passing through the power chip D1 and the current passing through the power chip D2 reach an equilibrium state.
The invention also provides a mobile terminal comprising the equalizing current circuit.
The invention discloses an equalizing current circuit, a charger and a mobile terminal, wherein the equalizing current circuit comprises: a current detecting resistor R1 and R2 connected with the input end, wherein the other end of the current detecting resistor R1 is connected with the negative electrode of the operational amplifier U2 and the input end of the power supply chip D1, the other end of the current detection resistor R is connected to the anode of the operational amplifier U2 and the input end of the power chip D2, the output end of the operational amplifier U2 is connected with the voltage feedback end of the power supply chip D1 through a resistor R3, the output terminals of the power supply chip D1 and the power supply chip D2 are respectively connected with the output terminal of the circuit, the voltage feedback end of the power supply chip D2 is connected with the output end through a resistor R7, the output end of the power supply chip D1 is grounded through a resistor R4 and a resistor R5, the voltage feedback end of the power chip D1 is grounded through the resistor R5, the output end of the operational amplifier U2 is grounded through the resistor R3 and the resistor R5, and the voltage feedback end of the power chip D2 is grounded through the resistor R6. The current balance output control scheme with simple structure and low cost is realized, so that the current output can be balanced in time when the power consumption of the equipment is large, and the output capacity and the heat dissipation performance of the current are balanced.
Drawings
The invention will be further described with reference to the accompanying drawings and examples, in which:
fig. 1 is a schematic diagram of a hardware structure of a mobile terminal according to the present invention;
fig. 2 is a communication network system architecture diagram provided by an embodiment of the present invention;
FIG. 3 is a first circuit diagram of a first embodiment of the equalizing current circuit of the present invention;
FIG. 4 is a second circuit diagram of a second embodiment of the balanced current circuit of the present invention;
FIG. 5 is a third circuit diagram of a third embodiment of the balanced current circuit of the present invention;
fig. 6 is a fourth circuit diagram of a fourth embodiment of the equalizing current circuit of the present invention.
Detailed Description
It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
In the following description, suffixes such as "module", "component", or "unit" used to denote elements are used only for facilitating the explanation of the present invention, and have no specific meaning in itself. Thus, "module", "component" or "unit" may be used mixedly.
The terminal may be implemented in various forms. For example, the terminal described in the present invention may include a mobile terminal such as a mobile phone, a tablet computer, a notebook computer, a palmtop computer, a Personal Digital Assistant (PDA), a Portable Media Player (PMP), a navigation device, a wearable device, a smart band, a pedometer, and the like, and a fixed terminal such as a Digital TV, a desktop computer, and the like.
The following description will be given by way of example of a mobile terminal, and it will be understood by those skilled in the art that the construction according to the embodiment of the present invention can be applied to a fixed type terminal, in addition to elements particularly used for mobile purposes.
Referring to fig. 1, which is a schematic diagram of a hardware structure of a mobile terminal for implementing various embodiments of the present invention, the mobile terminal 100 may include: RF (Radio Frequency) unit 101, WiFi module 102, audio output unit 103, a/V (audio/video) input unit 104, sensor 105, display unit 106, user input unit 107, interface unit 108, memory 109, processor 110, and power supply 111. Those skilled in the art will appreciate that the mobile terminal architecture shown in fig. 1 is not intended to be limiting of mobile terminals, which may include more or fewer components than those shown, or some components may be combined, or a different arrangement of components.
The following describes each component of the mobile terminal in detail with reference to fig. 1:
the radio frequency unit 101 may be configured to receive and transmit signals during information transmission and reception or during a call, and specifically, receive downlink information of a base station and then process the downlink information to the processor 110; in addition, the uplink data is transmitted to the base station. Typically, radio frequency unit 101 includes, but is not limited to, an antenna, at least one amplifier, a transceiver, a coupler, a low noise amplifier, a duplexer, and the like. In addition, the radio frequency unit 101 can also communicate with a network and other devices through wireless communication. The wireless communication may use any communication standard or protocol, including but not limited to GSM (Global System for Mobile communications), GPRS (General Packet Radio Service), CDMA2000(Code Division Multiple Access 2000), WCDMA (Wideband Code Division Multiple Access), TD-SCDMA (Time Division-Synchronous Code Division Multiple Access), FDD-LTE (Frequency Division duplex Long Term Evolution), and TDD-LTE (Time Division duplex Long Term Evolution).
WiFi belongs to short-distance wireless transmission technology, and the mobile terminal can help a user to receive and send e-mails, browse webpages, access streaming media and the like through the WiFi module 102, and provides wireless broadband internet access for the user. Although fig. 1 shows the WiFi module 102, it is understood that it does not belong to the essential constitution of the mobile terminal, and may be omitted entirely as needed within the scope not changing the essence of the invention.
The audio output unit 103 may convert audio data received by the radio frequency unit 101 or the WiFi module 102 or stored in the memory 109 into an audio signal and output as sound when the mobile terminal 100 is in a call signal reception mode, a call mode, a recording mode, a voice recognition mode, a broadcast reception mode, or the like. Also, the audio output unit 103 may also provide audio output related to a specific function performed by the mobile terminal 100 (e.g., a call signal reception sound, a message reception sound, etc.). The audio output unit 103 may include a speaker, a buzzer, and the like.
The a/V input unit 104 is used to receive audio or video signals. The a/V input Unit 104 may include a Graphics Processing Unit (GPU) 1041 and a microphone 1042, the Graphics processor 1041 Processing image data of still pictures or video obtained by an image capturing device (e.g., a camera) in a video capturing mode or an image capturing mode. The processed image frames may be displayed on the display unit 106. The image frames processed by the graphic processor 1041 may be stored in the memory 109 (or other storage medium) or transmitted via the radio frequency unit 101 or the WiFi module 102. The microphone 1042 may receive sounds (audio data) via the microphone 1042 in a phone call mode, a recording mode, a voice recognition mode, or the like, and may be capable of processing such sounds into audio data. The processed audio (voice) data may be converted into a format output transmittable to a mobile communication base station via the radio frequency unit 101 in case of a phone call mode. The microphone 1042 may implement various types of noise cancellation (or suppression) algorithms to cancel (or suppress) noise or interference generated in the course of receiving and transmitting audio signals.
The mobile terminal 100 also includes at least one sensor 105, such as a light sensor, a motion sensor, and other sensors. Specifically, the light sensor includes an ambient light sensor that can adjust the brightness of the display panel 1061 according to the brightness of ambient light, and a proximity sensor that can turn off the display panel 1061 and/or a backlight when the mobile terminal 100 is moved to the ear. As one of the motion sensors, the accelerometer sensor can detect the magnitude of acceleration in each direction (generally, three axes), can detect the magnitude and direction of gravity when stationary, and can be used for applications of recognizing the posture of a mobile phone (such as horizontal and vertical screen switching, related games, magnetometer posture calibration), vibration recognition related functions (such as pedometer and tapping), and the like; as for other sensors such as a fingerprint sensor, a pressure sensor, an iris sensor, a molecular sensor, a gyroscope, a barometer, a hygrometer, a thermometer, and an infrared sensor, which can be configured on the mobile phone, further description is omitted here.
The display unit 106 is used to display information input by a user or information provided to the user. The Display unit 106 may include a Display panel 1061, and the Display panel 1061 may be configured in the form of a Liquid Crystal Display (LCD), an Organic Light-Emitting Diode (OLED), or the like.
The user input unit 107 may be used to receive input numeric or character information and generate key signal inputs related to user settings and function control of the mobile terminal. Specifically, the user input unit 107 may include a touch panel 1071 and other input devices 1072. The touch panel 1071, also referred to as a touch screen, may collect a touch operation performed by a user on or near the touch panel 1071 (e.g., an operation performed by the user on or near the touch panel 1071 using a finger, a stylus, or any other suitable object or accessory), and drive a corresponding connection device according to a predetermined program. The touch panel 1071 may include two parts of a touch detection device and a touch controller. The touch detection device detects the touch direction of a user, detects a signal brought by touch operation and transmits the signal to the touch controller; the touch controller receives touch information from the touch sensing device, converts the touch information into touch point coordinates, sends the touch point coordinates to the processor 110, and can receive and execute commands sent by the processor 110. In addition, the touch panel 1071 may be implemented in various types, such as a resistive type, a capacitive type, an infrared ray, and a surface acoustic wave. In addition to the touch panel 1071, the user input unit 107 may include other input devices 1072. In particular, other input devices 1072 may include, but are not limited to, one or more of a physical keyboard, function keys (e.g., volume control keys, switch keys, etc.), a trackball, a mouse, a joystick, and the like, and are not limited to these specific examples.
Further, the touch panel 1071 may cover the display panel 1061, and when the touch panel 1071 detects a touch operation thereon or nearby, the touch panel 1071 transmits the touch operation to the processor 110 to determine the type of the touch event, and then the processor 110 provides a corresponding visual output on the display panel 1061 according to the type of the touch event. Although the touch panel 1071 and the display panel 1061 are shown in fig. 1 as two separate components to implement the input and output functions of the mobile terminal, in some embodiments, the touch panel 1071 and the display panel 1061 may be integrated to implement the input and output functions of the mobile terminal, and is not limited herein.
The interface unit 108 serves as an interface through which at least one external device is connected to the mobile terminal 100. For example, the external device may include a wired or wireless headset port, an external power supply (or battery charger) port, a wired or wireless data port, a memory card port, a port for connecting a device having an identification module, an audio input/output (I/O) port, a video I/O port, an earphone port, and the like. The interface unit 108 may be used to receive input (e.g., data information, power, etc.) from external devices and transmit the received input to one or more elements within the mobile terminal 100 or may be used to transmit data between the mobile terminal 100 and external devices.
The memory 109 may be used to store software programs as well as various data. The memory 109 may mainly include a storage program area and a storage data area, wherein the storage program area may store an operating system, an application program required by at least one function (such as a sound playing function, an image playing function, etc.), and the like; the storage data area may store data (such as audio data, a phonebook, etc.) created according to the use of the cellular phone, and the like. Further, the memory 109 may include high speed random access memory, and may also include non-volatile memory, such as at least one magnetic disk storage device, flash memory device, or other volatile solid state storage device.
The processor 110 is a control center of the mobile terminal, connects various parts of the entire mobile terminal using various interfaces and lines, and performs various functions of the mobile terminal and processes data by operating or executing software programs and/or modules stored in the memory 109 and calling data stored in the memory 109, thereby performing overall monitoring of the mobile terminal. Processor 110 may include one or more processing units; preferably, the processor 110 may integrate an application processor, which mainly handles operating systems, user interfaces, application programs, etc., and a modem processor, which mainly handles wireless communications. It will be appreciated that the modem processor described above may not be integrated into the processor 110.
The mobile terminal 100 may further include a power supply 111 (e.g., a battery) for supplying power to various components, and preferably, the power supply 111 may be logically connected to the processor 110 via a power management system, so as to manage charging, discharging, and power consumption management functions via the power management system.
Although not shown in fig. 1, the mobile terminal 100 may further include a bluetooth module or the like, which is not described in detail herein.
In order to facilitate understanding of the embodiments of the present invention, a communication network system on which the mobile terminal of the present invention is based is described below.
Referring to fig. 2, fig. 2 is an architecture diagram of a communication Network system according to an embodiment of the present invention, where the communication Network system is an LTE system of a universal mobile telecommunications technology, and the LTE system includes a UE (User Equipment) 201, an E-UTRAN (Evolved UMTS Terrestrial Radio Access Network) 202, an EPC (Evolved Packet Core) 203, and an IP service 204 of an operator, which are in communication connection in sequence.
Specifically, the UE201 may be the terminal 100 described above, and is not described herein again.
The E-UTRAN202 includes eNodeB2021 and other eNodeBs 2022, among others. Among them, the eNodeB2021 may be connected with other eNodeB2022 through backhaul (e.g., X2 interface), the eNodeB2021 is connected to the EPC203, and the eNodeB2021 may provide the UE201 access to the EPC 203.
The EPC203 may include an MME (Mobility Management Entity) 2031, an HSS (Home Subscriber Server) 2032, other MMEs 2033, an SGW (Serving gateway) 2034, a PGW (PDN gateway) 2035, and a PCRF (Policy and Charging Rules Function) 2036, and the like. The MME2031 is a control node that handles signaling between the UE201 and the EPC203, and provides bearer and connection management. HSS2032 is used to provide registers to manage functions such as home location register (not shown) and holds subscriber specific information about service characteristics, data rates, etc. All user data may be sent through SGW2034, PGW2035 may provide IP address assignment for UE201 and other functions, and PCRF2036 is a policy and charging control policy decision point for traffic data flow and IP bearer resources, which selects and provides available policy and charging control decisions for a policy and charging enforcement function (not shown).
The IP services 204 may include the internet, intranets, IMS (IP Multimedia Subsystem), or other IP services, among others.
Although the LTE system is described as an example, it should be understood by those skilled in the art that the present invention is not limited to the LTE system, but may also be applied to other wireless communication systems, such as GSM, CDMA2000, WCDMA, TD-SCDMA, and future new network systems.
Based on the above mobile terminal hardware structure and communication network system, the present invention provides various embodiments of the method.
Example one
Fig. 3 is a first circuit diagram of a first embodiment of the equalizing current circuit of the present invention. The present embodiment proposes an equalizing current circuit, which includes: a current detecting resistor R1 and R2 connected with the input end, wherein the other end of the current detecting resistor R1 is connected with the negative electrode of the operational amplifier U2 and the input end of the power supply chip D1, the other end of the current detection resistor R is connected to the anode of the operational amplifier U2 and the input end of the power chip D2, the output end of the operational amplifier U2 is connected with the voltage feedback end of the power supply chip D1 through a resistor R3, the output terminals of the power supply chip D1 and the power supply chip D2 are respectively connected with the output terminal of the circuit, the voltage feedback end of the power supply chip D2 is connected with the output end through a resistor R7, the output end of the power supply chip D1 is grounded through a resistor R4 and a resistor R5, the voltage feedback end of the power chip D1 is grounded through the resistor R5, the output end of the operational amplifier U2 is grounded through the resistor R3 and the resistor R5, and the voltage feedback end of the power chip D2 is grounded through the resistor R6.
Alternatively, in the present embodiment, when the current passing through the power chip D1 is greater than the current of the power chip D2, the voltage of the negative electrode of the operational amplifier U2 is less than the voltage of the positive electrode of the operational amplifier U2.
Optionally, in this embodiment, a high voltage is output through the output terminal of the operational amplifier U2, and the voltage of the voltage feedback terminal of the power chip D1 is increased by the high voltage.
Alternatively, in this embodiment, by reducing the output voltage of the output terminal of the power chip D1, the current passing through the power chip D1 is reduced, so that the current passing through the power chip D1 and the current passing through the power chip D2 reach an equilibrium state.
Alternatively, in the present embodiment, when the current passing through the power chip D2 is greater than the current of the power chip D1, the voltage of the negative electrode of the operational amplifier U2 is greater than the voltage of the positive electrode of the operational amplifier U2.
Optionally, in this embodiment, a low voltage is output through the output terminal of the operational amplifier U2, and the voltage of the voltage feedback terminal of the power chip D1 is reduced through the low voltage.
Alternatively, in this embodiment, by increasing the output voltage of the output terminal of the power chip D1, the current passing through the power chip D1 is increased, so that the current passing through the power chip D1 and the current passing through the power chip D2 reach an equilibrium state.
Optionally, in the present embodiment, the input voltage range of the equalizing current is between several volts and several hundred volts, and the input voltage range depends on the input voltage requirements of the operational amplifier U2, the power chip D1, and the power chip D2. In this embodiment, the resistance ranges of the resistor R1 and the resistor R2 are between 0.01 ohm and 1 ohm, alternatively, if the power chip D1 and the power chip D2 are low dropout linear regulators, the resistance ranges of the resistor R1 and the resistor R2 may be expanded appropriately, and if the power chip D1 and the power chip D2 are dc converters or other charging chips, the resistance ranges of the resistor R1 and the resistor R2 may be reduced appropriately. Optionally, in this embodiment, the smaller the resistance values of the resistor R1 and the resistor R2 are, the lower the current detection accuracy is, and at the same time, the lower the consumed power consumption is, whereas, the larger the resistance values of the resistor R1 and the resistor R2 are, the higher the current detection accuracy is, and at the same time, the larger the consumed power is, so in this embodiment, a larger-sized low dropout linear regulator may be selected. Optionally, in this embodiment, the resistor R4, the resistor R5, the resistor R6, and the resistor R7 are determined according to the characteristics of the low dropout linear regulator and the output voltage, and the resistances of the resistor R4, the resistor R5, the resistor R6, and the resistor R7 range from several hundred ohms to several tens of kiloohms, and optionally, the resistor R3 may adaptively select the resistance from several kiloohms to several hundreds of kiloohms according to the values of the resistor R4 and the resistor R5 and the debugging result.
The embodiment has the beneficial effects that by providing the equalizing current circuit, the circuit comprises: a current detecting resistor R1 and R2 connected with the input end, wherein the other end of the current detecting resistor R1 is connected with the negative electrode of the operational amplifier U2 and the input end of the power supply chip D1, the other end of the current detection resistor R is connected to the anode of the operational amplifier U2 and the input end of the power chip D2, the output end of the operational amplifier U2 is connected with the voltage feedback end of the power supply chip D1 through a resistor R3, the output terminals of the power supply chip D1 and the power supply chip D2 are respectively connected with the output terminal of the circuit, the voltage feedback end of the power supply chip D2 is connected with the output end through a resistor R7, the output end of the power supply chip D1 is grounded through a resistor R4 and a resistor R5, the voltage feedback end of the power chip D1 is grounded through the resistor R5, the output end of the operational amplifier U2 is grounded through the resistor R3 and the resistor R5, and the voltage feedback end of the power chip D2 is grounded through the resistor R6. The current balance output control scheme with simple structure and low cost is realized, so that the current output can be balanced in time when the power consumption of the equipment is large, and the output capacity and the heat dissipation performance of the current are balanced.
Example two
Fig. 4 is a second circuit diagram of a second embodiment of the equalizing current circuit of the present invention. Based on the above embodiments, in the present embodiment, the operational amplifier U2 employs the LM324AD, and the power supply chip D1 and the power supply chip D2 employ the LM 317H. Specifically, LM324AD is a low cost operational amplifier with true differential inputs, wherein the amplifier can operate with supply voltages as low as 3.0V or as high as 32V, a common mode input maximum (VCC-1.5) V, a common mode output voltage maximum (VCC-1.5) V, a gain bandwidth of 1.2MHz, an input offset voltage of LM324A of 2mV (typical value) to 3mV (maximum), an input offset current of LM324A of 2nA (typical value) to 30nA (maximum), an input offset current of LM324A of-15 nA (typical value) to-100 nA (maximum), and a common mode rejection ratio of LM324A of 65dB (typical value) to-80 dB (maximum).
Optionally, in this embodiment, LM317H is an adjustable 3-terminal positive voltage regulator capable of providing more than 1.5 amps of current in the output voltage range 1.2 volts to 37 volts, the maximum input-output voltage difference: 40VDC, minimum input-output voltage difference: 3 VDC.
Alternatively, in this embodiment, as shown in fig. 4, since the LM324AD is not a rail-to-rail input/output (rail-to-rail input/output, that is, full power supply amplitude output) operational amplifier, it is necessary to add a resistor R8, a resistor R9, a resistor R10, and a resistor R11 to adjust the input voltage of the operational amplifier to a proper range on the basis of the first embodiment, and in addition, the resistor R8, the resistor R9, the resistor R10, and the resistor R11 may also be used to adjust the ratio of the currents of the two power supplies. For example, the circuit inputs 12V, outputs 3.3V and outputs about 2.5A of maximum current. Optionally, in this embodiment, the LM324AD power supply also uses 12V, and according to the relevant applicable situation of the LM317H, the resistances of the resistor R5 and the resistor R6 are selected to be 1K ohm, the resistances of the resistor R4 and the resistor R7 are selected to be 600 ohm, so that the output voltage can be ensured to be about 3.3V, and the resistance R3 is selected to be 15K ohm, so that the current distribution accuracy of the balanced current of this embodiment can reach within 100 mA.
EXAMPLE III
Fig. 5 is a third circuit diagram of a third embodiment of the equalizing current circuit of the present invention. Based on the above embodiments, in this embodiment, in consideration of differences between the charging chip and the battery-to-charging-chip wiring, which may cause inconsistent current output by the charging chip to the battery, thereby causing inconsistent heat generation and affecting the current output capability of the whole power supply, the current output capability of the power supply can be controlled by introducing two current detection resistors R1, R2 and the operational amplifier U2 in this embodiment, namely, by controlling the current output capability of the power supply chip D1 and the power supply chip D2 (that is, the charging chip). Specifically, this embodiment provides a charger, which includes an equalizing current circuit, where the circuit includes: the current detection circuit comprises current detection resistors R1 and R2 connected with input ends, wherein the other end of the current detection resistor R1 is connected to the anode of an operational amplifier U2 and the input end of a power chip D1, the other end of the current detection resistor R is connected to the cathode of the operational amplifier U2 and the input end of the power chip D2, the output end of the operational amplifier U2 is connected with the battery detection end of the power chip D1 through a resistor R3, the output ends of the power chip D1 and the power chip D2 are respectively connected with the charging battery end of the circuit, the battery detection end of the power chip D2 is connected with the charging battery end, the battery detection end of the power chip D1 is connected with the charging battery end through a resistor R4, and the battery detection end of the power chip D1 is grounded through a resistor R5.
Alternatively, when the current passing through the power chip D1 is greater than the current passing through the power chip D2, the voltage of the positive electrode of the operational amplifier U2 is less than the voltage of the negative electrode of the operational amplifier U2, a negative voltage is output through the output terminal of the operational amplifier U2, the voltage of the battery detection terminal of the power chip D1 is reduced through the negative voltage, and the current passing through the power chip D1 is reduced through the reduction of the output voltage of the output terminal of the power chip D1, so that the current passing through the power chip D1 and the current passing through the power chip D2 reach an equilibrium state;
when the current passing through the power chip D2 is greater than the current passing through the power chip D1, the positive voltage of the operational amplifier U2 is greater than the negative voltage of the operational amplifier U2, a positive voltage is output through the output end of the operational amplifier U2, the voltage of the battery detection end of the power chip D1 is increased through the positive voltage, and the current passing through the power chip D1 is increased through increasing the output voltage of the output end of the power chip D1, so that the current passing through the power chip D1 and the current passing through the power chip D2 reach an equilibrium state.
The embodiment has the advantages that, through a charger, the charger comprises an equalizing current circuit, and the circuit comprises: the current detection circuit comprises current detection resistors R1 and R2 connected with input ends, wherein the other end of the current detection resistor R1 is connected to the anode of an operational amplifier U2 and the input end of a power chip D1, the other end of the current detection resistor R is connected to the cathode of the operational amplifier U2 and the input end of the power chip D2, the output end of the operational amplifier U2 is connected with the battery detection end of the power chip D1 through a resistor R3, the output ends of the power chip D1 and the power chip D2 are respectively connected with the charging battery end of the circuit, the battery detection end of the power chip D2 is connected with the charging battery end, the battery detection end of the power chip D1 is connected with the charging battery end through a resistor R4, and the battery detection end of the power chip D1 is grounded through a resistor R5. The current balance output control scheme with simple structure and low cost is realized, so that the current output can be balanced in time when the power consumption of the equipment is large, and the output capacity and the heat dissipation performance of the current are balanced.
Example four
Fig. 6 is a fourth circuit diagram of a fourth embodiment of the equalizing current circuit of the present invention. Based on the above embodiments, in the present embodiment, the power chip D1 and the power chip D2 adopt a PM7250B charging chip, support a QC4.0 charging protocol, maximum 12V input, maximum 4A charging, support differential input battery current detection and voltage detection. The operational amplifier adopts an LM324 circuit, wherein VCC adopts VBUS voltage, and can support 5V, 9V and 12V chargers. The circuit operation principle of this embodiment is as described in the above embodiments, and is not described herein again, and similarly, this embodiment may also implement a current balance output control scheme with a simple structure and low cost, so that current output can be balanced in time when the power consumption of the device is large, and the output capability and the heat dissipation performance of the current are balanced.
EXAMPLE five
The invention also provides a mobile terminal comprising the equalizing current circuit.
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The above-mentioned serial numbers of the embodiments of the present invention are merely for description and do not represent the merits of the embodiments.
Through the above description of the embodiments, those skilled in the art will clearly understand that the method of the above embodiments can be implemented by software plus a necessary general hardware platform, and certainly can also be implemented by hardware, but in many cases, the former is a better implementation manner. Based on such understanding, the technical solutions of the present invention may be embodied in the form of a software product, which is stored in a storage medium (such as ROM/RAM, magnetic disk, optical disk) and includes instructions for enabling a terminal (such as a mobile phone, a computer, a server, an air conditioner, or a network device) to execute the method according to the embodiments of the present invention.
While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (10)
1. A balanced current circuit, the circuit comprising: a current detecting resistor R1 and R2 connected with the input end, wherein the other end of the current detecting resistor R1 is connected with the negative electrode of the operational amplifier U2 and the input end of the power supply chip D1, the other end of the current detection resistor R is connected to the anode of the operational amplifier U2 and the input end of the power chip D2, the output end of the operational amplifier U2 is connected with the voltage feedback end of the power supply chip D1 through a resistor R3, the output terminals of the power supply chip D1 and the power supply chip D2 are respectively connected with the output terminal of the circuit, the voltage feedback end of the power supply chip D2 is connected with the output end through a resistor R7, the output end of the power supply chip D1 is grounded through a resistor R4 and a resistor R5, the voltage feedback end of the power chip D1 is grounded through the resistor R5, the output end of the operational amplifier U2 is grounded through the resistor R3 and the resistor R5, and the voltage feedback end of the power chip D2 is grounded through the resistor R6.
2. The balanced current circuit according to claim 1, wherein when the current through the power chip D1 is greater than the current through the power chip D2, the voltage of the negative pole of the operational amplifier U2 is less than the voltage of the positive pole of the operational amplifier U2.
3. The equalizing current circuit of claim 2, wherein a high voltage is output through the output terminal of the operational amplifier U2, and the voltage of the voltage feedback terminal of the power chip D1 is increased by the high voltage.
4. The balanced current circuit according to claim 3, characterized in that the current through the power chip D1 is reduced by reducing the output voltage of the output terminal of the power chip D1, so that the current through the power chip D1 and the current through the power chip D2 reach a balanced state.
5. The balanced current circuit according to claim 1, wherein when the current through the power chip D2 is greater than the current of the power chip D1, the voltage of the negative pole of the operational amplifier U2 is greater than the voltage of the positive pole of the operational amplifier U2.
6. The equalizing current circuit of claim 5, wherein a low voltage is output through the output terminal of the operational amplifier U2, and the voltage of the voltage feedback terminal of the power chip D1 is reduced by the low voltage.
7. The balanced current circuit as claimed in claim 6, wherein the current through the power chip D1 is increased by increasing the output voltage of the output terminal of the power chip D1, so that the current through the power chip D1 and the current through the power chip D2 reach a balanced state.
8. A charger, said charger comprising a balanced current circuit, said circuit comprising: the current detection circuit comprises current detection resistors R1 and R2 connected with input ends, wherein the other end of the current detection resistor R1 is connected to the anode of an operational amplifier U2 and the input end of a power chip D1, the other end of the current detection resistor R is connected to the cathode of the operational amplifier U2 and the input end of the power chip D2, the output end of the operational amplifier U2 is connected with the battery detection end of the power chip D1 through a resistor R3, the output ends of the power chip D1 and the power chip D2 are respectively connected with the charging battery end of the circuit, the battery detection end of the power chip D2 is connected with the charging battery end, the battery detection end of the power chip D1 is connected with the charging battery end through a resistor R4, and the battery detection end of the power chip D1 is grounded through a resistor R5.
9. The charger of claim 8, wherein when the current through the power chip D1 is larger than the current through the power chip D2, the voltage of the positive electrode of the operational amplifier U2 is smaller than the voltage of the negative electrode of the operational amplifier U2, a negative voltage is output through the output terminal of the operational amplifier U2, the voltage of the battery detection terminal of the power chip D1 is reduced by the negative voltage, and the current through the power chip D1 is reduced by reducing the output voltage of the output terminal of the power chip D1, so that the current through the power chip D1 and the current through the power chip D2 reach an equilibrium state;
when the current passing through the power chip D2 is greater than the current passing through the power chip D1, the positive voltage of the operational amplifier U2 is greater than the negative voltage of the operational amplifier U2, a positive voltage is output through the output end of the operational amplifier U2, the voltage of the battery detection end of the power chip D1 is increased through the positive voltage, and the current passing through the power chip D1 is increased through increasing the output voltage of the output end of the power chip D1, so that the current passing through the power chip D1 and the current passing through the power chip D2 reach an equilibrium state.
10. A mobile terminal characterized in that it comprises a balancing current circuit according to any one of claims 1 to 7.
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| CN202011040099.XA CN112202159A (en) | 2020-09-28 | 2020-09-28 | Balanced current circuit, charger and mobile terminal |
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| CN202011040099.XA CN112202159A (en) | 2020-09-28 | 2020-09-28 | Balanced current circuit, charger and mobile terminal |
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