CN112201189B - Potential shift circuit and display device having the same - Google Patents
Potential shift circuit and display device having the same Download PDFInfo
- Publication number
- CN112201189B CN112201189B CN202010947323.7A CN202010947323A CN112201189B CN 112201189 B CN112201189 B CN 112201189B CN 202010947323 A CN202010947323 A CN 202010947323A CN 112201189 B CN112201189 B CN 112201189B
- Authority
- CN
- China
- Prior art keywords
- voltage
- transistor
- shielding
- circuit
- shielding transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 239000000758 substrate Substances 0.000 claims abstract description 29
- 238000000034 method Methods 0.000 claims description 12
- 238000010586 diagram Methods 0.000 description 6
- 230000007704 transition Effects 0.000 description 5
- 230000007423 decrease Effects 0.000 description 4
- 238000006243 chemical reaction Methods 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
A potential shift circuit and a display device comprise a differential input circuit, a current limiting circuit, a latch circuit and a voltage shielding circuit. The voltage shielding circuit includes first to fourth shielding transistors. The first shielding transistor and the second shielding transistor are connected in series between the differential input circuit and the second output terminal, and the third shielding transistor and the fourth shielding transistor are connected in series between the differential input circuit and the first output terminal. Gates of the first and third shield transistors receive a first voltage, and gates of the second and fourth shield transistors receive a second voltage that is less than the first voltage. The substrates of the first and third shield transistors receive a third voltage and the substrates of the second and fourth shield transistors receive a fourth voltage greater than the third voltage.
Description
Technical Field
The present invention relates to a potential shift circuit and a display device having the same.
Background
A typical display includes a display panel and a display driving circuit for driving the display panel to display an image. The driving circuit provided in the non-display region generally has a potential shift circuit. The potential translation circuit is used for converting a signal in a low voltage domain into a signal in a high voltage domain or converting a signal in a high voltage domain into a signal in a low voltage domain so as to realize signal transmission in different voltage domains. The potential translation circuit comprises a differential input circuit, a latch circuit, a current limiting circuit and a voltage shielding circuit. The differential input circuit includes a forward input and a reverse input. The latch circuit includes a forward output and a reverse output. The current limiting circuit is used for limiting the current flowing through the transistor. In a single-stage to full positive voltage potential translation circuit formed by half-process components, a potential shielding circuit is used to protect the key points of the half-process components so as to protect the whole circuit in a correct operation voltage range. Typically, the shield voltage is set near the medium voltage, and the substrate voltage of the transistors in the potential shield circuit will also be near the medium voltage. However, the closer the shielding voltage is to the medium voltage, the slower the transition speed of the potential shift circuit, and when the shielding voltage is to be made to be medium voltage in order to increase the transition speed of the potential shift circuit, the shielding point between the potential shielding circuit and the differential input circuit will cause the problem of substrate leakage of the shielding transistor, so how to consider the transition speed and prevent the leakage of the shielding transistor is a technical problem to be solved.
Disclosure of Invention
In view of the foregoing, it is necessary to provide a potential shift circuit and a display device having the same, which are aimed at solving the technical problems of considering the transition speed and preventing the leakage of the shielding transistor in the prior art.
A potential shift circuit for converting a signal of a low voltage domain into a signal of a high voltage domain; the potential shift circuit includes:
a differential input circuit having a first input transistor and a second input transistor;
The latch circuit is provided with a first output end and a second output end;
The current limiting circuit is electrically connected with the bolt lock circuit; the current limiting circuit is used for limiting the current flowing through the latch circuit;
The voltage shielding circuit is electrically connected between the differential input circuit and the latch circuit; the voltage shielding circuit comprises a first shielding transistor, a second shielding transistor, a third shielding transistor and a fourth shielding transistor; the first shielding transistor and the second shielding transistor are connected in series between the first input transistor and the second output terminal, and a source electrode of the first shielding transistor is electrically connected with a source electrode of the second shielding transistor; the third shielding transistor and the fourth shielding transistor are connected in series between the second input transistor and the first output end, and a source electrode of the third shielding transistor is electrically connected with a source electrode of the fourth shielding transistor; the grid electrode of the first shielding transistor and the grid electrode of the third shielding transistor receive a first voltage, and the grid electrode of the second shielding transistor and the grid electrode of the fourth shielding transistor receive a second voltage; the substrate of the first shielding transistor and the substrate of the third shielding transistor receive a third voltage, and the substrate of the second shielding transistor and the substrate of the fourth shielding transistor receive a fourth voltage; wherein the first voltage is greater than the second voltage; the fourth voltage is greater than the third voltage.
A display device has a potential shift circuit; the potential translation circuit converts a signal in a low voltage domain into a signal in a high voltage domain; the potential shift circuit includes:
a differential input circuit having a first input transistor and a second input transistor;
The latch circuit is provided with a first output end and a second output end;
The current limiting circuit receives the driving voltage and is electrically connected with the latch circuit; the current limiting circuit is used for limiting the current flowing through the latch circuit;
The voltage shielding circuit is electrically connected between the differential input circuit and the latch circuit; the voltage shielding circuit comprises a first shielding transistor, a second shielding transistor, a third shielding transistor and a fourth shielding transistor; the first shielding transistor and the second shielding transistor are connected in series between the first input transistor and the second output terminal, and a source electrode of the first shielding transistor is electrically connected with a source electrode of the second shielding transistor; the third shielding transistor and the fourth shielding transistor are connected in series between the second input transistor and the first output end, and a source electrode of the third shielding transistor is electrically connected with a source electrode of the fourth shielding transistor; the grid electrode of the first shielding transistor and the grid electrode of the third shielding transistor receive a first voltage, and the grid electrode of the second shielding transistor and the grid electrode of the fourth shielding transistor receive a second voltage; the substrate of the first shielding transistor and the substrate of the third shielding transistor receive a third voltage, and the substrate of the second shielding transistor and the substrate of the fourth shielding transistor receive a fourth voltage; wherein the first voltage is greater than the second voltage; the fourth voltage is greater than the third voltage.
According to the potential translation circuit and the display device with the potential translation circuit with the structure, the third voltage is provided for the substrates of the first shielding transistor and the third shielding transistor, the fourth voltage is provided for the substrates of the second shielding transistor and the fourth shielding transistor, and the fourth voltage is set to be larger than the third voltage so as to increase the range of reverse bias of the PN junction surface of the transistor substrate in the potential shielding circuit, so that the voltage difference between the first voltage and the second voltage of the potential shielding circuit can be designed to be large, and the conversion speed of the potential translation circuit can be improved.
Drawings
FIG. 1 is a schematic block diagram of a display device according to a preferred embodiment.
Fig. 2 is a schematic diagram of a module of the potential shift circuit in fig. 1.
Fig. 3 is an equivalent circuit diagram of the potential shift circuit in fig. 2.
Description of the main reference signs
Display device 100
Scan driving circuit 110
Data driving circuit 120
Timing controller 130
Display area 101
Non-display area 103
Scanning line S 1-Sn
Data line D 1-Dm
Pixel unit 20
Potential translation circuit 200
Differential input circuit 201
Latch circuit 203
Current limiting circuit 205
Voltage shielding circuit 207
First input terminal IN
A second input terminal INB
First input transistor M1
Second input transistor M2
First output transistor M3
Second output transistor M4
A first output terminal OUT
A second output end OUTB
First transistor M5
Second transistor M6
First shielding transistor M7
Second shielding transistor M8
Third shielded transistor M9
Fourth shielded transistor M10
First node N1
Second node N2
Third node N3
Fourth node N4
First voltage V1
Second voltage V2
Third voltage V3
Fourth voltage V4
Supply voltage AVDD
Bias voltage VP
The invention will be further described in the following detailed description in conjunction with the above-described figures.
Detailed Description
In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.
The terms "first," "second," and "third" in the description of the invention and in the above figures, etc. are used for distinguishing between different objects and not for describing a particular sequential order. Furthermore, the term "include" and any variations thereof is intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or modules is not limited to only those steps or modules but may include other steps or modules not expressly listed or inherent to such process, method, article, or apparatus.
The following describes specific embodiments of a potential shift circuit and a display device having the potential shift circuit according to the present invention with reference to the drawings. Referring to fig. 1, fig. 1 is an equivalent block diagram of a display device 100 according to an embodiment of the invention. The display device 100 defines a display area 101 and a non-display area 103 arranged around the display area 101. The display area 101 includes a plurality of scan lines S 1-Sn and a plurality of data lines D 1-Dm. Wherein n, m is a positive integer. The plurality of scan lines S 1-Sn extend along the first direction X and are disposed parallel to each other, the plurality of data lines D 1-Dm extend along the second direction Y and are disposed parallel to each other, and the plurality of scan lines S 1-Sn and the plurality of data lines D 1-Dm are insulated from each other and are disposed in a grid-crossing manner, so as to define a plurality of pixel units 20 arranged in a matrix.
The display device 100 includes a scan driving circuit 110, a data driving circuit 120, and a timing controller 130. Each row of pixel units 20 is electrically connected to the scan driving circuit 110 through a scan line S n, and each column of pixel units 20 is electrically connected to the data driving circuit 120 through a data line D m. The timing controller 130 is electrically connected to the scan driving circuit 110 and the data driving circuit 120, respectively. The timing controller 130 generates a plurality of synchronous control signals to the scan driving circuit 110 and the data driving circuit 120. The plurality of synchronization control signals may include periodic synchronization control signals and aperiodic synchronization control signals. The plurality of synchronization control signals include a vertical synchronization signal (Vertical synchronization, vsync), a horizontal synchronization signal (Horizontal synchronization, hsync), and a Data Enable signal (Data Enable, DE). In the present embodiment, the timing controller 130 supplies a clock signal to the scan driving circuit 110. The scan driving circuit 110 provides scan signals to the plurality of scan lines S 1-Sn to scan the pixel units 20. The data driving circuit 120 is used for providing image signals to the plurality of data lines D 1-Dm to display images. The image signal is a digital signal, and is composed of a low level (e.g., logic 0) and a high level (e.g., logic 1). In the present embodiment, the scan driving circuit 110 is disposed above the display region, and the data driving circuit 120 is disposed on the left side of the display region.
The data driving circuit 120 includes a potential shift circuit 200. Fig. 2 is a block diagram illustrating a potential shift circuit 200 according to the present invention. The potential shift circuit 200 is used to convert an image signal in a low voltage domain into a conversion signal in a high voltage domain and supply the conversion signal to the pixel unit 20. In at least one embodiment of the present invention, the potential translation circuit 200 is applied to a circuit structure formed by half-process components. In at least one embodiment of the present invention, the supply voltage AVDD in the high voltage domain may be greater than the supply voltage in the low voltage domain. The high voltage domain may include a low level, an intermediate level, and a high level. Wherein the intermediate level is between the low level and the high level. In at least one embodiment of the invention, in the high voltage domain, the low level may be 0 volts, the intermediate level may be 6 volts, and the high level may be 12 volts; in the low voltage domain, the low level may be 0 volts and the high level may be 1.8 volts. In other embodiments, the intermediate level in the high voltage domain may also be set to other values as desired. The potential shift circuit 200 includes a differential input circuit 201, a latch circuit 203, a current limiting circuit 205, and a voltage shielding circuit 207.
Please refer to fig. 3, which is an equivalent circuit diagram of the potential shift circuit 200.
The differential input circuit 201 has a first input terminal IN and a second input terminal INB. Wherein the input signal is provided to the first input terminal IN and is inverted by an inverter (not shown) and provided to the second input terminal INB. The differential input circuit 201 includes a first input transistor M1 and a second input transistor M2. The gate of the first input transistor M1 is electrically connected to the first input terminal IN, the gate of the first input transistor M1 is electrically connected to the second input terminal INB, the source of the first input transistor M1 and the source of the second input transistor M2 are simultaneously electrically connected to the ground terminal, and the drain of the first input transistor M1 and the drain of the second input transistor M2 are respectively electrically connected to the voltage shielding circuit 207. In at least one embodiment of the present invention, the first input transistor M1 and the second input transistor M2 may be NMOS transistors.
The latch circuit 203 has a first output terminal OUT and a second output terminal OUTB. The latch circuit 203 includes a first output transistor M3 and a second output transistor M4. The gate of the first output transistor M3 is electrically connected to the first output terminal OUT, the gate of the second output transistor M4 is electrically connected to the second output terminal OUTB, the source of the first output transistor M3 and the source of the second output transistor M4 are simultaneously electrically connected to the current limiting circuit 205, the drain of the first output transistor M3 is electrically connected to the second output terminal OUTB, and the drain of the second output transistor M4 is electrically connected to the first output terminal OUT. In at least one embodiment of the present invention, the first and second output transistors M3 and M4 may be PMOS transistors.
The current limiting circuit 205 is electrically connected to the latch circuit 203. The current limiting circuit 205 is configured to limit a current flowing through the first output transistor M3 and the second output transistor M4. The current limiting circuit 205 includes a first transistor M5 and a second transistor M6. The gate of the first transistor M5 and the gate of the second transistor M6 receive the bias voltage VP. The source of the first transistor M5 and the source of the second transistor M6 receive the power supply voltage AVDD, respectively. The drain of the first transistor M5 is electrically connected to the source of the first output transistor M3, and the drain of the second transistor M6 is electrically connected to the source of the second output transistor M4. In at least one embodiment of the present invention, the first transistor M5 and the second transistor M6 may be PMOS transistors.
The voltage shielding circuit 207 is electrically connected between the differential input circuit 201 and the latch circuit 203. The voltage shielding circuit 207 is configured to control the switching speed of the potential shift circuit 200 according to the first voltage V1 and the second voltage V2. The voltage shielding circuit 207 includes a first shielding transistor M7, a second shielding transistor M8, a third shielding transistor M9, and a fourth shielding transistor M10. The first and second shielding transistors M7 and M8 are connected in series between the drain of the first input transistor M1 and the second output terminal OUTB, and the third and fourth shielding transistors M9 and M10 are connected in series between the drain of the second input transistor M2 and the first output terminal OUT. The gates of the first and third shielding transistors M7 and M9 receive the first voltage V1, and the gates of the second and fourth shielding transistors M8 and M10 receive the second voltage V2. Wherein the first voltage V1 is greater than the second voltage V2. The source of the first shielding transistor M7 is electrically connected to the source of the second shielding transistor M8 through a third node N3, and the source of the third shielding transistor M9 is electrically connected to the source of the fourth shielding transistor M10 through a fourth node N4. The drain of the first shielding transistor M7 is electrically connected to the second output terminal OUTB. The drain of the second shielding transistor M8 is electrically connected to the drain of the first input transistor M1 through the first node N1. The drain of the third shielding transistor M9 is electrically connected to the first output terminal OUT. The drain of the fourth shielding transistor M10 is electrically connected to the drain of the second input transistor M2 through the second node N2. The substrate of the first shielding transistor M7 and the substrate of the third shielding transistor M9 receive the third voltage V3, and the substrate of the second shielding transistor M8 and the substrate of the fourth shielding transistor M10 receive the fourth voltage V4. Wherein the third voltage V3 is smaller than the fourth voltage V4. In at least one embodiment of the present invention, the first and third shielding transistors M7 and M9 may be NMOS transistors, and the second and fourth shielding transistors M8 and M10 may be PMOS transistors. In at least one embodiment of the present invention, one of the third voltage V3 and the fourth voltage V4 may be set to an intermediate level. When the third voltage V3 is at the intermediate level, the fourth voltage V4 is greater than the intermediate level. When the fourth voltage V4 is at the intermediate level, the third voltage V3 needs to be less than the intermediate level.
In the process of switching the input signal of the low voltage domain from the low level to the high level, the first input transistor M1 is turned on gradually, and the second input transistor M2 is turned off gradually. The voltage of the third node N3 gradually decreases until the potential of the third node N3 is the sum of the second voltage V2 and the threshold voltage VTH of the second shielding transistor M8. At the same time, the voltage of the second output terminal OUTB of the latch 203 also gradually decreases to a voltage close to the third node N3. Therefore, the voltage of the fourth node N4 rises stepwise until the potential of the fourth node is the difference between the first voltage V1 and the threshold voltage VTH of the third shielding transistor M9. In the process of switching the input signal of the low voltage domain from the high level to the low level, the second input transistor M2 is turned on gradually, and the first input transistor M1 is turned off gradually. The voltage of the fourth node N4 gradually decreases until the potential of the fourth node is the sum of the second voltage V2 and the threshold voltage VTH of the fourth shielding transistor M10. Meanwhile, the voltage of the first output terminal OUT in the latch circuit 203 also gradually decreases to a voltage close to the fourth node N4, and thus, the voltage of the third node N3 gradually increases until the potential of the third node N3 is the difference between the first voltage V1 and the threshold voltage VTH of the first shielding transistor M7. In order to increase the switching speed, the first voltage V1 and the second voltage V2 are usually far from the middle level, and the PN junctions between the substrates of the first to fourth shielding transistors M7 to M10 are controlled to be reverse biased by designing a suitable third voltage V3 and a fourth voltage V4 to prevent the first to fourth shielding transistors M7 to M10 from leaking. Meanwhile, after the first voltage V1 and the second voltage V2 are designed according to the required state transition speed, the first voltage V1 and the fourth voltage V4 are equal, the second voltage V2 and the third voltage V3 are identical, and then the voltages of the third node N3 and the fourth node N4 can be between the first voltage V1 and the second voltage V2. Meanwhile, since the first voltage V1 is equal to the fourth voltage V4 and the second voltage V2 is set to be the same as the third voltage V3, the PN junctions between the substrates of the first to fourth shielding transistors M7 to M10 are also controlled to be reverse biased, so that the first to fourth shielding transistors M7 to M10 can be prevented from leaking. The method can simultaneously consider the state rotation speed and the electric leakage.
It will be appreciated by persons skilled in the art that the above embodiments have been provided for the purpose of illustrating the invention and are not to be construed as limiting the invention, and that suitable modifications and variations of the above embodiments are within the scope of the invention as claimed.
Claims (10)
1. A potential shift circuit for converting a signal of a low voltage domain into a signal of a high voltage domain; the method is characterized in that: the potential shift circuit includes:
a differential input circuit having a first input transistor and a second input transistor;
The latch circuit is provided with a first output end and a second output end;
the current limiting circuit receives the driving voltage and is electrically connected with the latch circuit; the current limiting circuit is used for limiting the current flowing through the latch circuit;
The voltage shielding circuit is electrically connected between the differential input circuit and the latch circuit; the voltage shielding circuit comprises a first shielding transistor, a second shielding transistor, a third shielding transistor and a fourth shielding transistor; the first shielding transistor and the second shielding transistor are connected in series between the first input transistor and the second output terminal, and a source electrode of the first shielding transistor is electrically connected with a source electrode of the second shielding transistor; the third shielding transistor and the fourth shielding transistor are connected in series between the second input transistor and the first output end, and a source electrode of the third shielding transistor is electrically connected with a source electrode of the fourth shielding transistor; the grid electrode of the first shielding transistor and the grid electrode of the third shielding transistor receive a first voltage, and the grid electrode of the second shielding transistor and the grid electrode of the fourth shielding transistor receive a second voltage; the substrate of the first shielding transistor and the substrate of the third shielding transistor receive a third voltage, and the substrate of the second shielding transistor and the substrate of the fourth shielding transistor receive a fourth voltage; wherein the first voltage is greater than the second voltage; the fourth voltage is greater than the third voltage.
2. The potential shift circuit according to claim 1, wherein: the high voltage domain includes a low level, a middle level, and a high level; the intermediate level is greater than the low level and less than the high level; the third voltage is at an intermediate level.
3. The potential shift circuit according to claim 1, wherein: the high voltage domain includes a low level, a middle level, and a high level; the intermediate level is greater than the low level and less than the high level; the fourth voltage is at an intermediate level.
4. The potential shift circuit according to claim 1, wherein: the first voltage is equal to the fourth voltage, and the second voltage is equal to the third voltage.
5. The potential shift circuit according to claim 1, wherein: the first shielding transistor and the third shielding transistor are N-type transistors, and the second shielding transistor and the fourth shielding transistor are P-type transistors.
6. The potential shift circuit according to claim 1, wherein: the grid electrode of the first input transistor is electrically connected with the first input end, the source electrode of the first input transistor receives a grounding voltage, and the drain electrode of the first input transistor is electrically connected with the drain electrode of the second shielding transistor; the grid electrode of the second input transistor is electrically connected with the second input end, the source electrode of the second input transistor receives the grounding voltage, and the drain electrode of the second input transistor is electrically connected with the drain electrode of the fourth shielding transistor.
7. A display device with potential shift circuit includes a potential shift circuit; the potential translation circuit is used for converting a signal in a low voltage domain into a signal in a high voltage domain; the method is characterized in that: the potential shift circuit includes:
a differential input circuit having a first input transistor and a second input transistor;
The latch circuit is provided with a first output end and a second output end;
the current limiting circuit receives the driving voltage and is electrically connected with the latch circuit; the current limiting circuit is used for limiting the current flowing through the latch circuit;
The voltage shielding circuit is electrically connected between the differential input circuit and the latch circuit; the voltage shielding circuit comprises a first shielding transistor, a second shielding transistor, a third shielding transistor and a fourth shielding transistor; the first shielding transistor and the second shielding transistor are connected in series between the first input transistor and the second output terminal, and a source electrode of the first shielding transistor is electrically connected with a source electrode of the second shielding transistor; the third shielding transistor and the fourth shielding transistor are connected in series between the second input transistor and the first output end, and a source electrode of the third shielding transistor is electrically connected with a source electrode of the fourth shielding transistor; the grid electrode of the first shielding transistor and the grid electrode of the third shielding transistor receive a first voltage, and the grid electrode of the second shielding transistor and the grid electrode of the fourth shielding transistor receive a second voltage; the substrate of the first shielding transistor and the substrate of the third shielding transistor receive a third voltage, and the substrate of the second shielding transistor and the substrate of the fourth shielding transistor receive a fourth voltage; wherein the first voltage is greater than the second voltage; the fourth voltage is greater than the third voltage.
8. The display device according to claim 7, wherein: the high voltage domain includes a low level, a middle level, and a high level; the intermediate level is greater than the low level and less than the high level; the third voltage is at an intermediate level.
9. The display device according to claim 7, wherein: the high voltage domain includes a low level, a middle level, and a high level; the intermediate level is greater than the low level and less than the high level; the fourth voltage is at an intermediate level.
10. The display device according to claim 7, wherein: the first voltage is equal to the fourth voltage, and the second voltage is equal to the third voltage.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010947323.7A CN112201189B (en) | 2020-09-10 | 2020-09-10 | Potential shift circuit and display device having the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202010947323.7A CN112201189B (en) | 2020-09-10 | 2020-09-10 | Potential shift circuit and display device having the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112201189A CN112201189A (en) | 2021-01-08 |
| CN112201189B true CN112201189B (en) | 2024-05-24 |
Family
ID=74015194
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202010947323.7A Active CN112201189B (en) | 2020-09-10 | 2020-09-10 | Potential shift circuit and display device having the same |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN112201189B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114637420B (en) * | 2022-03-01 | 2024-09-03 | 武汉华星光电半导体显示技术有限公司 | Touch display panel and mobile terminal |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5821800A (en) * | 1997-02-11 | 1998-10-13 | Advanced Micro Devices, Inc. | High-voltage CMOS level shifter |
| CN101388662A (en) * | 2007-09-11 | 2009-03-18 | 联发科技股份有限公司 | level conversion circuit |
| JP2013150219A (en) * | 2012-01-20 | 2013-08-01 | Toppan Printing Co Ltd | Semiconductor integrated circuit |
| US9859894B1 (en) * | 2017-01-26 | 2018-01-02 | Elite Semiconductor Memory Technology Inc. | Level shifting circuit and integrated circuit |
| CN207835431U (en) * | 2017-09-22 | 2018-09-07 | DB HiTek 株式会社 | Level translator and source electrode driver, gate drivers and display device including the level translator |
| CN110098830A (en) * | 2019-05-17 | 2019-08-06 | 上海艾为电子技术股份有限公司 | A kind of the substrate switching circuit and level shifting circuit of transistor |
| CN111600594A (en) * | 2020-05-22 | 2020-08-28 | 赛卓电子科技（上海）有限公司 | Level conversion circuit with anti-protection |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3695967B2 (en) * | 1998-11-16 | 2005-09-14 | 株式会社東芝 | Semiconductor integrated circuit device |
-
2020
- 2020-09-10 CN CN202010947323.7A patent/CN112201189B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5821800A (en) * | 1997-02-11 | 1998-10-13 | Advanced Micro Devices, Inc. | High-voltage CMOS level shifter |
| CN101388662A (en) * | 2007-09-11 | 2009-03-18 | 联发科技股份有限公司 | level conversion circuit |
| JP2013150219A (en) * | 2012-01-20 | 2013-08-01 | Toppan Printing Co Ltd | Semiconductor integrated circuit |
| US9859894B1 (en) * | 2017-01-26 | 2018-01-02 | Elite Semiconductor Memory Technology Inc. | Level shifting circuit and integrated circuit |
| CN207835431U (en) * | 2017-09-22 | 2018-09-07 | DB HiTek 株式会社 | Level translator and source electrode driver, gate drivers and display device including the level translator |
| CN110098830A (en) * | 2019-05-17 | 2019-08-06 | 上海艾为电子技术股份有限公司 | A kind of the substrate switching circuit and level shifting circuit of transistor |
| CN111600594A (en) * | 2020-05-22 | 2020-08-28 | 赛卓电子科技（上海）有限公司 | Level conversion circuit with anti-protection |
Also Published As
| Publication number | Publication date |
|---|---|
| CN112201189A (en) | 2021-01-08 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10255847B2 (en) | Level shift circuit and display driver | |
| US11769455B2 (en) | Shift register unit set, gate driving circuit and display apparatus | |
| US20220319393A1 (en) | Shift Register, Gate Driving Circuit, Display Apparatus and Driving Method | |
| CN112073048B (en) | Level shift circuit | |
| CN111971737B (en) | Shift register unit, grid driving circuit, display device and driving method | |
| CN1523670B (en) | Semiconductor device and driving method of the same | |
| US11735086B2 (en) | Shift register, gate driving circuit, display apparatus and driving method | |
| KR100807092B1 (en) | Digital to analog converter and converting method for driving a flat display panel | |
| CN102201192B (en) | Level shift circuit, data driver and display device | |
| CN111937067B (en) | Shifting register unit, driving method, grid driving circuit and display device | |
| CN109166542B (en) | Shifting register unit, driving method, grid driving circuit and display device | |
| CN105185338A (en) | CMOS GOA (Gate Driver on Array) circuit | |
| CN112201189B (en) | Potential shift circuit and display device having the same | |
| US8471803B2 (en) | Level shifters including circuitry for reducing short circuits and display devices using the same | |
| CN114974163B (en) | Scanning driving circuit, array substrate and display panel | |
| CN114639430B (en) | Shift register unit, gate drive circuit and display panel | |
| CN106251815B (en) | Level shifter and source driver integrated circuit | |
| US11049469B2 (en) | Data signal line drive circuit and liquid crystal display device provided with same | |
| KR101452645B1 (en) | Decoding and scan driver | |
| CN104485063A (en) | Display panel and drive circuit thereof | |
| CN213152036U (en) | Level shift circuit and integrated circuit | |
| CN111540328B (en) | GOA circuit and display panel | |
| CN100403389C (en) | Latch, latch driving method and flat panel display device | |
| US20210090520A1 (en) | Operational amplifier circuit and display apparatus with operational amplifier circuit for avoiding voltage overshoot | |
| US10847101B2 (en) | Gate driver circuit and liquid crystal panel using same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |