CN112198423A - Test excitation generating unit in FPGA chip - Google Patents
Test excitation generating unit in FPGA chip Download PDFInfo
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- CN112198423A CN112198423A CN202011021891.0A CN202011021891A CN112198423A CN 112198423 A CN112198423 A CN 112198423A CN 202011021891 A CN202011021891 A CN 202011021891A CN 112198423 A CN112198423 A CN 112198423A
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- 238000012360 testing method Methods 0.000 title claims abstract description 46
- 239000013598 vector Substances 0.000 claims description 36
- 238000010586 diagram Methods 0.000 description 12
- 238000011161 development Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 3
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3177—Testing of logic operation, e.g. by logic analysers
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
- G01R1/28—Provision in measuring instruments for reference values, e.g. standard voltage, standard waveform
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/31718—Logistic aspects, e.g. binning, selection, sorting of devices under test, tester/handler interaction networks, Test management software, e.g. software for test statistics or test evaluation, yield analysis
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention discloses a test excitation generating unit in an FPGA chip. The test stimulus generating unit includes: the excitation generating module is used for generating an excitation signal or a control signal required by the tested user logic unit; and the PCIE module is used for enabling the excitation generation module and the logic analysis module to be communicated with an external computer. The test excitation generating unit can generate an excitation signal or a control signal required by the tested user logic unit in the FPGA chip, so that the excitation signal or the control signal can be efficiently and flexibly provided for the tested user logic unit.
Description
Technical Field
The invention relates to the field of FPGA (field programmable gate array) chips, in particular to a test excitation generating unit in an FPGA chip.
Background
With the continuous development of scientific technologies such as 5G communication, Internet of things, artificial intelligence, big data, cloud computing and the like, the technological industry has higher and higher requirements on computing capability, computing delay and programmability of integrated circuits. FPGAs are widely used in various emerging technologies due to their high parallelism, low latency, high flexibility, high performance power consumption ratio, and other characteristics.
However, due to the reasons that the technical ecology of the FPGA is not sound, the development difficulty is high, the development period is long, and the like, the FPGA brings great challenges to developers. Among these challenges, the problem of the user functional logic testing link inside the FPGA is particularly prominent. Especially in a cloud FPGA system and a remote FPGA system, the user function logic test is more difficult and serious. One of the most difficult problems to solve is the problem of logic test stimulus signal generation.
In the prior art, the FPGA test stimulus signal is often provided through an external physical input interface. The signal quality and data correctness of the physical interface are limited by the external hardware environment, so that a great deal of time and energy must be consumed to test whether the hardware external interface communication is correct before testing the FPGA user function logic. In addition, the input excitation signal provided by the external interface is often limited by the external device and cannot be generated arbitrarily according to the requirements of logic function designers and logic testers. Furthermore, in the testing process of the FPGA logic circuit, in order to facilitate problem location, special control is often required for some special signals. In the traditional method, only a small number of signals can be controlled in a VIO (virtual IO) mode, and only external computer user software can be used for controlling, so that the control delay is large, and the control requirements of a large number of signals or low-delay signals cannot be met.
Therefore, a solution for providing excitation signals for testing the functional logic of the FPGA user with high efficiency and flexibility is needed.
Disclosure of Invention
In view of the above, the present invention provides a test excitation generating unit in an FPGA chip, which can solve the above technical problems.
The technical scheme of the invention is as follows:
a test stimulus generation unit within an FPGA chip, comprising:
the excitation generating module is used for generating an excitation signal or a control signal required by the tested user logic unit;
and the PCIE module is used for enabling the excitation generation module to communicate with an external computer.
According to a preferred embodiment of the present invention, the excitation generating module includes a vector buffer, a cycle schedule, an edge schedule, an instruction executing unit, and an interface timing generating unit, the vector buffer stores a plurality of vectors, each vector includes a cycle schedule address, an edge schedule address, edge data, a microinstruction, and a microinstruction parameter, and the instruction executing unit is configured to generate the excitation signal or the control signal at the interface timing generating unit by reading and executing the vector buffer, the cycle schedule, and the edge schedule.
According to a preferred embodiment of the present invention, the interface timing generation unit is configured to input the stimulus signal to the input signal interface of the user logic unit under test, or input the control signal to the test signal interface of the user logic unit under test.
According to a preferred embodiment of the present invention, the PCIE module includes a PCIE IP interface, a DMA write interface, and a DMA read interface, where the PCIE IP interface is configured to communicate with an external computer, the DMA write interface is configured to write vector data and configuration data into the excitation generating module, and the DMA read interface is configured to read data from the excitation generating module.
According to a preferred embodiment of the invention, the configuration data comprises cycle time data for writing a cycle schedule and edge time data for writing an edge schedule.
An FPGA chip includes a tested user logic unit and the above described test stimulus generation unit.
According to a preferred embodiment of the present invention, the FPGA chip further includes a selection circuit and a configuration register, and the selection circuit is configured to select an external physical interface or an excitation signal generated by the excitation generation module as an input of the tested user logic unit under the control of the configuration register.
According to a preferred embodiment of the present invention, the PCIE module further includes a register interface, configured to set the configuration register.
According to the technical scheme, the test excitation generating unit can generate the excitation signal and the control signal required by the tested user logic unit in the FPGA chip, so that the excitation signal or the control signal can be efficiently and flexibly provided for the tested user logic unit.
Drawings
The disclosure of the present invention will become more readily understood with reference to the accompanying drawings. It is easily understood by those skilled in the art that these drawings are only for illustrating the technical solutions of the present invention and are not intended to limit the scope of the present invention. In the figure:
FIG. 1 is a schematic diagram of an internal structure of an FPGA chip in the prior art;
FIG. 2 is a schematic diagram of the internal structure of an FGPA chip according to an embodiment of the invention;
FIG. 3 is a diagram illustrating vector data in a vector cache according to an embodiment of the invention;
FIG. 4 is a schematic diagram of a cycle schedule according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of an edge schedule according to an embodiment of the present invention;
fig. 6 is a schematic diagram of the excitation signal generation principle according to the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in detail with reference to the accompanying drawings and specific embodiments.
Fig. 1 is a schematic diagram of an internal structure of an FPGA chip in the prior art. As shown in fig. 1, a user function logic unit is included within the FPGA chip. The user function logic unit comprises an input signal interface, a test signal interface and an output signal interface. The input signal interface and the output signal interface are respectively connected with a physical interface of the FPGA chip. The test signal interface is connected with an external computer through a JTAG interface. In the prior art, an excitation signal for testing a user function logic unit is input from the outside of an FPGA chip through a physical interface. The output signal generated by the user function logic unit is output to an external analysis device through a physical interface for analysis. Some control signals for simple testing may be generated by VIO (virtual pin) technology provided by EDA vendors, input to the test signal interface through the JTAG interface. As described in the background section, the prior art is not efficient and flexible in providing test stimulus signals to user functional logic.
Fig. 2 is a schematic diagram of the internal structure of an FGPA chip according to an embodiment of the present invention. As shown in fig. 2, the FPGA chip includes a test stimulus generating unit and a tested user logic unit. The test stimulus generating unit includes: the device comprises an excitation generation module and a PCIE module. The excitation generating module is used for generating an excitation signal and a control signal required by the tested user logic unit. The PCIE module is used as an interface for the test excitation generating unit to communicate with an external computer. The tested user logic unit comprises an input signal interface, a test signal interface and an output signal interface. The FPGA chip may also include selection circuitry and configuration registers. The selection circuit is configured to select the excitation signal generated by the external physical interface or the excitation generation module as the input signal of the tested user logic unit under the control of the configuration register.
The test excitation generating unit is positioned in the FPGA chip, so that an excitation signal or a control signal can be efficiently and flexibly provided for the tested user logic unit from the interior of the FPGA chip, and the excitation signal or the control signal does not need to be introduced from the exterior of the FPGA chip, thereby avoiding the problem caused by the introduction of the excitation signal or the control signal from the exterior in the prior art.
According to an embodiment of the present invention, an excitation generation module includes a vector cache, a cycle schedule, an edge schedule, an instruction execution unit, and an interface timing generation unit. The vector cache stores a plurality of vectors, each vector including a cycle schedule address, an edge schedule address, edge data, a microinstruction, and microinstruction parameters. The instruction execution unit generates the excitation signal and the control signal at the interface timing generation unit by reading the vector cache, the cycle schedule, and the edge schedule. The interface sequential unit can be directly connected with an input signal interface of the tested user logic unit, and also can be connected with the input signal interface of the tested user logic unit through a selection circuit so as to provide an excitation signal for the tested user logic unit. In addition, the interface timing sequence generating unit is also connected with a test signal interface of the tested user logic unit and used for providing a control signal for the tested user logic unit. The output signal of the tested user logic unit can be output to an external device or a special instrument through a physical interface so as to analyze the logic correctness of the output signal. In addition, the internal signal output by the test signal interface of the logic unit of the tested user can be captured by a logic analyzer tool (such as a Chipscope tool of Xilinx company or a SignalTap tool of Intel company) provided by the FPGA original factory for analysis.
According to the embodiment of the invention, the PCIE module comprises a PCIE IP interface, a DMA writing interface and a DMA reading interface. The PCIE IP interface is used to communicate with an external computer. The DMA write interface is used to write vector data and configuration data to the stimulus generation module. The DMA read interface is used to read data from the stimulus generation module. The configuration data includes cycle time data for writing a cycle schedule and edge time data for writing an edge schedule. The PCIE module may further include a register interface, configured to set the configuration register.
The structures of the FPGA chip and the test stimulus generating unit according to the embodiment of the present invention are described above. The manner in which the excitation signal or control signal is generated will be described in detail below in conjunction with fig. 3-6.
FIG. 3 is a diagram illustrating vector data in a vector cache according to an embodiment of the invention. As shown in fig. 3, a plurality of vectors for generating the excitation signals or the control signals are stored in the vector buffer. Each vector includes a cycle schedule address, an edge schedule address, edge data, microinstructions, and microinstruction parameters. Cycle time data may be obtained from the cycle schedule by the cycle schedule address. Edge time data can be obtained from the edge schedule by the edge schedule address. Microinstructions are used to control the order, number, rhythm, condition, etc. of vector execution. The micro instruction parameters are the execution parameters required to execute the micro instructions. The instruction execution unit may obtain the cycle time data, the edge data, the microinstruction, and the microinstruction parameter by reading the vector in the vector cache, execute the microinstruction, and generate the excitation signal or the control signal at the interface timing generation unit. Some commonly used micro instructions and corresponding instruction parameters according to embodiments of the present invention are listed in table 1. The generation of the excitation signal or the control signal can be controlled by means of the microinstructions.
TABLE 1
FIG. 4 is a schematic diagram of a cycle schedule according to an embodiment of the present invention. As shown in fig. 4, 256 waveform cycles are stored in the cycle schedule according to an embodiment of the present invention. One period in the periodic schedule can be specified as a period of the excitation signal or the control signal by a periodic schedule address in the vector.
FIG. 5 is a diagram of an edge schedule according to an embodiment of the present invention. As shown in fig. 5, 256 kinds of edge information are stored in the edge schedule according to the embodiment of the present invention, and each kind of edge information includes 8 kinds of edge timing information. One kind of edge information in the edge schedule can be specified as the edge information of the excitation signal or the control signal by the edge schedule address in the vector.
Fig. 6 is a schematic diagram of the excitation signal generation principle according to the present invention. As shown in fig. 6, the generation signal (i.e., the stimulus signal or the control signal) is defined by a period T (32 clock cycles), 8 edge timings (3 rd, 6 th, 8 th, 11 th, 17 th, 23 th, 28 th, and 31 th clock cycles), and 8 edge data (10010110) with reference to a clock signal. The period T may be obtained from the cycle schedule using the cycle schedule address in the vector. The 8 edge instants can be obtained from the edge schedule using the edge schedule addresses in the vector. The 8 edge data (i.e. the signal values at 8 edge instants) can be obtained from the vector. By combining the above information with the microinstruction and the microinstruction parameter, an excitation signal or a control signal can be generated at the interface timing generation unit.
When the excitation signal or the control signal needs to be changed, an external computer can be used to write a new vector into the vector cache through the DMA write interface in the PCIE module, so that the excitation generation module generates a new excitation signal and/or a new control signal according to the new vector. In addition, the user can also use the external computer to write new cycle time data and/or edge time data into the cycle time table and/or the edge time table through the DMA write interface in the PCIE module, so as to change the selectable cycle time and edge time.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents, improvements and the like made within the spirit and principle of the present invention should be included in the scope of the present invention.
Claims (8)
1. A test stimulus generation unit within an FPGA chip, comprising:
the excitation generating module is used for generating an excitation signal or a control signal required by the tested user logic unit;
and the PCIE module is used for enabling the excitation generation module to communicate with an external computer.
2. The test stimulus generation unit of claim 1, wherein the stimulus generation module comprises a vector cache, a cycle schedule, an edge schedule, an instruction execution unit, and an interface timing generation unit, the vector cache storing a plurality of vectors, each vector comprising a cycle schedule address, an edge schedule address, edge data, a microinstruction, and microinstruction parameters, the instruction execution unit configured to generate the stimulus signal or the control signal at the interface timing generation unit by reading and executing the vector cache, the cycle schedule, and the edge schedule.
3. The test stimulus generation unit of claim 2, wherein the interface timing generation unit is configured to input the stimulus signal to an input signal interface of the user logic unit under test or input the control signal to a test signal interface of the user logic unit under test.
4. The test excitation generating unit according to any one of claims 1 to 3, wherein the PCIE module includes a PCIEP interface, a DMA write interface, and a DMA read interface, the PCIEP interface is used for communicating with an external computer, the DMA write interface is used for writing vector data and configuration data into the excitation generating module, and the DMA read interface is used for reading data from the excitation generating module.
5. The test stimulus generation unit of claim 4, wherein the configuration data comprises cycle time data for writing a cycle schedule and edge time data for writing an edge schedule.
6. An FPGA chip comprising a user logic unit under test and a test stimulus generation unit according to any one of claims 1 to 5.
7. The FPGA chip of claim 6, further comprising a selection circuit and a configuration register, the selection circuit configured to select an external physical interface or an excitation signal generated by the excitation generation module as an input of the user logic unit under test under control of the configuration register.
8. The FPGA chip of claim 7, wherein said PCIE module further comprises a register interface for setting said configuration register.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113721136A (en) * | 2021-07-20 | 2021-11-30 | 天津津航计算技术研究所 | FPGA-based synchronous 422 interface test excitation implementation system and method |
| CN115078968A (en) * | 2022-06-15 | 2022-09-20 | 上海类比半导体技术有限公司 | Chip test circuit, self-test chip and chip test system |
| CN117289114A (en) * | 2023-10-10 | 2023-12-26 | 苏州异格技术有限公司 | Logic function test circuit and test method |
| CN119535072A (en) * | 2025-01-20 | 2025-02-28 | 杭州高坤电子科技有限公司 | Test method, system, terminal and storage medium based on microinstruction classification operation |
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