CN112188723B - A high-speed multi-layer planar circuit board - Google Patents
A high-speed multi-layer planar circuit board Download PDFInfo
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- CN112188723B CN112188723B CN201910602509.6A CN201910602509A CN112188723B CN 112188723 B CN112188723 B CN 112188723B CN 201910602509 A CN201910602509 A CN 201910602509A CN 112188723 B CN112188723 B CN 112188723B
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- 239000010410 layer Substances 0.000 claims abstract description 212
- 239000002344 surface layer Substances 0.000 claims abstract description 31
- 239000003990 capacitor Substances 0.000 claims description 26
- 238000003475 lamination Methods 0.000 claims description 9
- 239000002184 metal Substances 0.000 claims description 7
- 239000011358 absorbing material Substances 0.000 claims description 4
- 239000011888 foil Substances 0.000 claims description 4
- 230000005855 radiation Effects 0.000 abstract description 7
- 230000001629 suppression Effects 0.000 abstract description 7
- 238000001228 spectrum Methods 0.000 description 6
- 239000000758 substrate Substances 0.000 description 6
- 230000009286 beneficial effect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 230000005284 excitation Effects 0.000 description 2
- 230000005764 inhibitory process Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 101100498823 Caenorhabditis elegans ddr-2 gene Proteins 0.000 description 1
- 230000010485 coping Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005670 electromagnetic radiation Effects 0.000 description 1
- 230000002401 inhibitory effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 230000003595 spectral effect Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
- H05K1/0298—Multilayer circuits
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/115—Via connections; Lands around holes or via connections
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
本发明提供一种高速多层平面电路板，所述电路板包括至少一叠层单元，其中叠层单元包括接地层、电源层和混合层，电源层布置在接地层和混合层中间，混合层用于布置地线和信号线；每一所述叠层单元中设置有至少一与电路板垂直的电源过孔，每一电源过孔旁至少设置一与电源过孔平行的伴电源地孔；电源过孔和伴电源地孔均贯穿所述叠层单元，所述电源过孔和所述伴电源地孔的一端均延伸至距离电源层最近的电路板的表层；电源过孔与叠层单元中电源层连接，伴电源地孔分别与叠层单元中接地层、混合层以及延伸经过的接地层、混合层连接。通过本发明，解决了基频谐波及高次谐波抑制效果不好以及多芯片模块造成电源噪声板沿辐射的问题。
The present invention provides a high-speed multi-layer planar circuit board, the circuit board includes at least one stacking unit, wherein the stacking unit includes a ground layer, a power layer and a mixed layer, the power layer is arranged between the ground layer and the mixed layer, and the mixed layer is used to arrange ground wires and signal wires; each of the stacking units is provided with at least one power via perpendicular to the circuit board, and each power via is provided with at least one accompanying power ground hole parallel to the power via; the power via and the accompanying power ground hole both penetrate the stacking unit, and one end of the power via and the accompanying power ground hole both extend to the surface layer of the circuit board closest to the power layer; the power via is connected to the power layer in the stacking unit, and the accompanying power ground hole is respectively connected to the ground layer, the mixed layer in the stacking unit, and the ground layer and the mixed layer extending therethrough. Through the present invention, the problem of poor suppression of fundamental harmonics and higher harmonics and board edge radiation of power supply noise caused by multi-chip modules is solved.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a high-speed multilayer planar circuit board.
Background
The planar circuit board is a main carrier of components in electronic products, and modern electronic products with complex control communication and multimedia functions commonly use a high-speed main frequency processor and a high-speed digital bus, and the planar circuit board used as a carrier comprises a multilayer printed circuit board, a circuit substrate for packaging a large chip, a circuit substrate for a multi-chip module and the like.
Typically, the power, ground, and signals of these planar circuit boards are disposed on designated planar layers, respectively, and a plurality of metal planes of different properties and dielectric spacing stacks are ultimately bonded to the planar circuit boards. The different numbers of through holes pass through the plane layers to realize electrical connection. The multi-layer circuit board generally refers to 6 or more metal layers, has more routing impedance options, and has better wiring density, isolation and electromagnetic protection capability. Electrical devices such as ICs, crystal oscillators, SOC chips, decoupling capacitors, etc. are disposed on the surface of the planar circuit board.
The power plane, ground plane and dielectric interlayer may be equivalently planar waveguides having an electrical mode, i.e. an electrical resonance characteristic, related to their physical dimensions, dielectric parameters. When power supply noise current from an electric device, such as power supply ripple, simultaneous switching noise (Simultaneous Switching Noise, SSN) caused by a high-speed digital signal, and the like, is injected into a power supply plane from a surface layer through a via hole thereof through a ground plane, the noise current is excited into electromagnetic waves, and the excited frequency and intensity are related to the position of the via hole in the plane. When the electromagnetic waves finally reach the edge of the circuit board, the electromagnetic waves radiate outwards through an equivalent slot antenna at the edge of the board, so that far-field electromagnetic interference (EMI) radiation is caused. The EMI radiation frequency range and the upper intensity limit of various current applications are regulated by corresponding international/national/industry standards. Currently, the upper frequency limit specified by automotive EMI emissions (CISPR 25) is 2.5GHz. Future CISPR standards organization programs will raise this upper limit to 400GHz.
An example of a typical power supply noise disturbance and radiation superscript is DDR-SDRAM. The DDR-SDRAM has high clock frequency (DDR 2 main frequency is more than 400 MHz), the number of parallel bus wires such as clock/data/address is large, and the signal swing is large. The result is a considerable amount of clock fundamental and higher harmonic energy, which is a strong source of interference. Even if both clock and signal lines are disposed within the PCB, noise can still propagate through the power ground plane waveguide, causing interference with the surrounding power supply, signals, and causing significant EMI emissions. The best solution is to control the energy spectral density of the noise source, such as using a clock spread spectrum technique (Spread spectrum clocking, SSC). But when the main control chip of the system does not support DDR spread spectrum application, other measures must be adopted for coping. A common method of suppressing power ground noise in practice is to use a patch capacitor to decouple the power ground. Because of the lead inductance and the wiring inductance of the patch capacitor, the power ground noise below 100MHz can be well suppressed, and the suppression effect on DDR fundamental frequency and higher harmonic waves is not obvious.
Such as significant board edge emissions due to power supply noise of large chip packages and circuit substrates for multi-chip modules. An equivalent planar antenna formed by a poorly grounded metal cover and a ground plane easily radiates this noise energy.
Disclosure of Invention
The invention aims to solve the technical problems of providing a high-speed multilayer planar circuit board which is used for solving the problems of the prior system that a main control chip does not support spread spectrum application, and a chip capacitor has poor effects of inhibiting fundamental frequency harmonic waves and higher harmonic waves of strong interference signals such as clocks and the like, so that the power supply noise of a printed circuit board, a large-scale packaging substrate and a multi-chip module is radiated along the board edge.
The invention provides a high-speed multilayer planar circuit board, which comprises at least one lamination unit, wherein:
The laminated unit comprises a grounding layer, a power supply layer and a mixed layer, wherein the power supply layer is arranged between the grounding layer and the mixed layer, and the mixed layer is used for arranging a ground wire and a signal wire;
at least one power supply via hole perpendicular to the circuit board is arranged in each lamination unit, and at least one power supply ground hole parallel to the power supply via hole is arranged beside each power supply via hole;
The power via hole and the power ground hole penetrate through the laminated unit, and one ends of the power via hole and the power ground hole extend to the surface layer of the circuit board nearest to the power layer;
the power via hole is connected with the power layer in the laminated unit, and the power ground hole is connected with the grounding layer and the mixed layer in the laminated unit and the extended grounding layer and the mixed layer respectively.
Further, a plurality of power supply ground holes are arranged beside the power supply via holes, and the distances from the power supply ground holes to the power supply via holes are equal.
Further, a high-frequency element connected to the power supply layer in the laminated unit is provided on the surface layer of the circuit board closest to the ground layer in the laminated unit.
Further, the outer edge of the power supply layer wraps an annular fence ground hole, and the annular fence ground hole is arranged between a ground layer and a mixed layer of a laminated unit where the power supply layer is located.
Further, the outer edge of the circuit board is wrapped with a wave absorbing material or a grounded metal foil layer.
Further, the circuit board comprises two laminated units, the number of layers is an even number of more than eight, and all layers in the circuit board are arranged symmetrically up and down.
Further, the circuit board comprises two or more laminated units;
The power via hole and the power ground hole in each laminated unit are through holes, and the other ends of the power via hole and the power ground hole extend to the surface layer of the circuit board farthest from the power layer;
The power supply ground hole is connected with the extended ground layer and the mixed layer;
the high-frequency element and the surface-mounted high-frequency decoupling capacitor which are connected with the power supply layer in the laminated unit are arranged on the surface layer of the circuit board nearest to the grounding layer in the laminated unit.
Further, the circuit board comprises two or more laminated units;
the power via hole and the power ground hole in each laminated unit are blind holes, and the other end of the power via hole is cut off in the laminated unit.
Further, the high-frequency element and the surface-mounted decoupling capacitor connected with the power supply layer in each laminated unit are arranged on the surface layer of the circuit board nearest to the grounding layer in the laminated unit.
The implementation of the invention has the following beneficial effects:
According to the invention, the laminated unit based on the ground layer, the power layer and the mixed layer is arranged in the circuit board, the power via hole and the power ground hole are arranged in the circuit board, electromagnetic wave intensity caused by excitation of the power via hole is restrained from noise source, omnidirectional noise suppression is realized, and the problems that the main control chip of the traditional system does not support spread spectrum application, the chip capacitor has poor effects of suppressing fundamental frequency harmonic wave and higher harmonic wave of strong interference signals such as clocks and the like, and the board edge radiation of power noise of the printed circuit board, the large-scale package substrate and the multi-chip module is caused.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a block diagram of a laminated unit provided in an embodiment of the present invention.
Fig. 2 is a top view of a power layer of a power ground hole assembly according to an embodiment of the present invention.
Fig. 3 is a cross-sectional view of a circuit board provided by an embodiment of the present invention, in which the outer edge of the circuit board is wrapped with a wave absorbing material or a grounded metal foil layer.
Fig. 4 is a block diagram of a high-speed multi-layer planar circuit board according to an embodiment of the present invention.
Fig. 5 is a block diagram of a high-speed multi-layer planar circuit board according to an embodiment of the present invention.
Fig. 6 is a graph of a simulation result of the combined isolation of power and ground holes according to an embodiment of the present invention.
Detailed Description
This patent sets up the stromatolite unit for the circuit board, and every stromatolite unit includes ground plane, power layer and mixed layer, sets up power via hole and companion's power via hole for the stromatolite unit, sets up high frequency component and high frequency decoupling capacitance at the top layer of the circuit board that is nearer to the power layer, and this concrete implementation is further explained below with reference to drawing and example.
Embodiments of the high-speed multilayer planar circuit board provided by the present invention will be described in detail below.
As shown in fig. 1, an embodiment of the present invention provides a laminated unit including a ground layer 11, a power supply layer 12, and a mixed layer 13, the power supply layer 12 being disposed between the ground layer 11 and the mixed layer 13, the mixed layer 13 being for disposing ground lines and signal lines.
It should be noted that, the mixed layer 13 is also used for arranging ground wires and can be regarded as a ground layer, the upper and lower ground layers wrap the power layer 12 to minimize electromagnetic wave emission and propagation in the vertical direction, and simultaneously, a double-part planar decoupling capacitor is formed between the power layers, thereby playing the role of reducing noise.
The laminated unit is provided with a power via hole 14 perpendicular to the high-speed multilayer planar circuit board, the power via hole 14 penetrates through the laminated unit and is connected with the power layer 12 in the laminated unit, a power ground hole 15 parallel to the power via hole 14 is arranged beside the power via hole 14, the power ground hole 15 penetrates through the laminated unit and is respectively connected with the ground layer 11 and the mixed layer 13 in the laminated unit, and in the embodiment, the connection of the power ground hole 15 and the mixed layer 13 is actually that the power ground hole 14 is connected with the ground part in the mixed layer 13.
The power via hole 14 is provided with a power ground hole 15, and the power ground hole 15 is provided around the power via hole 14, and the distance between them is generally not more than 1/20 of the wavelength corresponding to the highest frequency of the target noise suppression. If the highest frequency of the target noise suppression is 3GHz (wavelength=100 mm), the corresponding inter-hole distance should not exceed 5mm.
As shown in fig. 2, the embodiment of the present invention provides a power layer of a power ground hole combination, and a combination 51, a combination 52 and a combination 53 of a power via hole 14 and a power ground hole 15 can be seen from a top view of the power layer, wherein the ratio of the power via hole 14 to the power ground hole 15 in the combination 51, the combination 52 and the combination 53 is 1:1, 1:2 and 1:3, respectively, so that it can be known that at least one power ground hole 15 is disposed beside each power via hole 14;
The electromagnetic wave intensity caused by the forward current of the power via hole 14 and the backward current of the power ground hole 15 is partially offset to reduce the electromagnetic wave emission in the horizontal direction, in addition, the power via hole 14 and the power ground hole 15 are combined to be equivalent to a wideband decoupling capacitor to inhibit the resonance mode of the combined position area, the closer the distance between the power via hole 14 and the power ground hole 15 is, the smaller the current loop area is, the smaller the equivalent loop inductance is, the stronger the inhibition capability is, and the distance between the same power via hole 14 and the plurality of power ground holes 15 arranged beside the same power via hole 14 is equal, so that the noise inhibition effect is better.
As shown in fig. 3, the embodiment of the present invention provides a circuit board, which includes a ground layer 11, a power layer 12, and a mixed layer 13, and the outer edge wraps a wave absorbing material 61 or a ground metal foil layer 61 for shielding electromagnetic interference.
As shown in fig. 4, the embodiment of the present invention provides a high-speed multi-layer planar circuit board, which has eight layers, including a first lamination unit, a second lamination unit, a signal layer 16, and a signal layer 26, and includes two lamination units;
The first laminated unit comprises a ground layer 11, a power layer 12 and a mixed layer 13, the second laminated unit comprises a ground layer 21, a power layer 22 and a mixed layer 23, the ground layer 11 and the ground layer 21 are symmetrical, the power layer 12 and the power layer 22 are symmetrical, the mixed layer 13 and the mixed layer 23 are symmetrical, the signal layer 16 and the signal layer 26 are symmetrical, and all layers in the circuit board are arranged up and down symmetrically.
It should be noted that all layers of the circuit board are symmetrically arranged, which is beneficial to reducing noise interference.
The power via hole 14 in the first laminated unit penetrates through the first laminated unit and is connected with the power layer 12 in the first laminated unit, one end of the power via hole 14 extends to the surface layer of the circuit board nearest to the power layer 12, namely the signal layer 16 in the embodiment, a power ground hole 15 is arranged beside the power via hole 14 in the first laminated unit, one end of the power ground hole 15 extends to the surface layer of the circuit board nearest to the power layer 12, namely the signal layer 16 in the embodiment, and is respectively connected with the grounding layer 11, the mixed layer 13 and the grounding layer and the mixed layer extending through the first laminated unit, but one end of the power ground hole 15 extends to the surface layer of the circuit board outside the first laminated unit and is free of the grounding layer and the mixed layer.
The power via hole 14 and the power ground hole 15 in the first laminated unit are through holes, and the other ends of the power via hole 14 and the power ground hole 15 extend to the surface layer of the circuit board farthest from the power layer 12, and in this embodiment, the surface layer of the circuit board farthest from the power layer 12 is the signal layer 26.
The power ground holes 15 are connected to the ground layer 21, the hybrid layer 23, which extend through, whereas the power vias 14 are not connected to the power layer 22, since different power layers provide different voltages or different frequencies of power, which are individual and common to ground.
The high-frequency element 17 and the surface-mounted high-frequency decoupling capacitor 18 connected to the power supply layer 12 in the first laminated unit are provided on the surface layer of the circuit board closest to the ground layer 11 in the first laminated unit, that is, the signal layer 16.
It should be noted that the circuit board has two surface layers, one on the uppermost and one on the lowermost, and in this embodiment, the surface layers of the circuit board are the signal layer 16 and the signal layer 26, and the high-frequency element 17 is disposed on the surface layer closest to the ground layer 11 of the laminated unit where the power layer 12 is connected, so as to make the via distance between the high-frequency element 17 and the surface-mounted high-frequency decoupling capacitor 18 and the power layer 12 as short as possible, because the shorter the via, the smaller the inductance, and the inductance prevents the high-frequency signal from flowing back. Therefore, high-frequency related devices such as high-frequency decoupling capacitors and the like are placed on the same surface for high-frequency noise sources, so that the high-frequency noise flows back more effectively.
The surface-mounted low-frequency decoupling capacitor 19 connected with the power supply layer 12 in the first laminated unit is arranged on the surface layer of the circuit board farthest from the ground layer 11 in the first laminated unit, namely the signal layer 26, and the low-frequency element and the surface-mounted low-frequency decoupling capacitor can be arranged on the surface layer of any circuit board and separated from the high-frequency element as far as possible for convenience of management.
It should be noted that, the circuit board may be provided with more than two laminated units, but it is necessary to place the laminated units in the middle of the circuit board, which may result in that the distance between the power board and the surface layer of the circuit board in the laminated units is too far, resulting in that the power supply is over Kong Guochang and the high-frequency noise is difficult to control.
It should be noted that the power layer 12 is filled with two patterns, which means that the same power layer may be composed of more than two power sources, including power sources with different voltages or power sources with different frequencies.
As shown in fig. 5, the embodiment of the present invention provides a high-speed multi-layer planar circuit board, which has ten layers, including a first lamination unit, a second lamination unit, a signal layer 16, a signal layer 26, a mixed layer 31, and a mixed layer 32, and includes two lamination units in total;
The first laminated unit comprises a ground layer 11, a power layer 12 and a mixed layer 13, the second laminated unit comprises a ground layer 21, a power layer 22 and a mixed layer 23, the ground layer 11 and the ground layer 21 are symmetrical, the power layer 12 and the power layer 22 are symmetrical, the mixed layer 13 and the mixed layer 23 are symmetrical, the signal layer 16 and the signal layer 26 are symmetrical, the mixed layer 31 and the mixed layer 32 are symmetrical, and all layers in the circuit board are arranged up and down symmetrically.
The two power vias 14 in the first laminated unit penetrate through the first laminated unit and are connected with the power layer 12 in the first laminated unit, one end of each power via 14 extends to the surface layer of the nearest circuit board of the power layer 12, namely the mixed layer 31 in the embodiment, a power ground hole 15 is arranged beside each power via 14 in the first laminated unit, one end of each power ground hole 15 extends to the surface layer of the nearest circuit board of the power layer 12, namely the mixed layer 31 in the embodiment, and is respectively connected with the ground layer 11, the mixed layer 13 and the mixed layer 31 extending out of the first laminated unit, if the power ground hole 15 extends through the ground layer, the connection is also needed, and one end of each power ground hole 15 extends without passing through the ground layer in the embodiment.
The power via hole 14 and the power ground hole 15 in the first laminated unit are blind holes, and the other end of the power via hole 14 is cut off from the first laminated unit and cannot extend to the second laminated unit, so that two power domains are isolated and formed, and noise is reduced.
The high-frequency element 17 and the surface-mounted high-frequency decoupling capacitor 18 connected with the power supply layer 12 in the first laminated unit are arranged on the surface layer of the circuit board nearest to the ground layer 11 in the first laminated unit, namely the mixed layer 31, the surface-mounted low-frequency decoupling capacitors 19 are arranged on the surface layer (the surface-mounted low-frequency decoupling capacitors 19 are not marked in fig. 5) of the circuit board nearest to the ground layer 11 in the laminated unit because the power supply domain is isolated, and in a word, the high-frequency element 17, the surface-mounted high-frequency decoupling capacitors 18 and the surface-mounted low-frequency decoupling capacitors 19 are arranged on the surface layer of the circuit board nearest to the ground layer 11 in the first laminated unit, and the surface-mounted decoupling capacitors comprise the surface-mounted high-frequency decoupling capacitors 17 and the surface-mounted low-frequency decoupling capacitors 18.
The high frequency element 27 connected to the power supply layer 22 in the second laminated unit is provided on the surface layer of the circuit board nearest to the ground layer 21 in the second laminated unit, that is, the mixed layer 32, and the surface mount decoupling capacitor connected to the power supply layer 22 is also provided on the mixed layer 32.
The outer edge of the power layer 12 wraps the annular fence ground hole 41 in the first laminated unit, the annular fence ground hole 41 is arranged between the ground layer 11 and the mixed layer 13 of the first laminated unit where the power layer 12 is located, the annular fence ground hole is also arranged between the ground layer 21 and the mixed layer 23 in the second laminated unit, and the purpose of the annular fence ground hole is to reduce the diffusion of electromagnetic radiation of the power layer in the horizontal direction.
As shown in fig. 6, the embodiment of the invention provides an interference curve under different combinations of power via holes and power ground holes, and in the same circuit board, the power injection position and the other power isolation degree of the common board are obtained through simulation, and as can be seen from the figure, the number of the power ground holes is increased when the power via holes are provided with the power ground holes, and the interference degree of the common board is gradually reduced;
Referring to fig. 6, it can be seen that the provision of the power via and the power ground via not only reduces the interference in one laminated unit, but also reduces the interference between a plurality of power panels.
The implementation of the invention has the following beneficial effects:
the invention sets a laminated unit based on a ground layer, a power layer and a mixed layer in a circuit board, sets a power via hole and a power ground hole in the circuit board, starts from a noise source, suppresses electromagnetic wave intensity caused by excitation of the power via hole, realizes omnidirectional noise suppression, further sets a high-frequency element and a surface mount decoupling element on the surface layer of the circuit board nearest to a power panel, sets annular ground hole fences and other means for each power panel to reduce electromagnetic interference in the vertical direction and the horizontal direction, and solves the problems of the radiation of the base frequency and the higher harmonic of strong interference signals such as clocks caused by the fact that a main control chip of the traditional system does not support spread spectrum application and the patch capacitance has poor harmonic suppression effect on the base frequency and the higher harmonic of the strong interference signals such as clocks, and the like, and solves the problem of the radiation of the power noise panel edges of the printed circuit board, a large-scale package substrate and a multi-chip module.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.
Claims (9)
1. A high-speed multilayer planar circuit board, said circuit board comprising at least one laminated unit, wherein:
The laminated unit comprises a grounding layer, a power supply layer and a mixed layer, wherein the power supply layer is arranged between the grounding layer and the mixed layer, and the mixed layer is used for arranging a ground wire and a signal wire;
at least one power supply via hole perpendicular to the circuit board is arranged in each lamination unit, and at least one power supply ground hole parallel to the power supply via hole is arranged beside each power supply via hole;
The power via hole and the power ground hole penetrate through the laminated unit, and one ends of the power via hole and the power ground hole extend to the surface layer of the circuit board nearest to the power layer;
The power via hole is connected with the power layer in the laminated unit, and the power ground hole is respectively connected with the grounding layer and the mixed layer in the laminated unit and the grounding layer and the mixed layer which extend through the power via hole;
The outer edge of the power supply layer wraps the annular fence ground hole, and the annular fence ground hole is arranged between the ground layer and the mixed layer of the laminated unit where the power supply layer is arranged.
2. The circuit board of claim 1, wherein a plurality of power ground vias are disposed adjacent to the power via, and wherein distances from the plurality of power ground vias to the power via are equal.
3. The circuit board of claim 1, wherein the high frequency element connected to the power supply layer in the laminated unit is disposed on a surface layer of the circuit board nearest to the ground layer in the laminated unit.
4. The circuit board of claim 1, wherein the circuit board outer edge is wrapped with a wave-absorbing material or a grounded metal foil layer.
5. The circuit board of any one of claims 1-4, wherein the circuit board comprises two stacked units and has an even number of layers of eight or more, and all layers in the circuit board are arranged symmetrically up and down.
6. The circuit board of claim 1, wherein the circuit board comprises two or more stacked units;
The power via hole and the power ground hole in each laminated unit are through holes, and the other ends of the power via hole and the power ground hole extend to the surface layer of the circuit board farthest from the power layer;
The power supply ground hole is connected with the extended ground layer and the mixed layer;
the high-frequency element and the surface-mounted high-frequency decoupling capacitor which are connected with the power supply layer in the laminated unit are arranged on the surface layer of the circuit board nearest to the grounding layer in the laminated unit.
7. The circuit board of claim 6, wherein a surface mount low frequency decoupling capacitor connected to a power plane in the laminate unit is disposed on a surface of the circuit board furthest from a ground plane in the laminate unit.
8. The circuit board of claim 1, wherein the circuit board comprises two or more stacked units;
the power via hole and the power ground hole in each laminated unit are blind holes, and the other end of the power via hole is cut off in the laminated unit.
9. The circuit board of claim 8, wherein the high frequency components, the surface mount decoupling capacitors, connected to the power plane in each of the stacked units are disposed on a surface layer of the circuit board nearest to the ground plane in the stacked units.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910602509.6A CN112188723B (en) | 2019-07-04 | 2019-07-04 | A high-speed multi-layer planar circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910602509.6A CN112188723B (en) | 2019-07-04 | 2019-07-04 | A high-speed multi-layer planar circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN112188723A CN112188723A (en) | 2021-01-05 |
| CN112188723B true CN112188723B (en) | 2025-02-21 |
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| CN1695408A (en) * | 2003-01-31 | 2005-11-09 | 富士通株式会社 | Multilayer printed circuit board, electronic device, mounting method |
| CN103379729A (en) * | 2012-04-28 | 2013-10-30 | 鸿富锦精密工业（深圳）有限公司 | Printed circuit board |
| CN210670714U (en) * | 2019-07-04 | 2020-06-02 | 广州汽车集团股份有限公司 | A high-speed multi-layer planar circuit board |
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| JP3201345B2 (en) * | 1998-05-13 | 2001-08-20 | 日本電気株式会社 | Multilayer printed wiring board |
| JP3267274B2 (en) * | 1999-08-13 | 2002-03-18 | 日本電気株式会社 | Multilayer printed circuit board |
| CN108575044B (en) * | 2017-03-13 | 2023-01-24 | 富士康(昆山)电脑接插件有限公司 | Printed circuit board and assembly thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1695408A (en) * | 2003-01-31 | 2005-11-09 | 富士通株式会社 | Multilayer printed circuit board, electronic device, mounting method |
| CN103379729A (en) * | 2012-04-28 | 2013-10-30 | 鸿富锦精密工业（深圳）有限公司 | Printed circuit board |
| CN210670714U (en) * | 2019-07-04 | 2020-06-02 | 广州汽车集团股份有限公司 | A high-speed multi-layer planar circuit board |
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