CN112188257A - Clock control method and system - Google Patents
Clock control method and system Download PDFInfo
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- CN112188257A CN112188257A CN202010871220.7A CN202010871220A CN112188257A CN 112188257 A CN112188257 A CN 112188257A CN 202010871220 A CN202010871220 A CN 202010871220A CN 112188257 A CN112188257 A CN 112188257A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
- H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
- H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
- H04N21/4302—Content synchronisation processes, e.g. decoder synchronisation
- H04N21/4305—Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
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- Multimedia (AREA)
- Computer Networks & Wireless Communication (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Compression Or Coding Systems Of Tv Signals (AREA)
Abstract
The invention discloses a clock control method, which is used for controlling clock synchronization between a transmitting end and a receiving end, wherein the transmitting end is connected with the receiving end through an audio and video transmission channel, and the clock control method comprises the following steps: acquiring the crystal oscillator frequency of the receiving end and the cache parameters of the audio and video signals; calculating the crystal oscillator error between the transmitting end and the receiving end according to the change rate of the cache parameter of the receiving end; generating a correction coefficient according to the calculated crystal oscillator error; correcting the crystal oscillator frequency of the receiving end according to the generated correction coefficient to obtain a correction frequency; and generating a clock signal of the receiving end according to the obtained correction frequency. The clock control method can realize clock synchronization between the transmitting end and the receiving end and reduce clock errors. The invention also discloses a clock control system.
Description
Technical Field
The present invention relates to clock technologies, and in particular, to a clock control method and system.
Background
With the development of audio and video transmission technology, the cross-network transmission of audio and video signals is widely applied in the fields of digital television broadcasting, remote monitoring, digital video on demand, wireless multimedia and the like.
In the cross-network transmission of audio and video signals, the system comprises a transmitting end and a receiving end, wherein the transmitting end is used for encoding the audio and video signals and then sending the encoded audio and video signals to the receiving end, and the receiving end is used for decoding the audio and video signals and then outputting and playing the decoded audio and video signals.
In the prior art, a crystal oscillator clock is generally used to implement time synchronization between the transmitting end and the receiving end, but because a frequency error often exists between the crystal oscillator module of the transmitting end and the crystal oscillator module of the receiving end, a clock difference actually exists between the transmitting end and the receiving end, and the clock difference becomes larger and larger along with the lapse of time. If the clock speed of the receiving end is higher than that of the transmitting end, the audio and video buffer of the receiving end is smaller and smaller, and finally the audio and video buffer is empty, because no new audio and video signals can be output and played by the receiving end, the previous packet of content must be forged or repeatedly played, and the pause of video or the pause of audio is caused.
Disclosure of Invention
In order to solve the above-mentioned deficiencies of the prior art, the present invention provides a clock control method and system, which can achieve clock synchronization between a transmitting end and a receiving end and reduce clock errors.
The technical problem to be solved by the invention is realized by the following technical scheme:
a clock control method is used for controlling clock synchronization between a transmitting end and a receiving end, wherein the transmitting end is connected with the receiving end through an audio and video transmission channel, and the clock control method comprises the following steps:
acquiring the crystal oscillator frequency of the receiving end and the cache parameters of the audio and video signals;
calculating the crystal oscillator error between the transmitting end and the receiving end according to the change rate of the cache parameter of the receiving end;
generating a correction coefficient according to the calculated crystal oscillator error;
correcting the crystal oscillator frequency of the receiving end according to the generated correction coefficient to obtain a correction frequency;
and generating a clock signal of the receiving end according to the obtained correction frequency.
Further, before estimating the crystal oscillation error between the transmitting end and the receiving end, the method further comprises the following steps:
and judging whether the cache parameter of the receiving end is in a preset range, if not, calculating the crystal oscillator error between the transmitting end and the receiving end.
Further, after generating the clock signal of the receiving end, the method further includes the following steps:
and controlling the output rate of the audio and video signals cached by the receiving end according to the generated clock signal.
Further, the receiving end keeps the buffer parameters within a preset range by controlling the output rate of the receiving end.
Further, the buffer parameter is at least one of a buffer amount of the audio/video signal in the buffer of the receiving end and a space occupation ratio of the audio/video signal in the buffer of the receiving end.
Further, the correction coefficient is a frequency division coefficient or a frequency multiplication coefficient of the crystal oscillator frequency of the receiving end.
The utility model provides a clock control system for carry out clock synchronization between control transmitting terminal and the receiving terminal, connect through audio and video transmission path between transmitting terminal and the receiving terminal, including the receiving terminal, the receiving terminal includes crystal oscillator module, clock module and processing module:
the crystal oscillator module is used for generating a crystal oscillator frequency;
the processing module is used for decoding and caching the received audio and video signals, calculating a crystal oscillator error between the transmitting end and the receiving end according to the change rate of the caching parameter, and then generating a correction coefficient according to the calculated crystal oscillator error;
the clock module is used for generating a clock signal according to the crystal oscillator frequency generated by the crystal oscillator module and the correction coefficient generated by the processing module.
Further, the processing module comprises a buffer for buffering the decoded audio/video signal.
Furthermore, the processing module is further configured to control the output rate of the buffered audio/video signal according to the clock signal generated by the clock module.
The invention has the following beneficial effects: the clock control method and the clock control system correct the clock speed of the clock signal of the receiving end according to the cache parameter of the audio and video signal of the receiving end so as to realize clock synchronization with the transmitting end, reduce clock errors and ensure that the receiving end can normally output and play the audio and video signal.
Drawings
FIG. 1 is a block diagram illustrating the steps of a clock control method according to the present invention;
fig. 2 is a schematic block diagram of a clock control system provided by the present invention.
Detailed Description
The present invention will be described in detail below with reference to the accompanying drawings and examples.
Example one
As shown in fig. 1, a clock control method is used for controlling clock synchronization between a transmitting end and a receiving end, where the transmitting end and the receiving end are connected through an audio/video transmission channel, and includes the following steps:
s101: and acquiring the crystal oscillator frequency of the receiving end and the cache parameters of the audio and video signals.
In the step S101, the receiving end receives the encoded audio/video signal from the transmitting end through the audio/video transmission channel, then decodes the received audio/video signal, and then buffers the decoded audio/video signal in a buffer thereof; the buffer parameter refers to at least one of a buffer amount of the audio/video signal in the buffer of the receiving end and a space occupation ratio of the audio/video signal in the buffer of the receiving end, and the space occupation ratio of the audio/video signal in the buffer is preferably adopted.
The receiving end further comprises a crystal oscillator module, and the crystal oscillator module is used for generating a crystal oscillator frequency with fixed frequency.
S102: and judging whether the cache parameter of the receiving end is in a preset range, and if not, performing the next step S103.
In step S102, a preset range is preset, and only when the buffer parameter of the receiving end is not within the preset range, the following remaining steps are performed to control the clock synchronization between the transmitting end and the receiving end, and when the buffer parameter of the receiving end is within the preset range, step S101 and step S102 are repeated, so that the synchronization control is performed only when the accumulation of the clock difference affects the normal output playing of the receiving end, and the control is not performed when the accumulation of the clock difference does not affect the normal output playing of the receiving end, which can reduce the control frequency, and reduce the power consumption and the computational power consumption.
In this embodiment, the buffer parameter is a space ratio of the audio/video signal in the buffer of the receiving end, and the preset range is set to about 50%.
S103: and calculating the crystal oscillator error between the transmitting end and the receiving end according to the change rate of the cache parameter of the receiving end.
In step S103, the transmitting end also includes a crystal oscillator module, and the crystal oscillator module is configured to generate another crystal oscillator frequency with a fixed frequency.
When the change rate is positive, the crystal oscillator frequency of the transmitting end is larger than the crystal oscillator frequency of the receiving end, when the change rate is negative, the crystal oscillator frequency of the transmitting end is smaller than the crystal oscillator frequency of the receiving end, and when the change rate is zero, the crystal oscillator frequency of the transmitting end is equal to the crystal oscillator frequency of the receiving end; and the larger the numerical value of the change rate is, the larger the error of the crystal oscillator frequency between the transmitting end and the receiving end is.
S104: and generating a correction coefficient according to the calculated crystal oscillator error.
In step S104, the correction coefficient is a frequency division coefficient or a frequency multiplication coefficient of the crystal oscillator frequency of the receiving end, and when the change rate is positive, the correction coefficient is a frequency multiplication coefficient and is used for generating frequency multiplication amplification on the crystal oscillator frequency of the receiving end, and when the change rate is negative, the correction coefficient is a frequency division coefficient and is used for generating frequency division reduction on the crystal oscillator frequency of the receiving end.
S105: and correcting the crystal oscillator frequency of the receiving end according to the generated correction coefficient to obtain the correction frequency.
In step S105, when the change rate is positive, the crystal oscillator frequency of the receiving end is increased according to the generated frequency multiplication coefficient to obtain the correction frequency, and when the change rate is negative, the crystal oscillator frequency of the receiving end is decreased according to the generated frequency division coefficient to obtain the correction frequency.
S106: and generating a clock signal of the receiving end according to the obtained correction frequency.
In step S106, the clock speed of the clock signal at the receiving end is increased when the change rate is positive, and the clock speed of the clock signal at the receiving end is decreased when the change rate is negative.
The clock signal of the transmitting terminal is generated according to the crystal oscillator frequency of the transmitting terminal.
S107: and controlling the output rate of the audio and video signals cached by the receiving end according to the generated clock signal, wherein the caching parameter of the receiving end is maintained in a preset range by controlling the output rate of the receiving end.
In step S107, the generated clock signal is provided to the receiving end, and the receiving end automatically controls the output rate of the audio/video signal buffered by the receiving end according to the generated clock signal, so that the space occupation ratio of the audio/video signal in the buffer is always maintained at about 50%.
The clock control method corrects the clock speed of the clock signal of the receiving end according to the cache parameter of the audio and video signal of the receiving end so as to realize clock synchronization with the transmitting end, reduce clock errors and ensure that the receiving end can normally output and play the audio and video signal.
Example two
As shown in fig. 2, a clock control system for controlling clock synchronization between a transmitting end and a receiving end includes the transmitting end and the receiving end, which are connected through an audio/video transmission channel.
The receiving end comprises a crystal oscillator module, a clock module and a processing module, wherein
The crystal oscillator module is used for generating a crystal oscillator frequency;
the processing module is used for decoding and caching the received audio and video signals, calculating a crystal oscillator error between the transmitting end and the receiving end according to the change rate of the caching parameter, generating a correction coefficient according to the calculated crystal oscillator error, and controlling the output rate of the cached audio and video signals according to the clock signal generated by the clock module;
the clock module is used for generating a clock signal according to the crystal oscillator frequency generated by the crystal oscillator module and the correction coefficient generated by the processing module.
The processing module comprises a buffer used for buffering the decoded audio and video signals.
The receiving end also comprises a receiving module used for receiving the audio and video signals from the transmitting end.
In this embodiment, the clock module provides the generated clock signal to the receiving module, and the receiving module forwards the clock signal to the processing module.
The transmitting terminal comprises another crystal oscillator module, another clock module, another processing module and a transmitting module, wherein
The other crystal oscillator module is used for generating another crystal oscillator frequency;
the other clock module is used for generating another clock signal according to another crystal oscillator frequency generated by the other crystal oscillator module
The other processing module is used for coding the audio and video signals and controlling the sending rate of the coded audio and video signals according to another clock signal generated by the other clock module;
and the transmitting module is used for transmitting the coded audio and video signals to the receiving end.
In this embodiment, the other clock module directly provides the generated other clock signal to the other processing module, and the other processing module forwards the other clock signal to the transmitting module.
The above-mentioned embodiments only express the embodiments of the present invention, and the description is more specific and detailed, but not understood as the limitation of the patent scope of the present invention, but all the technical solutions obtained by using the equivalent substitution or the equivalent transformation should fall within the protection scope of the present invention.
Claims (9)
1. A clock control method is used for controlling clock synchronization between a transmitting end and a receiving end, and the transmitting end is connected with the receiving end through an audio and video transmission channel, and is characterized by comprising the following steps:
acquiring the crystal oscillator frequency of the receiving end and the cache parameters of the audio and video signals;
calculating the crystal oscillator error between the transmitting end and the receiving end according to the change rate of the cache parameter of the receiving end;
generating a correction coefficient according to the calculated crystal oscillator error;
correcting the crystal oscillator frequency of the receiving end according to the generated correction coefficient to obtain a correction frequency;
and generating a clock signal of the receiving end according to the obtained correction frequency.
2. The clock control method according to claim 1, further comprising, before estimating a crystal error between the transmitting end and the receiving end, the steps of:
and judging whether the cache parameter of the receiving end is in a preset range, if not, calculating the crystal oscillator error between the transmitting end and the receiving end.
3. The clock control method according to claim 1, further comprising, after generating the clock signal of the receiving end, the steps of:
and controlling the output rate of the audio and video signals cached by the receiving end according to the generated clock signal.
4. The clock control method according to claim 3, wherein the receiver maintains the buffer parameter within a predetermined range by controlling the output rate of the receiver.
5. The clock control method according to claim 1, wherein the buffer parameter is at least one of a buffer amount of the audio/video signal in the buffer of the receiving end and a space occupation ratio of the audio/video signal in the buffer of the receiving end.
6. The clock control method according to claim 1, wherein the correction factor is a frequency division factor or a frequency multiplication factor of a crystal oscillator frequency of the receiving end.
7. The utility model provides a clock control system for carry out clock synchronization between control transmitting terminal and the receiving terminal, connect through audio and video transmission path between transmitting terminal and the receiving terminal, its characterized in that, including the receiving terminal, the receiving terminal includes crystal oscillator module, clock module and processing module:
the crystal oscillator module is used for generating a crystal oscillator frequency;
the processing module is used for decoding and caching the received audio and video signals, calculating a crystal oscillator error between the transmitting end and the receiving end according to the change rate of the caching parameter, and then generating a correction coefficient according to the calculated crystal oscillator error;
the clock module is used for generating a clock signal according to the crystal oscillator frequency generated by the crystal oscillator module and the correction coefficient generated by the processing module.
8. The clock control system of claim 7, wherein the processing module comprises a buffer for buffering the decoded audio/video signal.
9. The clock control system of claim 7, wherein the processing module is further configured to control an output rate of the buffered audio/video signal according to a clock signal generated by the clock module.
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| CN202010871220.7A CN112188257A (en) | 2020-08-26 | 2020-08-26 | Clock control method and system |
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| CN202010871220.7A CN112188257A (en) | 2020-08-26 | 2020-08-26 | Clock control method and system |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112527237A (en) * | 2021-02-09 | 2021-03-19 | 深圳市创成微电子有限公司 | Audio interface circuit, control method thereof and audio equipment |
| CN112637102A (en) * | 2021-02-07 | 2021-04-09 | 深圳市创成微电子有限公司 | Audio interface circuit, control method thereof and audio equipment |
| CN114153311A (en) * | 2021-11-19 | 2022-03-08 | 北京小米移动软件有限公司 | Device control method, device, device and storage medium |
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| WO2013097182A1 (en) * | 2011-12-30 | 2013-07-04 | 宝添管理有限公司 | Wireless digital communication system and data rate error compensation method therein |
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| CN1214777A (en) * | 1996-04-01 | 1999-04-21 | 汤姆森多媒体公司 | Real-time clock for consumer device and method for implementing such clock |
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Address after: 3-4 / F, building 16, Hejing Industrial Zone, No.87 Hexiu West Road, Heping community, Fuhai street, Bao'an District, Shenzhen, Guangdong 518100 Applicant after: Shenzhen Bachao Technology Co.,Ltd. Address before: 3-4 / F, building 16, Hejing Industrial Zone, No.87 Hexiu West Road, Heping community, Fuhai street, Bao'an District, Shenzhen, Guangdong 518100 Applicant before: SHENZHEN BACHAO TECHNOLOGY Co.,Ltd. |
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Address after: 518103 301-401, building 16, Hejing Industrial Zone, No. 87, Hexiu West Road, Zhancheng community, Fuhai street, Bao'an District, Shenzhen, Guangdong Province Applicant after: Shenzhen Bachao Technology Co.,Ltd. Address before: 3-4 / F, building 16, Hejing Industrial Zone, No.87 Hexiu West Road, Heping community, Fuhai street, Bao'an District, Shenzhen, Guangdong 518100 Applicant before: Shenzhen Bachao Technology Co.,Ltd. |
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Application publication date: 20210105 |