CN112187261B - Digital-to-analog converter and compensation circuit - Google Patents

Abstract

The invention provides a digital-to-analog conversion device and a compensation circuit. In one embodiment, the digital-to-analog conversion device includes a ladder-type digital-to-analog converter and a compensation circuit. The ladder-type digital-to-analog converter is configured to receive a digital code having a plurality of bits and a reference voltage, and convert the digital code into an analog output signal according to the reference voltage. The compensation circuit is configured to receive the digital code, decode the digital code to generate a compensation code having a plurality of bits, and compensate a current value of the reference current according to the compensation code to generate a compensated reference current. The compensated reference current has a constant current value corresponding to different digital codes, thereby making the reference voltage constant.

Description

Digital-to-analog conversion device and compensation circuit

technical field

The invention relates to a digital-to-analog conversion device and a compensation circuit, in particular to a digital-to-analog conversion device and a compensation circuit with a constant reference voltage value.

Background technique

Please refer to FIG. 1 . FIG. 1 is a schematic circuit diagram of a conventional ladder-type digital-to-analog converter. Generally speaking, the current ladder-type digital-to-analog converter (R2R DAC) 410 generates an analog output signal Aout corresponding to the digital code Din through the reference voltage Vref and the digital code Din. For the ladder-type DAC 410 with high resolution requirements, the reference voltage Vref is an important parameter affecting the performance of the ladder-type DAC 410 . The reference voltage Vref is determined by the reference current Iref, the system power supply VDD and the wiring resistance Rp. However, the reference current Iref will produce fluctuations in current value according to the digital code Din. Such a fluctuation of the reference current Iref will cause the reference voltage Vref to be unstable, thereby reducing the resolution and performance of the ladder-type digital-to-analog converter 410, such as signal plus noise and distortion (SINAD), spurious-free dynamic Range (spurious free dynamic range, SFDR), etc.

Contents of the invention

The invention provides a digital-to-analog conversion device and a compensation circuit with a constant reference voltage.

The digital-to-analog conversion device of the present invention includes a ladder-type digital-to-analog converter and a compensation circuit. The ladder-type digital-to-analog converter is configured to receive a digital code with a plurality of bits and a reference voltage, and convert the digital code into an analog output signal according to the reference voltage. The reference voltage is generated according to the reference current. The reference current has a current value fluctuation corresponding to the digital code. The compensation circuit is coupled to the ladder-type digital-to-analog converter. The compensation circuit is configured to receive the digital code, decode the digital code according to the fluctuation of the current value to generate a compensation code with a plurality of bits, and compensate the current value of the reference current according to the compensation code to generate a compensated reference current. The compensated reference current has a constant current value corresponding to different digital codes.

The compensation circuit of the present invention is suitable for ladder-type digital-to-analog converters. The ladder-type digital-to-analog converter is configured to receive a digital code with a plurality of bits and receive a reference voltage and convert the digital code into an analog output signal according to the reference voltage. The reference voltage is generated according to the reference current. The reference current has a current value fluctuation corresponding to the digital code. The compensation circuit is configured to receive the digital code and decode the digital code according to the fluctuation of the current value to generate a compensation code with a plurality of bits. The compensation circuit is also configured to compensate the current value of the reference current according to the compensation code to generate a compensated reference current. The compensated reference current has a constant current value corresponding to different digital codes.

Based on the above, the digital-to-analog conversion device and the compensation circuit of the present invention decode the digital code according to the current value fluctuation of the reference current corresponding to the digital code to generate a compensation code, and compensate the current value of the reference current according to the compensation code to generate a compensated reference current. The reference current may have constant current values corresponding to different digital codes. In this way, the reference voltage can have a constant voltage value.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail with reference to the accompanying drawings.

Description of drawings

FIG. 1 is a schematic circuit diagram of an existing ladder-type digital-to-analog converter.

FIG. 2 is a schematic circuit diagram of a digital-to-analog conversion device according to a first embodiment of the present invention.

FIG. 3 is a schematic circuit diagram of a digital-to-analog conversion device according to a second embodiment of the present invention.

FIG. 4 is a schematic diagram showing current values corresponding to digital code values of the reference current, the first compensation current and the compensated reference current according to an embodiment of the present invention.

FIG. 5 is a schematic circuit diagram of a digital-to-analog conversion device according to a third embodiment of the present invention.

FIG. 6 is a schematic diagram showing current values of the reference current, the first compensation current, the second compensation current and the compensated reference current corresponding to digital code values according to an embodiment of the present invention.

Explanation of reference numbers:

100, 200, 300: digital to analog conversion device

110, 410: Ladder-type digital-to-analog converter

120, 220, 320: compensation circuit

Dcmp: compensation code

Iref_cmp: Compensated reference current

Icmp: compensation current

Vref: reference voltage

D1: first digital code value

D2: second digital code value

Din: digital code

Aout: Analog output signal

Iref: reference current

VDD: system power supply

Rp: wiring resistance

222, 322: first decoder

224, 324: the first compensation current generator

Ain: first compensation code

Icmp1: first compensation current

SW1_0～SW1_m: first switch

R1_0～R1_m: the first compensation resistor

326: second decoder

328: second compensation current generator

Bin: the second compensation code

Icmp2: second compensation current

SW2_0～SW2_n: the second switch

R2_0～R2_n: the second compensation resistor

Detailed ways

Please refer to FIG. 2 , which is a schematic diagram of a digital-to-analog conversion device according to a first embodiment of the present invention. In this embodiment, the digital-to-analog conversion device 100 includes a ladder-type digital-to-analog converter 110 and a compensation circuit 120 . The ladder-type DAC 110 is configured to receive a digital code Din having a plurality of bits and a reference voltage Vref, and convert the digital code Din into an analog output signal Aout according to the reference voltage Vref. The ladder type DAC 110 receives a reference voltage Vref through a reference voltage input terminal. The reference voltage Vref is generated according to the reference current Iref. For example, a voltage drop will be generated when the reference current Iref flows through the wiring resistor Rp. The reference voltage Vref is the difference between the system power supply VDD and the aforementioned voltage drop. The reference current Iref has a current value fluctuation corresponding to the digital code Din. The aforementioned fluctuation of the current value can be obtained, for example, during the manufacturing process of the ladder-type digital-to-analog converter 110 , during the testing process, or through simulation. The compensation circuit 120 is coupled to the ladder-type digital-to-analog converter 110 . The compensation circuit 120 is configured to receive the digital code Din, decode the digital code Din according to the fluctuation of the current value to generate a compensation code Dcmp having a plurality of bits, and compensate the current value of the reference current Iref according to the compensation code Dcmp to generate a compensated Reference current Iref_cmp. For example, the compensation circuit 120 is coupled to the reference voltage input terminal. The compensation circuit 120 generates a compensation current Icmp according to the compensation code Dcmp. The digital-to-analog conversion device 100 sums the compensation current Icmp and the reference current Iref to generate a compensated reference current Iref_cmp.

In this embodiment, the compensated reference current Iref_cmp has a constant current value corresponding to different digital codes Din. That is to say, the current value of the compensated reference current Iref_cmp will not change with the change of the digital code Din.

In this embodiment, since the current value of the compensated reference current Iref_cmp is constant corresponding to different digital codes Din, the voltage drop caused by the compensated reference current Iref_cmp flowing through the wiring resistor Rp is also constant. In this way, the ladder-type digital-to-analog converter 110 can receive a constant reference voltage Vref. The ladder-type digital-to-analog converter can receive a constant reference voltage, thereby improving the resolution of the ladder-type digital-to-analog converter, signal plus noise and distortion ratio (signal plus noise and distortion, SINAD), spurious freedynamic range (spurious freedynamic range) , SFDR) and other properties.

In this embodiment, the ladder-type digital-to-analog converter 110 and the compensation circuit 120 are connected to the reference ground terminal, and the potential of the reference ground terminal is used as the reference low voltage level. In some embodiments, the digital-to-analog conversion device 100 may further include a wiring reference resistor (not shown). The first end of the wiring reference resistor is coupled to the ladder-type digital-to-analog converter 110 and the compensation circuit 120 . The second terminal of the wiring reference resistor is coupled to the reference ground terminal. The wiring reference resistor is used to provide a reference low voltage level at the first end of the wiring reference resistor according to the resistance value of the wiring reference resistor. The ladder-type digital-to-analog converter 110 and the compensation circuit 120 receive a relatively stable reference low voltage level.

For further explanation, please refer to FIG. 3 and FIG. 4 at the same time. FIG. 3 is a schematic circuit diagram of a digital-to-analog conversion device according to a second embodiment of the present invention. FIG. 4 is a schematic diagram showing current values corresponding to digital code values of the reference current, the first compensation current and the compensated reference current according to an embodiment of the present invention. In this embodiment, the digital-to-analog conversion device 200 includes a ladder-type digital-to-analog converter 110 and a compensation circuit 220 . The compensation circuit 220 includes a first decoder 222 and a first compensation current generator 224 . The first decoder 222 is configured to receive the digital code Din and decode the digital code Din to generate a first compensation code Ain of a compensation code (such as the compensation code Dcmp of the first embodiment). The first compensation code Ain has multiple bits. The number of bits of the first compensation code Ain and the number of bits of the digital code Din may be the same or different. In this embodiment, in the design of the first decoder 222 , the required gate stages are lower than six. In this way, the digital-to-analog conversion device 200 can work under high-frequency (above 7.2 GHz) conditions. The first compensation current generator 224 is coupled to the first decoder 222 and the reference voltage input terminal. The first compensation current generator 224 is configured to receive the first compensation code Ain, and generate a first compensation current Icmp1 corresponding to the digital code Din according to the first compensation code Ain.

In this embodiment, the digital code value section between the first digital code value D1 and the second digital code value D2 of the reference current Iref in the digital code value of the digital code Din has a first-order current value with current value fluctuations ups and downs. For example, in the above-mentioned digital code value section, the current value of the reference current Iref increases with the increase of the digital code value, for example, increases from 5.5 mA to 7.5 mA. Next, it decreases as the value of the digital code increases, for example, from 7.5 milliamperes to 5.5 milliamperes. After the above-mentioned first-order current value fluctuation is known, the first decoder 222 and the first compensation current generator 224 are designed to provide the first compensation current as shown in FIG. 4 according to the above-mentioned first-order current value fluctuation. The result of the current value of Icmp1. The first compensation current Icmp1 can be used to compensate the reference current Iref, so as to eliminate the fluctuation of the first-stage current value. Different designs of the ladder-type DAC 110 may have different first compensation codes Ain. The designs of the first decoder 222 and the first compensation current generator 224 may also be different.

In this embodiment, the current fluctuation of the first compensation current Icmp1 is designed to be negatively correlated with the first-order current fluctuation. In this way, the digital-to-analog conversion device 200 can add the first compensation current Icmp1 and the reference current Iref to generate a compensated reference current Iref_cmp. The compensated reference current Iref_cmp has the same current value at different digital code values, for example, 7.5 or 8 mA.

To describe the generation method of the first compensation current Icmp1 in detail, in this embodiment, the first compensation current generator 224 includes m+1 first switches SW1_0 ˜ SW1_m and m+1 first compensation resistors R1_0 ˜ R1_m. The first terminals of the first switches SW1_0 - SW1_m are respectively coupled to the reference voltage input terminal. The control terminals of the first switches SW1_0˜SW1_m are respectively coupled to the first decoder 222 to receive different bit codes of the first compensation code Ain. For example, the number of the first switches SW1_0 ˜ SW1_m is equal to the number of bits of the first compensation code Ain. The control end of the first switch SW1_0 is used to receive the 0th bit of the first compensation code Ain. The control terminal of the first switch SW1_1 is used for receiving the first bit code of the first compensation code Ain. The control end of the first switch SW1_2 is used for receiving the second bit code of the first compensation code Ain. The control terminal of the first switch SW1_m is used for receiving the mth bit code of the first compensation code Ain. The present invention is not limited to this example.

The first ends of the first compensation resistors R1_0 ˜ R1_m are coupled to the second ends of the first switches SW1_0 ˜ SW1_m in a one-to-one manner. The second ends of the first compensation resistors R1_0˜R1_m are respectively coupled to the reference ground. For example, the first end of the first compensation resistor R1_0 is coupled to the second end of the first switch SW1_0 . A first end of the first compensation resistor R1_1 is coupled to a second end of the first switch SW1_1. A first end of the first compensation resistor R1_2 is coupled to a second end of the first switch SW1_2. A first end of the first compensation resistor R1_m is coupled to a second end of the first switch SW1_m.

In this embodiment, the first switches SW1_0 - SW1_m may be implemented by at least one transistor switch. The first switches SW1_0 - SW1_m are respectively turned on or turned off according to the first compensation code Ain. The first compensation current generator 224 turns on or off the first switches SW1_0˜SW1_m according to the first compensation code Ain, and determines the number of parallel connections of the first compensation resistors through the turned-on first switches to provide the first compensation resistors. value. The first compensation current generator 224 can provide the first compensation current Icmp1 according to the first compensation resistance value. The first compensation current Icmp1 flows from the reference voltage input terminal through the first compensation current generator 224 and flows to the reference ground terminal. For example, in the digital code value segment between the first digital code value D1 and the second digital code value D2, when the reference current Iref has a lower current value corresponding to the third digital code value, the first decoding The device 222 decodes the third digital code value to generate a first compensation code Ain for indicating to increase the current value of the first compensation current Icmp1. The first compensation current generator 224 increases the number of parallel connections of the first compensation resistors according to the first compensation code Ain to provide a lower value of the first compensation resistors, thereby increasing the current value of the first compensation current Icmp1 . On the other hand, when the reference current Iref has a lower current value corresponding to the fourth digital code value, the first decoder 222 decodes the fourth digital code value to generate a current indicating to reduce the first compensation current Icmp1 The value of the first compensation code Ain. The first compensation current generator 224 reduces the number of parallel connections of the first compensation resistors according to the first compensation code Ain to provide a higher value of the first compensation resistor, thereby reducing the current value of the first compensation current Icmp1 .

Please refer to FIG. 5 and FIG. 6 at the same time. FIG. 5 is a schematic circuit diagram of a digital-to-analog conversion device according to a third embodiment of the present invention. FIG. 6 is a schematic diagram showing current values of the reference current, the first compensation current, the second compensation current and the compensated reference current corresponding to digital code values according to an embodiment of the present invention. In this embodiment, the digital-to-analog conversion device 300 includes a ladder-type digital-to-analog converter 110 and a compensation circuit 320 . The compensation circuit 320 includes a first decoder 322 , a first compensation current generator 324 , a second decoder 326 and a second compensation current generator 328 . The implementation details of the first decoder 322 and the first compensation current generator 324 and the method of generating the first compensation current Icmp1 can be sufficiently taught in the implementation content of the second embodiment, so they will not be repeated here. In this embodiment, the first-order current fluctuation of the reference current Iref has a plurality of second-order current fluctuation packs. The generation of multiple second-order current value fluctuation packets is because the design of the ladder-type DAC 110 is changed, for example, a thermometer-coded circuit is added to the ladder-type DAC 110 . Therefore, compared with the second embodiment, this embodiment adds a second decoder 326 and a second compensation current generator 328 in order to eliminate the second-order current value fluctuation packet.

The above-mentioned first-order current fluctuation and second-order current fluctuation package can be obtained, for example, during the manufacturing process of the ladder-type digital-to-analog converter 110 , during the testing process, or through simulation. After the above-mentioned first-order current fluctuation and second-order current fluctuation packets are known, the first decoder 322, the first compensation current generator 324, the second decoder 326, and the second compensation current generator 328 will The first-order current fluctuation and the second-order current fluctuation package are designed to provide the result of the current value of the first compensation current Icmp1 and the result of the current value of the second compensation current Icmp2 as shown in FIG. 6 .

In this embodiment, the second decoder 326 is configured to receive the digital code Din and decode the digital code Din to generate a second compensation code Bin of the compensation code (such as the compensation code Dcmp of the first embodiment). The second compensation code Bin has a plurality of bits. In this embodiment, in the design of the second decoder 326 , the required order of logic gates is lower than 6 orders. In this way, the digital-to-analog conversion device 300 can work under high-frequency (above 7.2 GHz) conditions. The second compensation current generator 328 is coupled to the second decoder 326 and the reference voltage input terminal. The second compensation current generator 328 is configured to receive the second compensation code Bin, and generate a second compensation current Icmp2 corresponding to the digital code Din according to the second compensation code Bin. The second compensation current Icmp2 is used to eliminate the second-order current value fluctuation packet.

In this embodiment, the current fluctuation of the second compensation current Icmp2 is designed to be negatively correlated with the second-order current fluctuation. Therefore, the digital-to-analog conversion device 300 can sum up the second compensation current Icmp2 and the reference current Iref as shown in FIG. 6 to eliminate the second-order current fluctuation packet. After the fluctuation of the second order current value of the reference current Iref is eliminated, the result of the current value of the reference current Iref corresponding to the digital code value will be equal or similar to the current value of the reference current Iref corresponding to the digital code value as shown in Figure 4 the result of. That is to say, the digital-to-analog conversion device 300 can add up the first compensation current Icmp1 , the second compensation current Icmp2 and the reference current Iref as shown in FIG. 6 to generate the compensated reference current Iref_cmp. In this embodiment, different designs of the ladder-type DAC 110 may have different first compensation codes Ain and different second compensation codes Bin. The designs of the first decoder 322 , the first compensation current generator 324 , the second decoder 326 and the second compensation current generator 328 may also be different.

To describe the generation method of the second compensation current Icmp2 in detail, in this embodiment, the second compensation current generator 328 includes n+1 second switches SW2_0 -SW2_n and n+1 second compensation resistors R2_0 -R2_n. The first ends of the second switches SW2_0˜SW2_n are respectively coupled to the reference voltage input ends. The control terminals of the second switches SW2_0 - SW2_n are respectively coupled to the second decoder 326 to receive different bit codes of the second compensation code Bin. For example, the number of the second switches SW2_0˜SW2_n is equal to the number of bits of the second compensation code Bin. The control end of the second switch SW2_0 is used to receive the 0th bit of the second compensation code Bin. The control terminal of the second switch SW2_1 is used for receiving the first bit code of the second compensation code Bin. The control terminal of the second switch SW2_2 is used for receiving the second bit code of the second compensation code Bin. The control terminal of the second switch SW2_n is used for receiving the nth bit code of the second compensation code Bin. The present invention is not limited to this example.

The first ends of the second compensation resistors R2_0 ˜ R2_n are coupled to the second ends of the second switches SW2_0 ˜ SW2_n in a one-to-one manner. Second ends of the second compensation resistors R2_0˜R2_n are respectively coupled to the reference ground. For example, the first end of the second compensation resistor R2_0 is coupled to the second end of the second switch SW2_0 . A first end of the second compensation resistor R2_1 is coupled to a second end of the second switch SW2_1. A first end of the second compensation resistor R2_2 is coupled to a second end of the second switch SW2_2. A first end of the second compensation resistor R2_n is coupled to a second end of the second switch SW2_n.

In this embodiment, the second switches SW2_0 - SW2_n may be implemented by at least one transistor switch. The second switches SW2_0˜SW2_n are respectively turned on or turned off according to the second compensation code Bin. The second compensation current generator 328 turns on or off the second switches SW2_0˜SW2_n according to the second compensation code Bin, and determines the parallel connection quantity of the second compensation resistors through the turned-on second switches to provide the second compensation resistors. value. The second compensation current generator 328 can provide the second compensation current Icmp2 according to the second compensation resistance value. The second compensation current Icmp2 flows from the reference voltage input terminal through the second compensation current generator 328 and flows to the reference ground terminal.

In some embodiments, the first decoder 322 and the second decoder 326 can be integrated into a single decoding circuit. That is to say, the above decoding circuit can decode the digital code Din to generate the first compensation code Ain and the second compensation code Bin.

In summary, the digital-to-analog conversion device and the compensation circuit of the present invention decode the digital code according to the current value fluctuation of the reference current corresponding to the digital code to generate a compensation code, and compensate the current value of the reference current according to the compensation code to generate Compensated reference current. Therefore, the reference current may have constant current values corresponding to different digital codes. In this way, the ladder-type DAC can receive a constant reference voltage, thereby improving the resolution of the ladder-type DAC, as well as the performance of SINAD and SFDR.

Although the present invention has been disclosed above with the embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, this The scope of protection of the invention should be defined by the claims.

Claims (16)

1. A digital-to-analog converter, characterized in that it comprises: a ladder-type digital-to-analog converter configured to receive a digital code having a plurality of bits and receive a reference voltage, and convert the digital code into an analog output signal according to the reference voltage, wherein the reference voltage is varied according to a reference current is generated, wherein the reference current has a current value fluctuation corresponding to the digital code; and The compensation circuit, coupled to the ladder-type digital-to-analog converter, is configured to receive the digital code, decode the digital code according to the fluctuation of the current value to generate a compensation code with a plurality of bits, and according to the The compensation code compensates the current value of the reference current to generate a compensated reference current, wherein the compensated reference current has a constant current value corresponding to different digital codes, Wherein the digital code value section of the reference current between the first digital code value and the second digital code value in the digital code value of the digital code has a first-order current value fluctuation of the current value fluctuation, wherein The first-order current value fluctuation of the reference current has a plurality of second-order current value fluctuation packets, wherein the ladder-type digital-to-analog converter receives the reference voltage through a reference voltage input terminal, wherein the compensation circuit includes: a first decoder configured to receive the digital code and decode the digital code to generate a first compensation code of the compensation code, wherein the first compensation code has a plurality of bits; A first compensation current generator, coupled to the first decoder and the reference voltage input terminal, configured to receive the first compensation code, and generate a digital code corresponding to the first compensation code according to the first compensation code The first compensation current; a second decoder configured to receive the digital code and decode the digital code to generate a second compensation code of the compensation code, wherein the second compensation code has a plurality of bits; and A second compensation current generator, coupled to the second decoder and the reference voltage input terminal, configured to receive the second compensation code, and generate a digital code corresponding to the second compensation code according to the second compensation code The second compensation current, The first compensation current is used to compensate the reference current to eliminate the first-order current fluctuations, and the second compensation current is used to eliminate the plurality of second-order current fluctuation packets. 2. The digital-to-analog conversion device according to claim 1, wherein the first compensation current generator comprises: a plurality of first switches, the first ends of the plurality of first switches are respectively coupled to the reference voltage input end, and the control ends of the plurality of first switches are respectively coupled to the first decoder to receive different bit codes of the first compensation code; and a plurality of first compensation resistors, the first terminals of the plurality of first compensation resistors are coupled one-to-one to the second terminals of the plurality of first switches, and the second terminals of the plurality of first compensation resistors The terminals are respectively coupled to the reference ground terminals. 3. The digital-to-analog conversion device according to claim 2, wherein the first compensation current generator turns on or off the plurality of first switches according to the first compensation code, and is guided by The plurality of first switches turned on determines the number of parallel connections of the plurality of first compensation resistors to provide a first compensation resistance value, and provides the first compensation current according to the first compensation resistance value. 4 . The digital-to-analog conversion device according to claim 1 , wherein the current value fluctuation of the first compensation current is designed to exhibit a negative correlation with the first-order current value fluctuation. 5. The digital-to-analog conversion device according to claim 1, wherein the digital-to-analog conversion device sums the first compensation current and the reference current to generate the compensated reference current. 6. The digital-to-analog conversion device according to claim 1, wherein the second compensation current generator comprises: a plurality of second switches, the first ends of the plurality of second switches are respectively coupled to the reference voltage input end, and the control ends of the plurality of second switches are respectively coupled to the second decoder to receive a different bit code of the second compensation code; and a plurality of second compensation resistors, the first ends of the plurality of second compensation resistors are coupled one-to-one to the second ends of the plurality of second switches, and the second ends of the plurality of second compensation resistors The terminals are respectively coupled to the reference ground terminals. 7. The digital-to-analog conversion device according to claim 6, wherein the second compensation current generator turns on or off the plurality of second switches according to the second compensation code, and is guided by The plurality of second switches that are turned on determine the number of parallel connections of the plurality of second compensation resistors to provide a second compensation resistance value, and provide the second compensation current according to the second compensation resistance value. 8. The digital-to-analog conversion device according to claim 1, wherein the digital-to-analog conversion device sums the first compensation current, the second compensation current, and the reference current to generate the compensated reference current. 9. The digital-to-analog conversion device according to claim 1, wherein the digital-to-analog conversion device further comprises: Wiring reference resistors, the first end of the wiring reference resistors is coupled to the ladder-type digital-to-analog converter and the compensation circuit, the second end of the wiring reference resistors is coupled to the reference ground terminal, and is used to The resistance value of the wiring reference resistor provides a reference low voltage level at the first terminal of the wiring reference resistor. 10. A compensation circuit suitable for a ladder-type digital-to-analog converter, characterized in that the ladder-type digital-to-analog converter is configured to receive a digital code having a plurality of bits and a reference voltage, and based on the reference voltage converting the digital code into an analog output signal, wherein the reference voltage is generated from a reference current having a current value fluctuation corresponding to the digital code, wherein the compensation circuit is configured to: receiving the digital code, decoding the digital code according to the current value fluctuation to generate a compensation code having a plurality of bits, and Compensating the current value of the reference current according to the compensation code to generate a compensated reference current, wherein the compensated reference current has a constant current value corresponding to different digital codes, Wherein the digital code value section of the reference current between the first digital code value and the second digital code value in the digital code value of the digital code has a first-order current value fluctuation of the current value fluctuation, so There are multiple second-order current value fluctuation packets in the first-order current value fluctuation of the reference current, wherein the ladder-type digital-to-analog converter receives the reference voltage through a reference voltage input terminal, wherein the compensation circuit includes: a first decoder configured to receive the digital code and decode the digital code to generate a first compensation code of the compensation code, wherein the first compensation code has a plurality of bits; A first compensation current generator, coupled to the first decoder and the reference voltage input terminal, configured to receive the first compensation code, and generate a digital code corresponding to the first compensation code according to the first compensation code The first compensation current; a second decoder configured to receive the digital code and decode the digital code to generate a second compensation code of the compensation code, wherein the second compensation code has a plurality of bits; and A second compensation current generator, coupled to the second decoder and the reference voltage input terminal, configured to receive the second compensation code, and generate a digital code corresponding to the second compensation code according to the second compensation code The second compensation current, The first compensation current is used to compensate the reference current to eliminate the first-order current fluctuations, and the second compensation current is used to eliminate the plurality of second-order current fluctuation packets. 11. The compensation circuit according to claim 10, wherein the first compensation current generator comprises: a plurality of first switches, the first ends of the plurality of first switches are respectively coupled to the reference voltage input end, and the control ends of the plurality of first switches are respectively coupled to the first decoder to receive different bit codes of the first compensation code; and a plurality of first compensation resistors, the first terminals of the plurality of first compensation resistors are coupled one-to-one to the second terminals of the plurality of first switches, and the second terminals of the plurality of first compensation resistors The terminals are respectively coupled to the reference ground terminals. 12. The compensation circuit according to claim 11, wherein the first compensation current generator turns on or off the plurality of first switches according to the first compensation code, and through the turned on The plurality of first switches determine the number of parallel connections of the plurality of first compensation resistors to provide a first compensation resistance value, and provide the first compensation current according to the first compensation resistance value. 13. The compensation circuit according to claim 10, characterized in that, the fluctuation of the current value of the first compensation current is designed to exhibit a negative correlation with the fluctuation of the first-order current value. 14. The compensation circuit according to claim 10, wherein the second compensation current generator comprises: a plurality of second switches, the first ends of the plurality of second switches are respectively coupled to the reference voltage input end, and the control ends of the plurality of second switches are respectively coupled to the second decoder to receive a different bit code of the second compensation code; and a plurality of second compensation resistors, the first ends of the plurality of second compensation resistors are coupled one-to-one to the second ends of the plurality of second switches, and the second ends of the plurality of second compensation resistors The terminals are respectively coupled to the reference ground terminals. 15. The compensation circuit according to claim 14, wherein the second compensation current generator turns on or off the plurality of second switches according to the second compensation code, and through the turned on The plurality of second switches determines the number of parallel connections of the plurality of second compensation resistors to provide a second compensation resistance value, and provides the second compensation current according to the second compensation resistance value. 16. The compensation circuit according to claim 10, wherein the compensation circuit further comprises: Wiring reference resistors, the first end of the wiring reference resistors is coupled to the ladder-type digital-to-analog converter and the compensation circuit, the second end of the wiring reference resistors is coupled to the reference ground terminal, and is used to The resistance value of the wiring reference resistor provides a reference low voltage level at the first terminal of the wiring reference resistor.

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