CN112187049A

CN112187049A - Circuit, corresponding multiphase converter device and operating method

Info

Publication number: CN112187049A
Application number: CN202010626740.1A
Authority: CN
Inventors: A·加塔尼
Original assignee: STMicroelectronics SRL
Current assignee: STMicroelectronics SRL
Priority date: 2019-07-02
Filing date: 2020-07-01
Publication date: 2021-01-05
Anticipated expiration: 2040-07-01
Also published as: CN112187049B; US20220329146A1; US20210006163A1; US11404952B2; CN213305259U; US12244215B2; IT201900010662A1

Abstract

Circuits, corresponding multiphase converter devices and methods of operation are disclosed. The first switch couples an input node receiving a main control signal for a main switching stage of the multiphase converter to an output node delivering a secondary control signal for a secondary switching stage following actuation of the secondary switching stage. The second switch couples the output node to the capacitor during the period of activation/deactivation of the secondary switching stage. Current is supplied to the capacitor during the actuation period or current is drawn from the capacitor during the de-actuation period. The source current or sink current may be generated in proportion to the main control signal.

Description

Circuit, corresponding multiphase converter device and operating method

Cross Reference to Related Applications

The present application claims priority to italian patent application No. 102019000010662 filed on 7/2/2019, the contents of which are incorporated herein by reference in their entirety to the maximum extent allowed by law.

Technical Field

The present description relates to multi-phase electronic converters, such as DC/DC converter devices.

In particular, one or more embodiments relate to techniques for managing transitions of a multi-phase DC/DC converter between different operating states (e.g., managing power up and power down of a secondary phase).

Background

Electronic converters, such as DC/DC converters, are widely used in many applications to generate the power supply voltage levels required for the operation of complex electronic systems, such as smart phones, notebook computers, or other devices. The stable and accurate supply voltage provided at the output of the converter may also facilitate matching the performance expected from such electronic systems.

In many applications, the converter may be designed, for example, with power efficiency in mind, in order to reduce energy consumption.

For example, low power consumption of the converter may facilitate increasing the operational life of the battery-powered electronic device.

In the case of cable powered equipment, low power consumption may be beneficial, for example, due to reduced thermal stress caused by power dissipation.

Some applications may involve a wide range of output current capabilities from electronic converters. In order to provide satisfactory converter power efficiency throughout the entire output current range, multiphase DC/DC converters have been developed in order to avoid high currents flowing simultaneously in transistors (e.g., MOS transistors) and in components external to the converter.

A multiphase DC/DC converter includes more than two switching stages coupled (e.g., in parallel) at an output node of the converter, each of the switching stages being controlled by a respective PWM generation circuit. Typically, the main phase (i.e. the main switching stage) of the converter operates when the output load current is low, and at least one secondary phase may be activated as a result of the increase in output current. In the latter case, each of the active phases provides a fraction of the total output current.

In such a multi-phase DC/DC converter, transitions between different operating states (where each state corresponds to a different set of phases that are activated, and the transitions include powering up or down at least one secondary phase) should be properly managed.

Both powering up and powering down of the secondary phase may affect the performance of the converter, possibly creating problems for the entire application (i.e. the converter and/or the electronic device supplied thereby).

Fast transitions may be desirable in order to quickly respond to changes in output load current and avoid regulation losses due to, for example, limited output current capacity of a single phase (e.g., the main phase) of the converter.

Conversely, a transition that occurs too quickly may result in an undesirable response (e.g., spike) in the output voltage. Thus, the timing requirements of the transitions should be subject to trade-offs in order to provide improved performance under various different operating conditions of the converter (e.g., different values of input voltage Vin, output voltage Vout, output load current, and possibly process, voltage and temperature (PVT) variations, etc.).

Despite the extensive activities in the art, other improved solutions are desired.

There is a need in the art to provide such an improved solution.

Disclosure of Invention

One or more embodiments may relate to a corresponding multi-phase converter device.

One or more embodiments may relate to a corresponding method of operating a circuit or a multiphase converter device.

One or more embodiments may provide a circuit configured to generate a control signal for a secondary switching stage in a multiphase converter device, wherein the circuit is configured to generate the control signal for the secondary switching stage in dependence on the control signal for the primary switching stage.

One or more embodiments may thus help to provide selected timing for powering up and down the secondary phases of a multi-phase converter, thereby matching wide output current capacity requirements with small transients at the output voltage during transitions.

One or more embodiments may help to provide such transition timing that is not dependent on the operating conditions of the converter.

Drawings

One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings, in which:

FIG. 1 is an exemplary circuit block diagram of a multi-phase converter;

FIG. 2 is an exemplary circuit diagram of a circuit for managing state transitions in a multi-phase converter; and is

Fig. 3 is an exemplary circuit diagram of another circuit for managing state transitions in a multi-phase converter.

Detailed Description

In the following description, one or more specific details are illustrated, which are intended to provide a thorough understanding of examples of embodiments of the present description. Embodiments may be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail so that aspects of the embodiments will not be obscured.

Reference to "one embodiment" or "an embodiment" within the framework of the specification is intended to indicate that a particular configuration, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, phrases such as "in an embodiment" or "in one embodiment" that may be present in one or more points of the specification do not necessarily refer to one and the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Throughout the drawings attached hereto, like parts or elements are indicated with like reference numerals/numerals, and corresponding descriptions will not be repeated for the sake of brevity.

Reference signs used herein are provided merely for convenience and therefore do not limit the extent of protection or the scope of the embodiments.

By way of introduction of a detailed description of exemplary embodiments, reference may first be made to fig. 1, which fig. 1 illustrates an exemplary circuit block diagram of a two-phase DC/DC converter. In the present detailed description, reference is made to the exemplary case of a two-phase converter only by way of simplification. One or more embodiments may generally be applied to multi-phase converters having more than two phases (i.e., a primary phase and at least one secondary phase).

As illustrated in fig. 1, the two-phase DC/DC converter 10 may include a first switching stage 100, a second switching stage 100', and a control circuit coupled thereto.

Each of the switching stages 100 and 100' may include a respective half-bridge arrangement including a high-side switch and a low-side switch (e.g., MOS transistors), a respective reactive component (e.g., an inductor) coupled to the half-bridge arrangement, and a respective drive circuit 1000, 1000' coupled to the high-side switch and the low-side switch to control the switches thereof according to a respective PWM modulation signal PWM, PWM '. The switching stage 100, 100' may be configured to receive an input voltage Vin and generate an output voltage Vout of the converter 10. For example, in one or more embodiments, the switching stages 100, 100' may be implemented according to conventional buck, boost, or buck-boost topologies.

The control circuit in the converter 10 may include a (e.g., resistive) voltage divider 102 configured to generate the feedback voltage signal Vfb by dividing the output voltage Vout. The control circuit may comprise an error amplifier 104, the error amplifier 104 being configured to determine a difference between the feedback voltage signal Vfb and the reference voltage signal Vref, thereby generating a first control signal Vc indicative of the determined difference for controlling the operation of the converter 10.

In the first comparator 106, the first control signal Vc may be compared with a periodic ramp signal (e.g., a triangular or sawtooth signal) to generate a first output oscillation signal PWM (e.g., a first pulse width modulation signal) for controlling the switching operation of the first switching stage 100.

In a two-phase converter 10 as illustrated in fig. 1, the first control signal Vc may be provided at an input of the phase management circuit block 108, wherein the phase management circuit block 108 is configured to generate the second control signal Vc' at an output. In the second comparator 106', the second control signal Vc' may be compared with the periodic ramp signal, thereby generating a corresponding output oscillation signal PWM 'for controlling the switching operation of the second switching stage 100'. Thus, in one or more embodiments, phase management circuit block 108 may be configured to generate second control signal Vc' so as to cause the timing of transitions between different operating states of converter 10 (i.e., operating in only one phase, or in two phases in parallel) to be independent of the operating conditions of the converter.

As illustrated in fig. 1, the signals PWM and PWM' may be provided as inputs to a Finite State Machine (FSM) circuit block 110 in the converter 10, the finite state machine 110 may be configured to receive input signals from:

a first Discontinuous Mode Detector (DMD) comparator 112 configured to detect whether the inductor current in the first switching stage 100 reaches a certain threshold (e.g., zero),

a second DMD comparator 112 'configured to detect whether the inductor current in the second switching stage 100' reaches a certain threshold (e.g., zero),

a first comparator skip block 114 configured to control a transition of the first phase to the pulse skip mode,

a second comparator skip block 114' configured to control a transition of the second phase to the pulse skip mode,

a first overcurrent protection OCP circuit block 116 configured to limit the inductor current in the first switching stage 100 to a maximum value,

a second OCP circuit block 116 'configured to limit the inductor current in the second switching stage 100' to a maximum value, an

Signals external to the converter 10 (e.g., digital signals), such as the enable signal EN, the clock signal CK, and the TEST signal TEST.

The finite state machine circuit block 110 may be configured to control the ramp generator circuit block 118, and the ramp generator circuit block 118 may generate a ramp signal for application to the first comparator 106 and the second comparator 106'. The ramp generator circuit block 118 may receive additional input signals from a high side current sensing circuit block 120, which high side current sensing circuit block 120 may be configured to sense the current flowing in the first and second switching stages 100, 100'.

Finite state machine circuit block 110 may additionally be configured to control loop suppressor circuit block 122, which loop suppressor circuit block 122 is configured to be powered up as a result of the respective phase entering a pulse skipping mode.

Fig. 2 is an exemplary circuit diagram of a possible implementation of the phase management circuit block 108, the phase management circuit block 108 being used to generate the second control signal Vc' and manage the transitions between the operating states of the two-phase converter 10.

The phase management circuit block 108 as illustrated in fig. 2 may include an input node 1080 for receiving the first control signal Vc and an output node 1082 for providing a second control signal Vc', wherein:

the output node 1082 may be selectively coupled to the input node 1080 via an electronic switch SW1,

the output node 1082 may be selectively coupled to the intermediate node 1084 via an electronic switch SW2, and

a capacitive component C (e.g., a capacitor) is coupled between the intermediate node 1084 and a reference (ground) node GND.

The capacitor C is configured to:

is charged by means of a current generator G1, which current generator G1 can be selectively coupled between the supply node Vsupply and the intermediate node 1084 via an electronic switch SW3, to inject a constant reference current Iref into the capacitor C; and

discharged by means of a current generator G2, which current generator G2 can be selectively coupled between the intermediate node 1084 and a reference (ground) node via an electronic switch SW4, to sink a constant reference current Iref from the capacitor C.

Thus, the operation of the circuit 108 as illustrated in fig. 2 may be summarized as follows:

during the time period in which the secondary phase of the converter 10 is activated, the switches SW2 and SW3 may be closed and the switches SW1 and SW4 may be opened, resulting in an increase of the secondary control signal Vc' from 0V to Vc (where Vc is the steady-state value of the control voltage of the entire loop of the converter 10) and a ramp with a constant slew rate due to the capacitor 10 being charged with a constant current Iref;

when the power-up transition of the secondary phase is terminated (i.e. when Vc '═ Vc; the activation period ends), switch SW2 may be opened and switch SW1 may be closed, thereby coupling output node 1082 to input node 1080 and propagating the main control voltage Vc of the entire DC/DC control loop to the second comparator 106';

during the period of deactivation of the secondary phase, switches SW2 and SW4 may be closed, while switches SW1 and SW3 may be open, resulting in the secondary control signal Vc' decreasing from Vc to 0V and having a ramp of constant slew rate due to the capacitor C being discharged at constant current Iref; and is

When the power-down transition of the secondary phase is terminated (i.e. when Vc '═ 0V; the end of the deactivation period), switches SW2 and SW4 may be kept closed to maintain the secondary control signal Vc' ═ 0V.

Alternatively, the capacitor C may be charged/discharged using a switched current, for example, in case the total value to be obtained is lower than the reference current Iref available in the system. The switching current may be obtained by arranging an electronic switch, which is alternately activated and deactivated (i.e. rendered conductive and non-conductive, respectively) with a certain duty cycle D (where D is comprised between 0 and 1), in series with a current generator providing the reference current Iref. Thus, the average value of the switching current may be equal to Iref D, and thus lower than Iref.

The phase management circuit 108 as illustrated in fig. 2 may not allow to achieve a well-defined timing for the power-up and power-down transitions of the second phase of the converter 10, in particular in case of a change of the operating point of the converter due to changes of the input voltage Vin, the output voltage Vout and the output current.

In practice, variations in operating conditions may result in variations in the control voltage signal Vc. The circuit as illustrated in fig. 2 may operate with power-up and power-down timings proportional to the value of the control signal Vc itself. Thus, in a circuit as illustrated in fig. 2, the total transition time may not be optimized, which may require design tradeoffs that may result in poor output voltage regulation performance, or poor performance with rapid recovery of changes in output current capacity requests.

One or more embodiments as illustrated in fig. 3 may provide an improvement in this regard, providing a duration of power-up and power-down transitions of the secondary phase(s) that is independent of the constant slew rate ramping of Vc' but is related to the variable slew rate ramping.

In particular, in one or more embodiments as illustrated in fig. 3, the slew rate of the control signal Vc' during power-up and power-down transitions may be a function of (e.g., proportional to) the control voltage Vc itself. This may be obtained, for example, by charging and/or discharging the capacitor C with a variable current generated as a function of the control voltage Vc.

In particular, fig. 3 is an example of a possible circuit implementation for generating a charge/discharge current as a function of Vc, but other implementations are possible. As illustrated in fig. 3 (where elements and components similar to those illustrated in fig. 2 have been indicated with similar reference numerals), during activation of the secondary phase of the converter 10 (i.e., with switches SW2 and SW3 closed and switches SW1 and SW4 open), the capacitor C may be charged with a current I3 injected into the node 1084, where the value of I3 depends on the value of the control voltage Vc.

In particular, phase management circuit block 108 in accordance with one or more embodiments may include a transconductance amplifier circuit arrangement TA (e.g., including an operational amplifier 1086, a transistor M1, and a resistor R arranged as shown in fig. 3) configured as a voltage-to-current converter to generate a current I1, the current I1 being a function of a value of a control voltage Vc (e.g., proportional to Vc: I1 ═ Vc/R). The current I1 generated by the transconductance amplifier TA may be mirrored by means of a current mirror circuit arrangement comprising transistors M2 and M4, providing a current I3 n I1 n Vc/R, where n is a mirroring factor depending on the size of the transistors M2 and M4.

Similarly, during deactivation of the secondary phase of the converter 10 (i.e., with switches SW2 and SW4 closed and switches SW1 and SW3 open), the capacitor C may be discharged with a current I4 sunk from the node 1084, the value of the current I4 depending on the value of the control voltage Vc. The current I1 generated by the transconductance amplifier TA may be mirrored by means of a cascaded arrangement of current mirror circuits (e.g. a first current mirror comprising transistors M2, M3 and a second current mirror comprising transistors M5, M6) providing a current I4M I1M Vc/R, where M is a mirroring factor depending on the size of the transistors M2, M3, M5 and M6.

Thus, one or more embodiments according to fig. 3 may provide power-up and power-down sequences that are independent of the operating conditions of the converter device 10, as long as they may be independent of the value of the control voltage Vc.

For example, where Vc is high, the current generated to control the slew rate of Vc' (i.e., I3 or I4) may be accordingly high, thereby compensating for the high value of Vc to be achieved. In the case where Vc is low, the current generated to control the slew rate of Vc' may be low, thereby compensating for the low value of Vc to be reached, resulting in power-up and power-down sequences (t, respectively) that are not dependent on the value of Vc_upAnd t_down) As long as:

such a transition time t is not dependent on Vc, except_upAnd t_downIt may also be adjusted by selecting the value of the resistor R and/or the values of the mirror factors n and m to help set the duration of the transition of the converter device 10 to provide improved performance in terms of output current capacity response and output voltage regulation.

In one or more embodiments, the transition time t_upAnd t_downBy providing a variable power supply in the circuit of figure 3The container C and/or the variable resistor R are adjusted "in real time".

Again, it should be noted that fig. 3 provides a non-limiting example of a possible implementation of a circuit for generating a charging current I3 and/or a discharging current I4 depending on the value of the control voltage Vc, which current is used to provide a transition timing of the multiphase converter device that is almost independent of Vc itself, and therefore of the operating conditions of the converter device. Alternative embodiments are possible

For example, in one or more embodiments, the values of the charge current I3 (e.g., flowing in transistor M4) and/or the discharge current I4 (e.g., flowing in transistor M6) may be set by a digital controller configured to sense the control signal Vc and select the values of the charge and discharge currents as a function thereof.

Accordingly, one or more embodiments may provide the following advantages over existing solutions:

the possibility of generating a fixed and constant power-up/power-down sequence of the secondary phase under different operating conditions, since the charge/discharge current depends on (e.g. is proportional to) the control voltage Vc;

-the possibility to select the power-up/power-down sequence in order to avoid variations in the output voltage and/or current capacity problems:

i) in order to avoid variations in the output voltage, the time may be chosen to be long enough to prevent ripple phenomena on the output voltage,

ii) in order to provide a satisfactory output current capacity, a time may be selected that is short enough to prevent the converter from operating with insufficient output current capacity;

the architecture of one or more embodiments described herein may provide improved flexibility of use and may be used with different trigger signals to manage activation and deactivation of a second phase (or secondary phase in general), for example:

a signal provided by an output current sensor (e.g., a comparator circuit) configured to manage activation and deactivation of the secondary phase in accordance with an output current requested by the application load,

a signal provided by an input voltage sensor (e.g., a comparator circuit) configured to manage the secondary phase as a function of the converter input voltage,

-a signal provided by a control voltage (Vc) comparator configured to power up or power down the secondary phase in dependence of a converter control voltage, the converter control voltage depending on the behavior of the converter, an

-external trigger signals and/or other application dependent signals.

As exemplified herein, a circuit (e.g., 108) may be configured to generate a secondary switching stage control signal (e.g., Vc') for a multiphase converter device (e.g., 10). The multiphase converter device includes a primary switching stage (e.g., 100) and at least one secondary switching stage (e.g., 100'). Such circuitry may include:

an input node (e.g. 1080) configured to receive a control signal (e.g. Vc) for a main switching stage of a multiphase converter device,

an output node (e.g. 1082) configured to provide the secondary switching stage control signal for the at least one secondary switching stage of a multiphase converter device,

a first electronic switch (e.g. SW1) configured to couple the output node to the input node as a result of the at least one secondary switching stage being activated, an

-a second electronic switch (e.g. SW2) configured to couple the output node to a capacitive component (e.g. capacitor C) during activation or deactivation of the at least one secondary switching stage.

The circuit may include: a first current generation circuit configured to generate a first current (e.g., I3) for selectively (e.g., SW3) charging a capacitive component during activation of the at least one secondary switching stage; and a second current generation circuit configured to generate a second current (e.g., I4) for selectively (e.g., SW4) discharging the capacitive component during deactivation of the at least one secondary switching stage. The first and second current generating circuits may be configured to generate at least one of the first and second currents in dependence on the control signal received at the input node.

As exemplified herein, the first and second current generating circuits may be configured to generate the at least one of the first and second currents in proportion to the control signal.

As exemplified herein, the circuitry may comprise:

a transconductance amplifier arrangement (e.g., TA) coupled to the input node and configured to generate a control current (e.g., I1) according to a control signal received at the input node,

a first current mirror circuit block (e.g. M2, M4) configured to mirror the control current to generate the first current, an

A second current mirror circuit block (e.g. M2, M3, M5, M6) configured to mirror the control current to generate the second current.

As exemplified herein, the circuit may include a digital controller circuit block configured to sense the control signal and set a value of at least one of the first current and the second current according to the sensed control signal.

As exemplified herein, a multiphase converter device can include a main switching stage controllable by a main control signal and at least one secondary switching stage controllable by a respective control signal, wherein the at least one secondary switching stage can be activated to provide current in parallel with the main switching stage. The multi-phase converter device may comprise at least one circuit according to one or more embodiments configured to generate the control signal for the at least one secondary switching stage in dependence on the main control signal.

As exemplified herein, a multi-phase converter device can include a plurality of secondary switching stages according to one or more embodiments and a plurality of circuits configured to generate respective control signals for secondary switching stages of the plurality of secondary switching stages.

As exemplified herein, a method of operating a circuit according to one or more embodiments or a multiphase converter device according to one or more embodiments may comprise:

-receiving a control signal for a main switching stage of a multiphase converter device at an input node of the circuit,

-coupling an output node of the circuit to an input node of the circuit as a result of the at least one secondary switching stage being activated,

-coupling an output node of the circuit to a capacitive component during activation or deactivation of the at least one secondary switching stage,

-generating a first current for selectively charging the capacitive component during activation of the at least one secondary switching stage and a second current for selectively discharging the capacitive component during deactivation of the at least one secondary switching stage, and

-generating at least one of the first current and the second current from the control signal received at an input node of the circuit.

Without prejudice to the underlying principles, the details and the embodiments may vary, even significantly, with respect to what has been described by way of example only, without departing from the scope of protection.

The scope of protection is defined by the appended claims.

The claims are an integral part of the technical teaching provided herein for the examples.

Claims

1. A control circuit configured to control operation of a multiphase converter device including a primary switching stage and a secondary switching stage, the control circuit comprising:

an input node configured to receive a main control signal for the main switching stage;

an output node configured to provide a secondary control signal for the secondary switching stage;

a first electronic switch configured to couple the output node to the input node after completion of activation of the secondary switching stage;

a second electronic switch configured to couple the output node to a capacitive component during a period of activation of the secondary switching stage and during a period of deactivation of the secondary switching stage;

a first current generation circuit configured to generate a first current for selectively charging the capacitive component during the time period of activation of the secondary switching stage; and

a second current generation circuit configured to generate a second current for selectively discharging the capacitive component during the time period of deactivation of the secondary switching stage.

2. The control circuit of claim 1, wherein the first current is generated according to the master control signal.

3. The control circuit of claim 2, wherein the first current is proportional to a voltage of the main control signal.

4. The control circuit of claim 1, wherein the second current is generated according to the master control signal.

5. The control circuit of claim 4, wherein the second current is proportional to a voltage of the main control signal.

6. The control circuit of claim 1, wherein the first current generated by the first current generating circuit is proportional to the main control signal, and wherein the second current generated by the second current generating circuit is proportional to the main control signal.

7. The control circuit of claim 1, further comprising:

a transconductance amplifier coupled to the input node and configured to generate a control current according to the main control signal received at the input node; and is

Wherein the first current generation circuit comprises a first current mirror circuit configured to mirror the control current to generate the first current; and is

Wherein the second current generation circuit comprises a second current mirror circuit block configured to mirror the control current to generate the second current.

8. The control circuit of claim 1, further comprising a digital controller circuit configured to sense the master control signal and set a value of at least one of the first current and the second current according to the sensed master control signal.

9. A multiphase converter apparatus comprising:

a main switching stage controllable by a main control signal;

a secondary switching stage controllable by a secondary control signal;

wherein the secondary switching stage is activatable to provide current in parallel with the primary switching stage;

a control circuit, comprising:

an input node configured to receive the master control signal;

an output node configured to provide the secondary control signal;

10. The multiphase converter device of claim 9, wherein the first current is generated in accordance with the master control signal.

11. The multiphase converter apparatus of claim 10, wherein the first current is proportional to a voltage of the main control signal.

12. The multiphase converter device of claim 9, wherein the second current is generated in accordance with the master control signal.

13. The multiphase converter apparatus of claim 12, wherein the second current is proportional to a voltage of the main control signal.

14. The multiphase converter device of claim 9, wherein the first current generated by the first current generation circuit is proportional to the main control signal, and wherein the second current generated by the second current generation circuit is proportional to the main control signal.

15. The multiphase converter device of claim 9, further comprising:

16. The multiphase converter device of claim 9, further comprising a digital controller circuit configured to sense the main control signal and set a value of at least one of the first current and the second current according to the sensed main control signal.

17. A multi-phase converter circuit comprising:

a main switching stage coupled to the output node and controlled by the first pulse width modulation signal for switching;

a secondary switching stage coupled to the output node and controlled by a second pulse width modulation signal for switching;

a first circuit configured to determine a difference between a voltage at the output node and a reference voltage and generate a first control voltage;

a first comparator configured to compare the first control voltage with a first ramp signal to generate the first pulse width modulation signal;

a second comparator configured to compare a second control voltage with a second ramp signal to generate the second pulse width modulation signal;

a second circuit configured to generate the second control voltage, wherein the second circuit causes a gradual increase in a level of the second control voltage to a level of the first control voltage in response to a change in the secondary switching stage from a de-actuated state to an actuated state.

18. The circuit of claim 17, wherein the second circuit comprises:

an output node for outputting the second control voltage;

a capacitor;

a first switch that selectively couples the capacitor to the output node in response to the change in the secondary switching stage from the de-actuated state to the actuated state; and

a current source configured to generate a charging current applied to charge the capacitor in response to the change in the secondary switching stage from the de-actuated state to the actuated state.

19. The circuit of claim 18, wherein the second circuit further comprises:

an input node receiving the first control voltage; and

a second switch selectively coupling the input node to the output node in response to gradually increasing a level of the second control voltage to the level of the first control voltage.

20. The circuit of claim 19, wherein the first switch is controlled to decouple the capacitor from the output node.

21. The circuit of claim 18, wherein the current source comprises a voltage-to-current converter circuit having: an input configured to receive the first control voltage; and an output to generate the charging current in accordance with the level of the first control voltage.

22. The circuit of claim 18, wherein the current source comprises a fixed current source that generates the charging current.

23. The circuit of claim 18, wherein the current source comprises a variable current source that generates the charging current proportional to the level of the first control voltage.

24. The circuit of claim 17, wherein the second circuit is further configured to cause the level of the second control voltage to gradually decrease from the level of the first control voltage in response to a change in the secondary switching stage from the actuated state to the de-actuated state.

25. The circuit of claim 24, wherein the second circuit comprises:

an output node for outputting the second control voltage;

a capacitor;

a first switch that selectively couples the capacitor to the output node in response to the change in the secondary switching stage from the actuated state to the de-actuated state; and

a current source configured to generate a discharge current applied to discharge the capacitor in response to the change in the secondary switching stage from the actuated state to the de-actuated state.

26. The circuit of claim 25, wherein the first switch is controlled to decouple the capacitor from the output node.

27. The circuit of claim 25, wherein the current source comprises a voltage-to-current converter circuit having: an input configured to receive the first control voltage; and an output to generate the discharge current in accordance with the level of the first control voltage.

28. The circuit of claim 25, wherein the current source comprises a fixed current source that generates the discharge current.

29. The circuit of claim 25, wherein the current source comprises a variable current source that generates the discharge current proportional to the level of the first control voltage.