CN112185973B - Memory, manufacturing method and operation method of memory - Google Patents

Abstract

The invention provides a memory, a manufacturing method and an operation method of the memory, wherein the memory comprises a first floating gate structure, a second floating gate structure and an erasing gate, wherein the first floating gate structure, the second floating gate structure and the erasing gate are formed on a semiconductor substrate, and the erasing gate is positioned between the first floating gate structure and the second floating gate structure; a first oxide layer and a second oxide layer formed on the semiconductor substrate. By forming the erase gate between the first floating gate structure and the second floating gate structure, an erase voltage can be applied to the erase gate and zero voltage can be applied to the first word line and the second word line when the memory is erased, so that electrons can flow from the first floating gate structure to the erase gate or from the second floating gate structure to the erase gate when the memory is erased, and the electric field strength of the first oxide layer and the second oxide layer can be reduced, thereby improving the durability of the memory.

Description

Memory, method for manufacturing memory, and method for operating memory

Technical Field

The present invention relates to the field of semiconductor technology, and in particular to a memory, a manufacturing method of the memory, and an operating method thereof.

Background technique

Electrically Erasable Programmable Read-Only Memory (EEPROM) is a long-life non-volatile memory (it can still maintain the stored data information when the power is off). Its main feature is that it can maintain the stored information for a long time without power. It has many advantages such as high integration, fast access speed and easy erasure. Therefore, it has been widely used in many fields such as microcomputers and automatic control.

Please refer to FIG1, which is a schematic diagram of the structure of a memory (EEPROM) in the prior art, including: a semiconductor substrate 10, a first floating gate 20a and a second floating gate 20b located on the semiconductor substrate, a dielectric layer 30 located on the first floating gate 20a and the second floating gate 20b, and a source line 40 located between the first floating gate 20a and the second floating gate 20b; a first word line 60a located on a side of the first floating gate 20a away from the source line, and a second word line 60b located on a side of the second floating gate 20b away from the source line 40, and an oxide layer 50 is formed between the semiconductor substrate 10 and the first word line 60a and the second word line 60b. When erasing the memory, a word line erasing method is adopted. Specifically, a zero voltage is applied to the source line 40, that is, the voltage of the source line 40 is 0, and a voltage is applied to the first word line 60a or the second word line 60b, for example, a voltage of 10V is applied, so that there is a certain voltage difference between the word line 60 and the source line 40. Driven by the voltage difference, electrons will flow from the first floating gate 20a to the word line 60a or from the second floating gate 20b to the word line 60b, thereby completing the erasing operation. In order to achieve the erasing effect, the erasing method needs to apply a higher voltage to the first word line 60a or the second word line 60b, which will affect the electric field strength of the oxide layer 50 and increase the electric field strength of the oxide layer 50, thereby reducing the durability of the memory.

Summary of the invention

The object of the present invention is to provide a memory, a method for manufacturing the memory and an operating method thereof, so as to solve the problem that the electric field strength of the oxide layer increases due to excessive voltage applied to the word line during the erasing process of the memory, and the durability of the memory is low.

In order to solve the above technical problems, the present invention provides a memory, comprising:

Semiconductor substrate;

A first floating gate structure, a second floating gate structure and an erase gate are formed on the semiconductor substrate, wherein the erase gate is located between the first floating gate structure and the second floating gate structure;

A first oxide layer and a second oxide layer are formed on the semiconductor substrate, wherein the first oxide layer is located on a side of the first floating gate structure away from the erase gate, and the second oxide layer is located on a side of the second floating gate structure away from the erase gate;

A first word line is formed on one side of the first floating gate structure and covers the first oxide layer, and a second word line is formed on one side of the second floating gate structure and covers the second oxide layer.

Optionally, in the memory, the memory further includes:

A first spacer layer, located on the first floating gate structure;

A second spacer layer, located on the second floating gate structure;

A third spacer layer, covering the first floating gate structure and a side wall of the first spacer layer away from the erase gate;

a fourth spacer layer, covering the second floating gate structure and a side wall of the second spacer layer away from the erase gate;

a fifth spacer layer, covering a side wall of the first word line away from the first floating gate structure;

a sixth spacer layer, covering a side wall of the second word line away from the second floating gate structure;

A source line located in the semiconductor substrate aligned with the erase gate;

A tunneling oxide layer, covering the source line, the first floating gate structure and a side wall of the second floating gate structure close to the erase gate, and extending to cover a side wall of the first spacer layer and the second spacer layer;

A first bit line is located in the semiconductor substrate on a side of the five sidewall layers away from the first word line;

The second bit line is located in the semiconductor substrate at a side of the sixth wall layer away from the second word line.

Optionally, in the memory, the first floating gate structure includes a first floating gate oxide layer and a first floating gate layer stacked in sequence, and the second floating gate structure includes a second floating gate oxide layer and a second floating gate layer stacked in sequence.

Based on the same inventive concept, the present invention also provides a method for manufacturing a memory, the method for manufacturing the memory comprising:

Providing a semiconductor substrate;

forming a first floating gate structure, a second floating gate structure and an erase gate on the semiconductor substrate, wherein the erase gate is located between the first floating gate structure and the second floating gate structure;

forming a first oxide layer and a second oxide layer on the semiconductor substrate, wherein the first oxide layer is located on a side of the first floating gate structure away from the erase gate, and the second oxide layer is located on a side of the second floating gate structure away from the erase gate;

A first word line and a second word line are formed, wherein the first word line is located at one side of the first floating gate structure and covers the first oxide layer, and the second word line is located at one side of the second floating gate structure and covers the second oxide layer.

Optionally, in the method for manufacturing the memory, the method for forming the first floating gate structure, the second floating gate structure and the erase gate includes:

forming a floating gate structure layer on the semiconductor substrate;

forming a dielectric layer on the floating gate structure layer, wherein the dielectric layer has a first opening penetrating in a thickness direction, and the first opening exposes a portion of the floating gate structure layer;

Forming a first spacer layer and a second spacer layer, wherein the first spacer layer and the second spacer layer are both located above the exposed floating gate structure layer and cover two side walls of the first opening respectively;

Using the first spacer layer and the second spacer layer as masks, etching the exposed floating gate structure layer to form a second opening exposing the semiconductor substrate;

Performing an ion implantation process on the exposed semiconductor substrate to form a source line;

forming a tunneling oxide layer, wherein the tunneling oxide layer covers the source line and extends to cover the sidewalls of the second opening and the first opening;

forming the erase gate, wherein the erase gate covers the tunnel oxide layer and fills the second opening and the first opening;

removing the dielectric layer to expose a portion of the floating gate structure layer;

Etching the exposed floating gate structure layer to form a first floating gate structure and a second floating gate structure;

Wherein, after etching the exposed floating gate structure layer, the first floating gate structure exposes a first portion of the semiconductor substrate on a side away from the erase gate, and the second floating gate structure exposes a second portion of the semiconductor substrate on a side away from the erase gate; the first oxide layer is located on the exposed first portion of the semiconductor substrate, and the second oxide layer is located on the exposed second portion of the semiconductor substrate.

Optionally, in the method for manufacturing the memory, before forming the first oxide layer and the second oxide layer, the method for manufacturing the memory further includes:

forming a third spacer layer, wherein the third spacer layer covers the first floating gate structure and a side wall of the first spacer layer close to the first word line;

A fourth spacer layer is formed, where the fourth spacer layer covers the second floating gate structure and a side wall of the second spacer layer close to the second word line.

Optionally, in the memory manufacturing method, after forming the first word line and the second word line, the memory manufacturing method further includes:

forming a fifth spacer layer, wherein the fifth spacer layer covers a side wall of the first word line away from the first floating gate structure;

forming a sixth spacer layer, wherein the sixth spacer layer covers a side wall of the second word line away from the second floating gate structure;

forming a first bit line, wherein the first bit line is located in the semiconductor substrate on a side of the five sidewall layers away from the first word line;

forming a second bit line, wherein the second bit line is located in the semiconductor substrate at a side of the sixth wall layer away from the second word line; and

forming a first bit line contact structure, wherein the first bit line contact structure is formed on the first bit line;

A second bit line contact structure is formed, wherein the second bit line contact structure is formed on the second bit line.

Optionally, in the method for manufacturing the memory, the first floating gate structure includes a first floating gate oxide layer and a first floating gate layer stacked in sequence, and the second floating gate structure includes a first floating gate oxide layer and a second floating gate layer stacked in sequence.

Based on the same inventive concept, the present invention further provides a method for operating a memory, the method for operating the memory comprising the memory provided by the present invention;

Performing an erasing operation on the memory, applying an erasing voltage to the erase gate, and applying a zero voltage to the first word line, the second word line, the first bit line, the second bit line, and the source line;

Performing a programming operation on the memory, applying a first voltage to the first word line, applying a second voltage to the first bit line, applying a third voltage to the second bit line, applying a fourth voltage to the source line and the erase gate, and applying a zero voltage to the second word line;

A read operation is performed on the memory, a fifth voltage is applied to the first word line and the second word line, a sixth voltage is applied to the first bit line, and a zero voltage is applied to the second bit line, the source line and the erase gate to perform a read operation on the first floating gate structure.

Optionally, in the operation method of the memory, the erase voltage is 10V~14V; the first voltage is 1V~2V, the second voltage is 0.1V~0.8V, the third voltage is 1V~3V, the fourth voltage is 5V~9V, the fifth voltage is 1V~3V, and the sixth voltage is 0.5V~2V.

In the memory, the manufacturing method and the operating method of the memory provided by the present invention, the memory includes: a first floating gate structure, a second floating gate structure and an erase gate formed on a semiconductor substrate, the erase gate is located between the first floating gate structure and the second floating gate structure, and by forming the erase gate between the first floating gate structure and the second floating gate structure, the first floating gate structure and the second floating gate structure can be erased by using an erase gate erasing method, so that electrons can flow from the first floating gate structure to the erase gate or from the second floating gate structure to the erase gate. The memory also includes: a first oxide layer and a second oxide layer formed on the semiconductor substrate, the first oxide layer is located on a side of the first floating gate structure away from the erase gate, and the second oxide layer is located on a side of the second floating gate structure away from the erase gate; a first word line formed on one side of the first floating gate structure and covering the first oxide layer, and a second word line formed on one side of the second floating gate structure and covering the second oxide layer. Due to the presence of the erase gate, electrons can flow from the first floating gate structure to the erase gate or from the second floating gate structure to the erase gate, thereby reducing the electric field strength of the first oxide layer and the second oxide layer. When the memory is erased, an erase voltage may be applied to the erase gate, and a zero voltage may be applied to the first word line and the second word line, thereby implementing an erase operation on the first floating gate structure and the second floating gate structure using an erase gate erasing method, thereby reducing the electric field strength of the first oxide layer and the second oxide layer, and thereby improving the durability of the memory.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of the structure of a memory device in the prior art;

FIG2 is a schematic diagram of the structure of a memory provided by an embodiment of the present invention;

3 to 16 are schematic diagrams of structures formed in a method for manufacturing a memory provided by an embodiment of the present invention;

The reference numerals are described as follows:

10-semiconductor substrate; 20a-first floating gate; 20b-second floating gate; 30-dielectric layer; 40-source line; 50-oxide layer; 60a-first word line; 60b-second word line;

100-semiconductor substrate; 101-floating gate structure layer; 102-floating gate oxide layer; 103-floating gate layer; 104-dielectric layer; 105-first opening; 106-second opening; 110-first floating gate structure; 111-first floating gate oxide layer; 112-first floating gate layer; 113-first spacer layer; 114-second spacer layer; 120-second floating gate structure; 121-second floating gate oxide layer; 122-second floating gate layer; 130-source line; 1 40-tunneling oxide layer; 150-erase gate; 160-third side wall layer; 161-fourth side wall layer; 162-oxidation material layer; 170-first oxide layer; 171-second oxide layer; 172-word line material layer; 180-first word line; 181-second word line; 182-fifth side wall layer; 183-sixth side wall layer; 190-first bit line; 191-second bit line; 192-first bit line contact structure; 193-second bit line contact structure.

Detailed ways

The memory, the manufacturing method of the memory, and the operating method of the memory proposed in the present invention are further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

Please refer to FIG2, which is a schematic diagram of the structure of a memory provided by an embodiment of the present invention. As shown in FIG2, the present invention provides a memory, the memory comprising: a semiconductor substrate 100, a first floating gate structure 110, a second floating gate structure 120 and an erase gate 150 formed on the semiconductor substrate 100, the erase gate 150 being located between the first floating gate structure 110 and the second floating gate structure 120; a first oxide layer 170 and a second oxide layer 171 formed on the semiconductor substrate 100, the first oxide layer 170 being located on a side of the first floating gate structure 110 away from the erase gate 150, and the second oxide layer 171 being located on a side of the second floating gate structure 120 away from the erase gate 150; a first word line 180 formed on one side of the first floating gate structure 110 and covering the first oxide layer 170, and a second word line 181 formed on one side of the second floating gate structure 120 and covering the second oxide layer 171.

When the memory is erased, an erase voltage may be applied to the erase gate 150, and a zero voltage may be applied to the first word line 180 and the second word line 181, so that electrons may flow from the first floating gate structure 110 to the erase gate 150 or from the second floating gate structure 120 to the erase gate 150. Thus, the electric field strength of the first oxide layer 170 and the second oxide layer 171 may be reduced, thereby improving the durability of the memory.

Specifically, the first floating gate structure 110 includes a first floating gate oxide layer 111 and a first floating gate layer 112 stacked in sequence, and the second floating gate structure 120 includes a second floating gate oxide layer 121 and a second floating gate layer 122 stacked in sequence. The first floating gate oxide layer 111 is used for isolation between the first floating gate layer 112 and the semiconductor substrate 100, and the second floating gate oxide layer 121 is used for isolation between the second floating gate layer 122 and the semiconductor substrate 100. The first floating gate oxide layer 111 and the second floating gate oxide layer 121 may be, for example, silicon oxide; the first floating gate layer 112 and the second floating gate layer 122 may be, for example, polysilicon, both of which can capture or lose electrons in the memory, so that the memory can have an erase function.

The memory further includes a source line 130 , which is located in the semiconductor substrate 100 aligned with the erase gate 150 , that is, the source line 130 is located in the semiconductor substrate 100 between the first floating gate structure 110 and the second floating gate structure 120 , and the erase gate 150 is located above the source line 130 .

The memory further includes a first spacer layer 113 and a second spacer layer 114. The first spacer layer 113 is located on the first floating gate structure 110, and the second spacer layer 114 is located on the second floating gate structure 120. Both the first spacer layer 113 and the second spacer layer 114 are silicon oxide layers, which have an isolation function.

Furthermore, the memory also includes a tunneling oxide layer 140, which covers the source line 130, the first floating gate structure 110 and a side wall of the second floating gate structure 120 close to the erase gate 150, and extends in the height direction to cover a side wall of the first sidewall layer 113 and the second sidewall layer 114, that is, the tunneling oxide layer 140 is located between the erase gate 150 and the first floating gate structure 110, the second floating gate structure 120 and the source line 130, and the tunneling oxide layer 140 can isolate the erase gate 150 from the first floating gate structure 110, the second floating gate structure 120 and the source line 130.

Furthermore, a third spacer 160 is formed between the first word line 180 and the first floating gate structure 110. Specifically, the third spacer 160 covers the first floating gate structure 110 and a side wall of the first spacer 113 away from the erase gate; the third spacer 160 may be, for example, a silicon oxide layer, and the third spacer 160 is used for isolation between the first word line 180 and the first floating gate structure 110.

A fourth spacer 161 is formed between the second word line 181 and the second floating gate structure 120. Specifically, the fourth spacer 161 covers the second floating gate structure 120 and a side wall of the second spacer 114 away from the erase gate 150, and is close to the second word line 182. The fourth spacer 161 may be, for example, a silicon oxide layer, and is used for isolation between the second word line 181 and the second floating gate structure 120.

Furthermore, the memory also includes a fifth spacer layer 182 and a sixth spacer layer 183 , the fifth spacer layer 182 covers a side wall of the first word line 180 away from the third spacer layer 160 ; the sixth spacer layer 183 covers a side wall of the second word line 182 away from the fourth spacer layer 161 .

In addition, the memory also includes a first bit line 190 and a second bit line 191, the first bit line 190 is located in the semiconductor substrate 100 on a side of the fifth sidewall layer 182 away from the first word line 180; the second bit line 191 is located in the semiconductor substrate 100 on a side of the sixth sidewall layer 183 away from the second word line 181.

Based on the memory as described above, the manufacturing method of the memory is described below. Please refer to Figures 3 to 15. Figure 3 is a schematic flow chart of the manufacturing method of the memory provided by an embodiment of the present invention; Figures 4 to 15 are schematic flow charts formed in the manufacturing method of the memory provided by an embodiment of the present invention. The manufacturing method of the memory provided by this embodiment is described in detail below in conjunction with the accompanying drawings.

As shown in FIG. 3 , the present invention further provides a method for manufacturing the memory, comprising:

Step S1: providing a semiconductor substrate;

Step S2: forming a first floating gate structure, a second floating gate structure and an erase gate on the semiconductor substrate, wherein the erase gate is located between the first floating gate structure and the second floating gate structure;

Step S3: forming a first oxide layer and a second oxide layer on the semiconductor substrate, wherein the first oxide layer is located on a side of the first floating gate structure away from the erase gate, and the second oxide layer is located on a side of the second floating gate structure away from the erase gate;

Step S4: forming a first word line and a second word line, wherein the first word line is located at one side of the first floating gate structure and covers the first oxide layer, the first word line is located at one side of the first floating gate structure and covers the first oxide layer, and the second word line is located at one side of the second floating gate structure and covers the second oxide layer.

First, step S1 is performed, as shown in Fig. 4, to provide a semiconductor substrate 100, which can be single crystal, polycrystalline or amorphous silicon or silicon germanium, or silicon on insulator SOI. In this embodiment, the semiconductor substrate 100 is a silicon substrate.

Next, step S2 is performed, as shown in FIGS. 4 to 12 , to form a first floating gate structure 110 , a second floating gate structure 120 and an erase gate 150 on the semiconductor substrate 100 , wherein the erase gate 150 is located between the first floating gate structure 110 and the second floating gate structure 120 .

Specifically, in step S2, the method for forming the first floating gate structure 110, the second floating gate structure 120 and the erase gate 150 includes: first, executing step S21, as shown in Figure 4, forming a floating gate structure layer 101 on the semiconductor substrate 100; specifically, the floating gate structure layer 101 includes a floating gate oxide layer 102 and a floating gate layer 103 stacked in sequence, and the floating gate oxide layer 102 covers the semiconductor substrate 100.

Next, step S22 is performed, as shown in FIG4 and FIG5, a dielectric layer 104 is formed on the floating gate structure layer 101; the dielectric layer 104 has a first opening 105 that penetrates in the thickness direction, and the first opening 105 exposes a portion of the floating gate structure layer 101; further, a specific method for forming the dielectric layer 104 includes forming the dielectric layer 104 on the floating gate structure layer 101, and then forming the first opening 105 in the dielectric layer 104 by dry etching. The dielectric layer 104 can be a silicon nitride layer, which has a masking function.

Next, step S23 is performed, as shown in Figure 6, to form a first side wall layer 113 and a second side wall layer 114, wherein the first side wall layer 113 and the second side wall layer 114 are both located above the exposed floating gate structure layer 101 and respectively cover the two side walls of the first opening 105; the material of the first side wall layer 113 and the second side wall layer 114 can be silicon oxide, which can be formed by a deposition method.

Next, step S24 is performed. As shown in FIG7 , the first spacer layer 113 and the second spacer layer 114 are used as masks to etch the exposed floating gate structure layer 101 to form a second opening 106 exposing the semiconductor substrate 100. Specifically, the second opening 106 penetrates the floating gate structure layer 101 in the thickness direction and is connected to the first opening 105, and the second opening 106 exposes the semiconductor substrate 100 between the first floating gate structure 110 and the second floating gate structure 120. More specifically, the second opening 106 divides and separates the floating gate structure layer 101 into a first part and a second part, and the first part and the second part of the floating gate structure layer 101 are respectively located on both sides of the second opening 106.

Next, step S25 is performed, as shown in FIG8 , in which an ion implantation process is performed on the exposed semiconductor substrate 100 to form a source line 130 in the semiconductor substrate 100. Specifically, the source line 130 extends from the surface of the semiconductor substrate 100 into the semiconductor substrate 100, and the source line 130 is located in the semiconductor substrate 100 between the first floating gate structure 110 and the second floating gate structure 120. The source line 130 is disposed in the semiconductor substrate 100, which can increase the coupling area between the source line 130 and the first floating gate structure 110 and the second floating gate structure 120, thereby increasing the coupling coefficient of the source line 130 to the first floating gate structure 110 and the second floating gate structure 120.

Next, step S26 is performed, as shown in Figure 9, to form a tunneling oxide layer 140, which covers the source line 130 and extends in the height direction to cover the side walls of the second opening 106 and the first opening 105, that is, the tunneling oxide layer 140 covers the side walls and bottom walls of the first opening 105 and the second opening 106, and the tunneling oxide layer 140 has an isolation function in subsequent processes.

Next, step S27 is performed: forming the erase gate 150, the erase gate 150 covers the tunnel oxide layer 140 and fills the second opening 106 and the first opening 105; specifically, the erase gate 150 is located above the source line 130 (or located above the tunnel oxide layer at the bottom wall of the second opening 106) and fills the second opening 106 and the first opening 105, that is, the erase gate 150 is aligned with the source line 130. When the memory is subsequently erased, an erase voltage can be applied to the erase gate 150, and a zero voltage can be applied to the first word line 180 and the second word line 181, so that electrons can flow from the first floating gate structure 110 to the erase gate 150 or from the second floating gate structure 120 to the erase gate 150, thereby reducing the electric field strength of the first oxide layer 170 and the second oxide layer 171, thereby improving the durability of the memory.

Next, step S28 is performed, as shown in FIG10 , to remove the dielectric layer 104 to expose a portion of the floating gate structure layer 101, that is, to expose a portion of the floating gate structure layer 101 covered by the floating gate structure layer 101. The portion of the floating gate structure layer 101 may be removed by a dry etching process.

Next, step S29 is performed: as shown in FIG. 11 , the exposed floating gate structure layer 101 is etched to form a first floating gate structure 110 and a second floating gate structure 120. Specifically, the first floating gate structure 110 includes a first floating gate oxide layer 111 and a first floating gate layer 112 stacked in sequence, and the second floating gate structure 120 includes a second floating gate oxide layer 121 and a second floating gate layer 122 stacked in sequence. More specifically, the first portion of the floating gate oxide layer 102 constitutes the first floating gate oxide layer 111, the second portion of the floating gate oxide layer 102 constitutes the second gate oxide layer 121, the first portion of the floating gate layer 103 constitutes the first floating gate layer 112, and the second portion of the floating gate layer 103 constitutes the second floating gate layer 122. The first portion and the second portion of the floating gate oxide layer 102 are respectively located on both sides of the erase gate 150, and the first portion and the second portion of the floating gate layer 103 are respectively located on both sides of the erase gate 150.

After etching the exposed floating gate structure layer 101 , the first floating gate structure 110 exposes a first portion of the semiconductor substrate 100 on a side away from the erase gate 150 , and the second floating gate structure 120 exposes a second portion of the semiconductor substrate 100 on a side away from the erase gate 150 .

Next, as shown in Figure 12, a third spacer layer 160 is formed, and the third spacer layer 160 covers the first floating gate structure 110 and a side wall of the first spacer layer 113 away from the erase gate 150; specifically, the third spacer layer 160 can be, for example, a silicon oxide layer, and the third spacer layer 160 can isolate the first word line 180 from the first floating gate structure 110.

Next, a fourth spacer 161 is formed. The fourth spacer 161 covers the second floating gate structure 120 and a side wall of the second spacer 114 away from the erase gate 150 .

Next, step S3 is performed, as shown in FIG14, a first oxide layer 170 and a second oxide layer 171 are formed on the semiconductor substrate 100, the first oxide layer 170 is located on a side of the first floating gate structure 110 away from the erase gate 150, and the second oxide layer 171 is located on a side of the second floating gate structure 120 away from the erase gate 150; specifically, the first oxide layer 170 is located on the exposed first portion of the semiconductor substrate 100, and the second oxide layer 171 is located on the exposed second portion of the semiconductor substrate 100. The first oxide layer 170 and the second oxide layer 171 may be formed by thermal oxidation.

Next, step S4 is performed to form a first word line 180 and a second word line 181, wherein the first word line 180 is located at one side of the first floating gate structure 110 and covers the first oxide layer 170, and the second word line 181 is located at one side of the second floating gate structure 120 and covers the second oxide layer 171. That is, the first oxide layer 170 is located between the first word line 180 and the semiconductor substrate 100, which can isolate the first word line 180 from the semiconductor substrate 100, and the second oxide layer 171 is located between the second word line 181 and the semiconductor substrate 100, which can isolate the second word line 181 from the semiconductor substrate 100.

Specifically, as shown in FIG13, the method for forming the first oxide layer 170, the second oxide layer 171, the first word line 180, and the second word line 181 includes forming an oxide material layer 162 on the exposed semiconductor substrate 100 (or the exposed first and second parts of the semiconductor substrate 100), and then forming a word line material layer 172 on the global surface of the semiconductor substrate 100. Then, as shown in FIG14, etching the word line material layer 172 and the oxide material layer 162, and stopping at the surface of the semiconductor substrate 100 to form the first oxide layer 170, the second oxide layer 172, the first word line 180, and the second word line 181. The word line material layer 172 may be made of polysilicon.

After forming the first word line 180 and the second word line 181, the memory manufacturing method further includes: executing step S5, as shown in FIG15, forming a fifth spacer 182, the fifth spacer 182 covering a side wall of the first word line 180 away from the first floating gate structure 110. Specifically, the material of the fifth spacer 182 can be a silicon oxide layer, which can be formed by a deposition method, and the fifth spacer 182 can isolate the first word line 180 from an external process layer, and protect the second word line 181 in a subsequent ion implantation process.

Next, execute step S6, and continue to refer to Figure 15 to form a sixth side wall layer 183, and the sixth side wall layer 183 covers the side wall of the second word line 181 away from the second floating gate structure 120; specifically, the material of the sixth side wall layer 183 can be silicon oxide, which can be formed by a deposition method. The sixth side wall layer 183 can isolate the second word line 181 from the external process layer, and protect the second word line 181 in the subsequent ion implantation process.

In addition, the sixth spacer layer 183 and the fifth spacer layer 182 can be formed in the same process step to save process time.

Next, step S7 is performed, as shown in FIG. 16 , to form a first bit line 190 , wherein the first bit line 190 is located in the semiconductor substrate 100 on a side of the five sidewall spacers 182 away from the first word line 180 .

Then, step S8 is performed, and as shown in FIG. 16 , a second bit line 191 is formed. The second bit line 191 is located in the semiconductor substrate 100 on a side of the sixth spacer 183 away from the second word line 181 .

Next, referring to FIG. 2 , a first bit line contact structure 192 is formed, the first bit line contact structure 192 is formed on the first bit line 190, that is, the first bit line contact structure 192 is aligned with the first bit line 190 and is electrically connected to the first bit line 190; and a second bit line contact structure 193 is formed, the second bit line contact structure 193 is formed on the second bit line 191, that is, the second bit line contact structure 193 is aligned with the second bit line 191 and is electrically connected to the second bit line 191. The first bit line contact structure 192 is used to electrically connect the first bit line 190 to the peripheral circuit, and the second bit line contact structure 193 is used to electrically connect the second bit line 191 to the peripheral circuit.

Specifically, the method for forming the first bit line 190 and the second bit line 191 includes performing ion implantation on the semiconductor substrate 100 to form the first bit line 190 in the semiconductor substrate 100 on a side of the fifth spacer 182 away from the first word line 180, and forming the second bit line 191 in the semiconductor substrate 100 on a side of the sixth spacer 183 away from the second word line 181. More specifically, the first bit line 190 and the second bit line 191 can be formed in the same process step to save process time. Further, the first floating gate structure 110, the first spacer layer 113, the third spacer layer 160, the fifth spacer layer 182, the first word line 180, the first bit line 190 and the first bit line contact structure 192 constitute a first storage unit of the memory, the second floating gate structure 120, the second spacer layer 114, the fourth spacer layer 161, the sixth spacer layer 183, the second word line 181, the second bit line 191 and the second bit line contact structure 193 constitute a second storage unit of the memory, the first storage unit, the second storage unit, the source line 130 and the erase gate 150 constitute two storage bits of the memory (a memory usually includes multiple storage bits).

Based on the same inventive concept, the present invention also provides a memory operating method, which includes the memory provided by the present invention, and further includes performing an erase operation, a program operation and a read operation on the memory provided by the present invention.

Specifically, the method for erasing the memory includes: applying an erase voltage to the erase gate 150, applying a zero voltage to the first word line 180, the second word line 181, the first bit line 190, the second bit line 191 and the source line 130, and performing an erase operation on the first floating gate structure 110 and the second floating gate structure 120. Electrons can flow from the first floating gate structure 110 to the erase gate 150 or from the second floating gate structure 120 to the erase gate 150, thereby applying a zero voltage to the first word line 180 and the second word line 181, and compared with the prior art, the electric field strength of the first oxide layer 170 and the second oxide layer 171 can be reduced, thereby improving the durability of the memory.

The memory programming operation method includes: applying a first voltage to the first word line 180, applying a second voltage to the first bit line 190, applying a third voltage to the second bit line 191, applying a fourth voltage to the source line 130 and the erase gate 150, and applying a zero voltage to the second word line 181. The value of the first voltage is less than the value of the third voltage. For example, when programming the first floating gate structure 110, the first voltage applied to the source line 130 and the erase gate 150 can be coupled to the first floating gate layer 112, thereby generating a voltage on the first floating gate structure 110. After the first bit line 190 applies a voltage, a lateral electric field is generated between the source line 130 and the first bit line 190, and the electric field can accelerate electrons under the first word line 180, thereby generating hot carriers, and the hot carriers can tunnel to the first floating gate structure 110 (specifically, the first floating gate layer 112) after colliding with the electrons, thereby completing the programming of the first floating gate structure 110. However, since zero voltage is applied to the second word line, that is, the second word line 181 is grounded and the second bit line 191 is applied with a fourth voltage, the channel at the bottom of the second word line 181 is closed (or cannot be turned on), so that no carriers pass between the source line 130 and the second bit line 191, and the second floating gate structure 120 (specifically, the second floating gate layer 122) cannot be programmed.

The memory read operation method includes: applying a fifth voltage to the first word line 180, applying a zero voltage to the second word line 181, applying a sixth voltage to the first bit line 190, and applying a zero voltage to the second bit line 191, the source line 130, and the erase gate 150, so as to perform a read operation on the first floating gate structure 110. Since the fifth voltage is applied to the first word line 180 and the sixth voltage is applied to the first bit line 190, the first bit line 190 and the source line 130 can be connected, thereby completing the reading of the first floating gate structure 110. Furthermore, since the second word line 181 applies a zero voltage, the channel at the bottom of the second word line 181 is closed (or cannot be turned on), so that the second floating gate structure 120 cannot be read. Furthermore, since a zero voltage is applied to the second bit line 191 and a sixth voltage is applied to the first bit line 190, the second bit line 191 can separate the signal of the first bit line 190 from the signals of the bit lines in other storage bits in the memory (for example, the bit line in another storage bit adjacent to the storage bit where the first bit line is located in a memory), that is, when performing a read operation, the second bit line 191 can shield the bit line signals except the first bit line 190 signal, thereby avoiding signal interference and completing the read operation on the first floating gate structure 110.

Among them, the erase voltage is 10V~14V, for example, it can be 12V, the first voltage is 1~2V, for example, it can be 1V, the second voltage is 0.1~0.8V, for example, it can be 0.3V, the third voltage is 1V~3V, for example, it can be 1.5V, the fourth voltage is 5V~9V, for example, it can be 6V, the fifth voltage can be 1V-3V, and the sixth voltage can be 0.5V~2V.

In summary, in the memory, the manufacturing method of the memory, and the operating method provided by the present invention, the memory includes a first floating gate structure, a second floating gate structure, and an erase gate formed on the semiconductor substrate, and the erase gate is located between the first floating gate structure and the second floating gate structure; by forming the erase gate between the first floating gate structure and the second floating gate structure, when the memory is erased, an erase voltage can be applied to the erase gate, and a zero voltage can be applied to the first word line and the second word line, that is, the erase gate erasing method can be used to erase the first floating gate structure and the second floating gate structure, thereby, when the memory is erased, electrons can flow from the first floating gate structure to the erase gate or from the second floating gate structure to the erase gate, thereby reducing the electric field strength of the first oxide layer and the second oxide layer, thereby improving the durability of the memory.

The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims (9)

1. A memory, the memory comprising:

A semiconductor substrate;

A first floating gate structure, a second floating gate structure, and an erase gate formed on the semiconductor substrate, the erase gate being located between the first floating gate structure and the second floating gate structure, the erase gate being for applying an erase voltage at the time of an erase operation;

The first oxide layer is positioned on one side of the first floating gate structure away from the erasing gate, and the second oxide layer is positioned on one side of the second floating gate structure away from the erasing gate;

A first word line formed on a side of the first floating gate structure away from the erase gate and covering the first oxide layer, and a second word line formed on a side of the second floating gate structure and covering the second oxide layer;

a source line in the semiconductor substrate aligned to the erase gate;

A tunneling oxide layer covering the source line, the first floating gate structure and a sidewall of the second floating gate structure, which is close to the erase gate;

a fifth side wall layer covering one side wall of the first word line far away from the first floating gate structure;

A sixth side wall layer covering a side wall of the second word line far away from the second floating gate structure;

The first bit line is positioned in the semiconductor substrate at one side of the five side wall layers far away from the first word line;

The second bit line is positioned in the semiconductor substrate at one side of the sixth side wall layer far away from the second word line;

Applying an erase voltage on the erase gate and applying zero voltages on the first word line, the second word line, the first bit line, the second bit line, and the source line when performing an erase operation on the memory;

Applying a first voltage on the first word line, a second voltage on the first bit line, a third voltage on the second bit line, a fourth voltage on the source line and the erase gate, and a zero voltage on the second word line when programming the memory, wherein no carriers pass between the source line and the second bit line during a programming operation;

When the memory is read, a fifth voltage is applied to the first word line and the second word line, a sixth voltage is applied to the first bit line, and zero voltage is applied to the second bit line, the source line and the erase gate, so that the first floating gate structure is read, wherein the second bit line shields bit line signals except the first bit line signal during the read operation.

2. The memory of claim 1, wherein the memory further comprises:

The first side wall layer is positioned on the first floating gate structure, and the tunneling oxide layer also extends to cover the first side wall layer;

the second side wall layer is positioned on the second floating gate structure, and the tunneling oxide layer also extends to cover the second side wall layer;

The third side wall layer covers the first floating gate structure and a side wall of the first side wall layer, which is far away from the erasing gate;

And the fourth side wall layer covers the second floating gate structure and one side wall of the second side wall layer, which is far away from the erasing gate.

3. The memory of claim 1, wherein the first floating gate structure comprises a first floating gate oxide layer and a first floating gate layer stacked in sequence, and the second floating gate structure comprises a first floating gate oxide layer and a second floating gate layer stacked in sequence.

4. The memory of claim 1 wherein the erase voltage is 10V to 14V; the first voltage is 1V-2V, the second voltage is 0.1V-0.8V, the third voltage is 1V-3V, the fourth voltage is 5V-9V, the fifth voltage is 1V-3V, and the sixth voltage is 0.5V-2V.

5. A method of manufacturing a memory device according to any one of claims 1 to 4, characterized in that the method of manufacturing a memory device comprises:

providing a semiconductor substrate;

forming a first floating gate structure, a second floating gate structure and an erase gate on the semiconductor substrate, wherein the erase gate is positioned between the first floating gate structure and the second floating gate structure, and the erase gate is used for applying an erase voltage during an erase operation;

Forming a first oxide layer and a second oxide layer on the semiconductor substrate, wherein the first oxide layer is positioned on one side of the first floating gate structure far away from the erasing gate, and the second oxide layer is positioned on one side of the second floating gate structure far away from the erasing gate;

Forming a first word line and a second word line, wherein the first word line is positioned on one side of the first floating gate structure far away from the erasing gate and covers the first oxidation layer, and the second word line is positioned on one side of the second floating gate structure far away from the erasing gate and covers the second oxidation layer;

forming a fifth side wall layer, wherein the fifth side wall layer covers one side wall, far away from the first floating gate structure, of the first word line;

forming a sixth side wall layer, wherein the sixth side wall layer covers a side wall, far away from the second floating gate structure, of the second word line;

Forming a first bit line, wherein the first bit line is positioned in the semiconductor substrate at one side of the five side wall layers far away from the first word line;

And forming a second bit line, wherein the second bit line is positioned in the semiconductor substrate at one side of the sixth side wall layer far away from the second word line.

6. The method of manufacturing a memory of claim 5, wherein the forming of the first floating gate structure, the second floating gate structure, and the erase gate comprises:

forming a floating gate structure layer on the semiconductor substrate;

Forming a dielectric layer on the floating gate structure layer, wherein the dielectric layer is provided with a first opening penetrating in the thickness direction, and part of the floating gate structure layer is exposed out of the first opening;

forming a first side wall layer and a second side wall layer, wherein the first side wall layer and the second side wall layer are both positioned above the exposed floating gate structure layer and respectively cover two side walls of the first opening;

etching the exposed floating gate structure layer by taking the first side wall layer and the second side wall layer as masks to form a second opening exposing the semiconductor substrate;

performing an ion implantation process on the exposed semiconductor substrate to form a source line;

forming a tunneling oxide layer, wherein the tunneling oxide layer covers the source line and extends to cover the side walls of the second opening and the first opening;

Forming the erasing gate, wherein the erasing gate covers the tunneling oxide layer and fills the second opening and the first opening;

removing the dielectric layer to expose part of the floating gate structure layer;

Etching the exposed floating gate structure layer to form a first floating gate structure and a second floating gate structure;

After etching the exposed floating gate structure layer, one side of the first floating gate structure, which is far away from the erasing gate, exposes a first part of the semiconductor substrate, and one side of the second floating gate structure, which is far away from the erasing gate, exposes a second part of the semiconductor substrate; the first oxide layer is located on the exposed first portion of the semiconductor substrate and the second oxide layer is located on the exposed second portion of the semiconductor substrate.

7. The method of manufacturing a memory according to claim 6, wherein before forming the first oxide layer and the second oxide layer, the method of manufacturing a memory further comprises:

forming a third side wall layer, wherein the third side wall layer covers the first floating gate structure and a side wall, close to the first word line, of the first side wall layer;

And forming a fourth side wall layer, wherein the fourth side wall layer covers the second floating gate structure and a side wall, close to the second word line, of the second side wall layer.

8. The method of manufacturing a memory according to claim 7, wherein after forming the first bit line and the second bit line, the method of manufacturing a memory further comprises:

And

Forming a first bit line contact structure, the first bit line contact structure being formed on the first bit line;

a second bit line contact structure is formed on the second bit line.

9. The method for manufacturing a memory according to claim 8, wherein the first floating gate structure includes a first floating gate oxide layer and a first floating gate layer stacked in this order, and the second floating gate structure includes a second floating gate oxide layer and a second floating gate layer stacked in this order.