CN112185316A

CN112185316A - GOA circuit and display panel

Info

Publication number: CN112185316A
Application number: CN202011146151.XA
Authority: CN
Inventors: 李亚锋; 杨博
Original assignee: Wuhan China Star Optoelectronics Technology Co Ltd
Current assignee: Wuhan China Star Optoelectronics Technology Co Ltd
Priority date: 2020-10-23
Filing date: 2020-10-23
Publication date: 2021-01-05

Abstract

The application discloses GOA circuit and display panel. A third global control signal adjustable by increasing voltage; when the power is off, the forward scanning direct current control signal, the reverse scanning direct current control signal, the third global control signal and all clock signals are controlled to provide high-level signals, each level of GOA units are controlled to output high-level grid driving signals, images on a display screen can be rapidly cleared, and afterimages of displayed pictures before the images appear are avoided.

Description

GOA circuit and display panel

Technical Field

The application relates to the technical field of display, in particular to a GOA circuit and a display panel.

Background

A Thin film transistor liquid crystal display (TFT-LCD) has become the mainstream display in the market, and the basic principle of the TFT-LCD is that liquid crystal in the display is driven by voltage to deflect, so that the propagation direction of light is changed to make the display different colors. The Gate Driver On Array (GOA) technology of the Array substrate integrates a Gate driving circuit On the Array substrate of a liquid crystal display panel by using the existing thin film transistor liquid crystal display Array (Array) process, and realizes the driving mode of scanning the Gate lines (Gate) line by line.

In the GOA circuit, when Abnormal Power Off (APO for short) occurs, the liquid crystal display panel may have image sticking phenomenon due to the residual level in the pixel capacitor. And the problems of high system power consumption in a low power wake-up (LPWG) mode and heavy load striation exist. In the prior art, an effective mechanism for preventing the occurrence of the ghost phenomenon and improving the problems of high power consumption and heavy-load horizontal stripes of the LPWG is lacked.

Disclosure of Invention

The embodiment of the application provides a GOA circuit and a display panel, can control each grade of GOA unit to output a high-level grid driving signal when the power is off, rapidly clear away the image on a display screen, and avoid the ghost of the displayed picture before appearing.

The embodiment of the application provides a GOA circuit, which comprises a plurality of cascaded GOA units; the nth grade GOA unit includes: a forward and reverse scanning control module, for outputting a first node control signal at a first node and a second node control signal at a second node according to the forward scanning DC control signal or the reverse scanning DC control signal; an output module, coupled to the first node and receiving an nth-level clock signal, for outputting an nth-level gate driving signal according to the first node control signal and the nth-level clock signal during a forward scan or a reverse scan of the GOA circuit; a pull-down maintaining module, coupled to the first node, the second node and an output terminal of the output module, for maintaining a low level of the first node control signal and the nth stage gate driving signal and a high level of the second node control signal; the forward and reverse scanning control module is further used for responding to a third global control signal when the power is off so as to generate a first power-off control signal; the output module is further used for outputting a high-level nth-level gate driving signal according to the first power-off control signal and a high-level nth-level clock signal.

An embodiment of the present application further provides a display panel, including: an array substrate, array substrate includes the GOA circuit of this application.

The application has the advantages that: when the outage, this application GOA circuit can control each grade GOA unit output high level's grid drive signal to clear away the image on the display screen rapidly, the ghost of the display screen before avoiding appearing is favorable to user's visual experience. When the power is off, the GOA circuit can pull down the level of the second node, and can solve the problem of high power consumption when low power consumption is awakened. According to the method and the device, the thin film transistor is additionally arranged on the paths of the forward scanning direct current control signal/the reverse scanning direct current control signal of the forward and reverse scanning control module and the first node respectively, so that the paths of the forward scanning direct current control signal and the reverse scanning direct current control signal which leak electricity to the first node can be controlled, and the problem of heavy-load cross striations is solved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

FIG. 1 is a circuit diagram of an embodiment of a GOA circuit;

FIG. 2 is a block diagram of a GOA circuit according to the present application;

FIG. 3 is a circuit diagram of an embodiment of a GOA circuit of the present application;

FIG. 4 is a timing diagram of forward scan driving of the GOA circuit shown in FIG. 3;

FIG. 5 is a timing diagram of a reverse scan driving of the GOA circuit shown in FIG. 3;

FIG. 6 is a timing diagram of signals of the GOA circuit shown in FIG. 3 during power-down;

fig. 7 is a schematic diagram of a display panel structure according to the present application.

Detailed Description

Reference will now be made in detail to embodiments of the present application, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar components or components having the same or similar functions throughout. The terms "first," "second," "third," and the like in the description and in the claims of the present application, and in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the objects so described are interchangeable under appropriate circumstances. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise. Furthermore, the terms "comprising" and "having," as well as any variations thereof, are intended to cover a non-exclusive inclusion. The directional phrases referred to in this application, for example: up, down, left, right, front, rear, inner, outer, lateral, etc., are simply directions with reference to the drawings.

In the description of the present application, it is to be understood that the terms "connected" and "connected" are to be interpreted broadly unless explicitly defined or limited otherwise. For example, the components may be electrically connected or in communication with each other, directly or indirectly through intervening media, or may be in communication within or interacting with each other. It will be understood that when an element is referred to as being "coupled" to another element, there are intervening elements present. The specific meaning of the above terms in the present application can be understood by those of ordinary skill in the art as appropriate.

The application provides a novel GOA circuit, wherein a third global control signal with adjustable voltage is added to a forward and reverse scanning control module; when the power is off, the output module of each GOA unit is controlled to output a high-level gate driving signal by controlling the forward scanning direct current control signal, the reverse scanning direct current control signal, the third global control signal and all clock signals to provide a high-level signal, so that the image on a display screen can be rapidly cleared, the ghost of a displayed picture before the occurrence is avoided, and the visual experience of a user is facilitated. This application maintains the module at the pull-down and increases the fourth global control signal of voltage adjustable, when the outage, provides low level signal through further controlling fourth global control signal, draws down the second node level, can solve the low-power consumption and awaken up the time consumption problem on the high side. According to the method and the device, the thin film transistor is respectively added on the paths of the forward scanning direct current control signal/the reverse scanning direct current control signal of the forward and reverse scanning control module and the first node, the paths of the forward scanning direct current control signal and the reverse scanning direct current control signal which leak electricity to the first node can be controlled, and therefore the problem of heavy-load cross striations is solved.

Referring to fig. 1, a circuit diagram of an embodiment of a GOA circuit is shown. In the GOA circuit, there are typically 2 key nodes: point Q, point P. The main function of the Q point is to maintain a higher level during the pixel charging phase, so that the level of the output nth gate driving signal Gn can be controlled to be high/low according to the high/low level corresponding to the nth clock signal CKn; the main role of the P-point is to maintain a high level in a Pixel Holding (Pixel Holding) phase, thereby ensuring that the Q-point and the nth stage gate driving signal Gn output a low level.

In the GOA circuit, when an abnormal power failure (APO) occurs, if the forward scan dc control signal U2D and the reverse scan dc control signal D2U are both low, the OVL Timing (Timing) cannot guarantee that all clock signals CK are constant low level VGL, so the clock signals CK have high or low; this causes a charge residue at the P-point, which turns on the transistor NT10, and further pulls the nth gate driving signal Gn low, thereby causing image sticking.

Referring to fig. 2, a block diagram of a GOA circuit of the present application is shown. The GOA circuit comprises a plurality of cascaded GOA units. As shown in fig. 2, the nth level GOA unit includes: a forward/reverse scanning control module 21, an output module 22 and a pull-down maintaining module 23.

The forward/reverse scan control module 21 is configured to output a first node control signal at a first node Q and a second node control signal at a second node P according to the forward scan dc control signal U2D or the reverse scan dc control signal D2U. The output module 22 is coupled to the first node Q and receives an nth-stage clock signal CKn, and is configured to output an nth-stage gate driving signal Gn according to the first node control signal and the nth-stage clock signal CKn during a forward scan or a reverse scan of the GOA circuit. The pull-down maintaining module 23 is coupled to the first node Q, the second node P and the output terminal of the output module 22, and is configured to maintain the low level of the first node control signal and the nth gate driving signal Gn and maintain the high level of the second node control signal. The forward and reverse scanning control module 21 is further configured to respond to a third global control signal Gas3 when the power is off, so as to generate a first power-off control signal; the output module 22 is further configured to output an nth level gate driving signal Gn according to the first power-off control signal and the nth level clock signal CKn. The nth level gate driving signal Gn with high level can turn on the pixel driving switch controlled by the corresponding gate line, thereby rapidly clearing the image on the display screen and avoiding the afterimage of the previous display picture.

Specifically, during the forward scan of the GOA circuit, the forward/reverse scan control module 21 responds to the forward scan dc control signal U2D, the nth-m gate driving signal G (n-m) (n and m are natural numbers, and n > m), and the third global control signal Gas3, pre-charges the first node Q to pull up the level of the first node Q, and then pull down the level of the second node P, so as to output a high-level first node control signal at the first node Q and output a low-level second node control signal at the second node P; the output module 22 transmits the nth stage clock signal CKn with high/low level in response to the first node control signal with high level. And then pulls down the level of the first node Q in response to the n + m-th stage gate driving signal G (n + m). The first node Q and the second node P are basically in a mutual-holding process, the level of the first node Q is high, and the level of the second node P is basically low; the level of the first node Q is low and the level of the second node P is substantially high.

Specifically, during the reverse scan of the GOA circuit, the forward/reverse scan control module 21 responds to the reverse scan dc control signal D2U, the nth + mth gate driving signal G (n + m), and the third global control signal Gas3, pre-charges the first node Q, pulls up the level of the first node Q, and then pulls down the level of the second node P, so as to output a high-level first node control signal at the first node Q, and output a low-level second node control signal at the second node P; the output module 22 transmits the nth stage clock signal CKn with high/low level in response to the first node control signal with high level. And then pulls down the level of the first node Q in response to the nth-m stage gate driving signal G (n-m).

When the power is turned off, the forward scan dc control signal U2D, the reverse scan dc control signal D2U, the third global control signal Gas3 and the nth stage clock signal CKn all provide high level signals to control the output module 22 to output the nth stage gate driving signal Gn. Further, all the clock signals CK provide high level signals to control the output module 22 of each level of the GOA unit to output high level gate driving signals, so that the image on the display screen can be rapidly cleared, and the afterimage of the previous display picture can be avoided.

In a further embodiment, the GOA unit level 1, the GOA unit level 2, … …, and the GOA unit level m receive the initial signal STV; the original signal STV is also received by the 1 st, 2 nd, … … th, and m th last GOA units. The initial signal STV is a high level signal.

In a further embodiment, the pull-down maintaining module 23 may be further configured to generate a second power-down control signal in response to the fourth global control signal Gas4 when the power is turned off, so as to stop outputting low-level signals to the first node Q and the output terminal of the output module 22, thereby solving the problem of high power consumption when the low-power wake-up is performed. Specifically, during the forward/reverse scan of the GOA circuit, after the level of the first node Q is pulled down and the first node control signal outputs a low level, the pull-down maintaining module 23 charges the second node P to pull up the level of the second node P in response to the nth-m stage clock signal CK (n-m)/nth + m stage clock signal CK (n + m) and the fourth global control signal Gas4, and then outputs a low level signal to the first node Q and the output terminal of the output module 22, so as to maintain the low levels of the first node control signal and the nth stage gate driving signal Gn. At power-off, all clock signals CK provide high level signals, and the fourth global control signal Gas4 provides low level signals to pull down the level of the second node P, thereby stopping outputting low level signals to the first node Q and the output terminal of the output module 22 of each GOA unit.

In a further embodiment, the forward/reverse scan control module 21 may be further configured to control a path of the forward scan dc control signal U2D and the reverse scan dc control signal D2U leaking to the first node Q, so as to improve the heavy duty horizontal stripe problem. Specifically, during the forward scanning of the GOA circuit, the forward/reverse scanning control module 21 is further responsive to the nth-m stage clock signal CK (n-m) to pass the forward scanning dc control signal U2D on; during the reverse scan of the GOA circuit, the forward/reverse scan control module 21 is further responsive to the (n + m) th stage clock signal CK (n + m) to pass the reverse scan dc control signal D2U.

In this embodiment, the nth level GOA unit further includes: a first global control module 24 and a second global control module 25.

The first global control module 24 is coupled to the output terminal of the output module 22, and is configured to output a high signal to the output terminal of the output module 22 in response to a first global control signal Gas 1. The second global control module 25 is coupled to the output terminal of the output module 22, and is configured to output a low signal to the output terminal of the output module 22 in response to a second global control signal Gas 2. When the first global control signal Gas1 provides a high level signal, each stage of the GOA unit of the GOA circuit outputs a high level signal, and enters an All Gate line All-On (All Gate On) stage. When the second global control signal Gas2 provides a high level signal, each stage of the GOA unit of the GOA circuit outputs a low level signal, and enters an All Gate Off (All Gate Off) stage.

This application is when the outage, all provides high level signal through control forward scanning direct current control signal, reverse scanning direct current control signal, third global control signal and all clock signals, and the image on the display screen can be clear away rapidly to the nth level gate drive signal Gn of control output module output high level, shows the ghost of picture before avoiding appearing, is favorable to user's visual experience. When the power is off, the fourth global control signal is further controlled to provide a low level signal, the level of the second node is pulled down, and the problem that the power consumption is higher when the low power consumption is awakened can be solved. According to the method and the device, the thin film transistor is respectively added on the paths of the forward scanning direct current control signal/the reverse scanning direct current control signal of the forward and reverse scanning control module and the first node, the paths of the forward scanning direct current control signal and the reverse scanning direct current control signal which leak electricity to the first node can be controlled, and therefore the problem of heavy-load cross striations is solved. According to the method and the device, the gate line full-on or gate line full-off function is further achieved through the first global control module and the second global control module.

Referring to fig. 2, fig. 3, and fig. 4-fig. 6 together, wherein fig. 3 is a circuit diagram of an embodiment of the GOA circuit of the present application, fig. 4 is a forward scan driving timing diagram of the GOA circuit shown in fig. 3, fig. 5 is a reverse scan driving timing diagram of the GOA circuit shown in fig. 3, and fig. 6 is a timing variation diagram of signals of the GOA circuit shown in fig. 3 when the power is off. In this example the value of m is 2. It should be noted that the value of m in the present embodiment is merely exemplary and is not to be construed as limiting the present application.

As shown in fig. 3, the forward/reverse scanning control module 21 includes: a first thin film transistor NT1, a second thin film transistor NT2, a sixth thin film transistor NT6, a seventh thin film transistor NT7, and a first capacitor C1. The first thin film transistor NT1 has a first terminal receiving the forward scan dc control signal U2D, a control terminal receiving the (n-2) th gate driving signal G (n-2) (n >2), and a second terminal connected to the first sub-node Qa. The second thin film transistor NT2 has a first terminal receiving the reverse scan dc control signal D2U, a control terminal receiving the (n +2) th stage gate driving signal G (n +2), and a second terminal connected to the first sub-node Qa. The sixth thin film transistor NT6 has a first terminal receiving a constant voltage low level VGL, a control terminal connected to the first sub-node Qa, and a second terminal connected to the second node P. A first terminal of the seventh thin film transistor NT7 is connected to the first sub-node Qa, a control terminal thereof receives the third global control signal Gas3, and a second terminal thereof is connected to the first node Q. One end of the first capacitor C1 is connected to the first node Q, and the other end receives the constant voltage low level VGL.

The output module 22 includes: the ninth thin film transistor NT 9. The ninth thin film transistor NT9 has a first terminal receiving the nth stage clock signal CKn, a control terminal connected to the first node Q, and a second terminal serving as an output terminal of the output module 22 for outputting the nth stage gate driving signal Gn.

The pull-down maintaining module 23 includes: a third thin film transistor NT3, a fourth thin film transistor NT4, a fifth thin film transistor NT5, a tenth thin film transistor NT10, and a second capacitor C2. The third thin film transistor NT3 has a first terminal receiving the n-2 th stage clock signal CK (n-2), a control terminal receiving the forward scan dc control signal U2D, and a second terminal coupled to the second node P. The fourth thin film transistor NT4 has a first terminal receiving the (n +2) th stage clock signal CK (n +2), a control terminal receiving the reverse scan dc control signal D2U, and a second terminal coupled to the second node P. The fifth thin film transistor NT5 has a first terminal receiving a constant voltage low level VGL, a control terminal connected to the second node P, and a second terminal connected to the first sub-node Qa. A first terminal of the tenth thin film transistor NT10 receives a constant voltage low level VGL, a control terminal thereof is connected to the second node P, and a second terminal thereof is connected to the output terminal of the output module 22; one end of the second capacitor C2 is connected to the second node P, and the other end receives a constant voltage low level VGL.

In this embodiment, the forward/reverse scanning control module 21 further includes: a fourteenth thin film transistor NT14 and a fifteenth thin film transistor NT 15. The fourteenth thin film transistor NT14 has a first terminal receiving the forward scan dc control signal U2D, a control terminal receiving the n-2 th stage clock signal CK (n-2), and a second terminal connected to the first terminal of the first thin film transistor NT 1. The fifteenth thin film transistor NT15 has a first terminal receiving the reverse scan dc control signal D2U, a control terminal receiving the (n +2) th stage clock signal CK (n +2), and a second terminal connected to the first terminal of the second thin film transistor NT 2.

In this embodiment, the pull-down maintaining module 23 further includes: the eighth thin film transistor NT 8. The first terminal of the eighth thin film transistor NT8 receives a fourth global control signal Gas4, and the control terminals thereof are simultaneously connected to the second terminal of the third thin film transistor NT3 and the second terminal of the fourth thin film transistor NT4, and the second terminal thereof is connected to the second node P.

In this embodiment, the first global control module 24 includes: an eleventh thin film transistor NT11 and a twelfth thin film transistor NT 12. The first terminal and the control terminal of the eleventh thin film transistor NT11 are shorted for receiving the first global control signal Gas1, and the second terminal is connected to the output terminal of the output module 22. The twelfth thin film transistor NT12 has a first terminal receiving a constant voltage low VGL, a control terminal receiving the first global control signal Gas1, and a second terminal connected to the second node P.

In this embodiment, the second global control module 25 includes: the thirteenth thin film transistor NT 13. The thirteenth thin film transistor NT13 has a first terminal receiving the constant voltage low VGL, a control terminal receiving the second global control signal Gas2, and a second terminal connected to the output terminal of the output module 22.

The working principle of forward scanning of the GOA circuit of the present application is further explained with reference to fig. 3 and 4. In fig. 4, U2D is a high-level forward direction scanning dc control signal, D2U is a low-level reverse direction scanning dc control signal, Gas3 and Gas4 are high-level global control signals, Gas1 and Gas2 are low-level global control signals, CK (n-2), CKn and CK (n +2) are corresponding clock signals (alternating current), G (n-2), Gn and G (n +2) are waveforms of corresponding gate driving signals, and Q, P indicates waveforms of corresponding nodes.

The specific working principle of the forward scanning of the nth-level GOA unit is as follows:

a pre-charging stage: CK (n-2), G (n-2) and U2D are all at high level, transistors NT14, NT1 and NT7 are turned on, the Qa point outputs high level, and the Q point is precharged. When the Q point is high level, the transistor NT9 is in a conducting state; transistor NT6 is also in the on state and point P is pulled low.

Gn output high level stage: CKn is ramped to high level, and since the Q point is precharged and the capacitor C1 has a certain holding effect on the charges, the transistor NT9 is still in a conducting state, and Gn outputs a high level corresponding to CKn.

Gn output low level stage: CKn is ramped to a low level, and since the capacitor C1 has a holding effect on the high level at the Q point, the transistor NT9 is still in a conducting state, and Gn outputs a low level corresponding to CKn.

Q point level pull-down stage: when CK (n +2) and G (n +2) jump high, the transistors NT15 and NT2 are turned on because D2U is low, the Qa point level is pulled low, and the Q point level is also pulled low, so that the transistor NT9 is turned off.

Q point low level and Gn output low level maintaining stage: when CK (n-2) jumps high again, the transistors NT3, NT8 are turned on, and the P point is charged, so that the transistors NT5 and NT10 are both in a conductive state; meanwhile, the capacitor C2 has a certain holding effect on the high level of the point P, so that the low level of the point Q and the low level of the Gn output can be ensured to be stable.

And other stages: a gate line full-open stage: the GAS1 is high, and each stage of the GOA unit of the GOA circuit outputs a high level gate driving signal. A gate line full-off stage: the GAS2 is high, and each stage of the GOA unit of the GOA circuit outputs a low level gate driving signal.

The working principle of reverse scan of the GOA circuit of the present application is further explained with reference to fig. 3 and 5. In fig. 5, U2D is a low-level forward direction scanning dc control signal, D2U is a high-level reverse direction scanning dc control signal, Gas3 and Gas4 are high-level global control signals, Gas1 and Gas2 are low-level global control signals, CK (n-2), CKn and CK (n +2) are corresponding clock signals (alternating current), G (n-2), Gn and G (n +2) are waveforms of corresponding gate driving signals, and Q, P indicates waveforms of corresponding nodes.

The specific working principle of the reverse scanning of the nth-level GOA unit is as follows:

a pre-charging stage: CK (n +2), G (n +2), and D2U are simultaneously at high level, transistors NT15, NT2, and NT7 are turned on, a high level is output at the Qa point, and the Q point is precharged. When the Q point is high level, the transistor NT9 is in a conducting state; transistor NT6 is also in the on state and point P is pulled low.

Q point level pull-down stage: when CK (n-2) and G (n-2) are transited to high, U2D is at low level, transistors NT14 and NT1 are in on state, Qa point level is pulled low, and Q point level is also pulled low, so that transistor NT9 is in off state.

Q point low level and Gn output low level maintaining stage: when CK (n +2) jumps high again, the transistors NT4, NT8 are turned on, and the P point is charged, so that the transistors NT5 and NT10 are both in a conductive state; meanwhile, the capacitor C2 has a certain holding effect on the high level of the point P, so that the low level of the point Q and the low level of the Gn output can be ensured to be stable.

And other stages: a gate line full-open stage: GAS1 is high, and each stage of the GOA unit of the GOA circuit outputs a high signal. A gate line full-off stage: GAS2 is high and each stage of the GOA unit of the GOA circuit outputs a low signal.

The working principle of the GOA circuit after power-off will be further explained with reference to fig. 3 and 6. In fig. 6, the first timing is the input signal level of the GOA circuit at a certain time when the display panel normally operates, and the second timing is the input signal level of the GOA circuit when the display panel is powered off.

As can be seen from fig. 6, at power-off, the forward scan dc control signal U2D, the reverse scan dc control signal D2U, the third global control signal Gas3, and all the clock signals CK provide high level signals (the initial signal STV also provides a high level signal); thereby, the transistor NT9 of each stage of the GOA circuit can be controlled to output the gate driving signal G of high level. The fourth global control signal Gas4 provides a low level signal, so that the P-point level can be pulled down to stop outputting low level signals to the Q-point and the output end of each level of GOA unit, and the problem of high power consumption when low power consumption is awakened is solved.

Based on the same inventive concept, the application also provides a display panel.

Referring to fig. 7, a schematic diagram of a panel structure is shown in the present application. The display panel 70 includes an array substrate 71, and the array substrate 71 includes a GOA circuit 711. The GOA circuit 711 adopts the GOA circuit described in fig. 2 or fig. 3 of the present application. The connection manner and operation principle of the circuit elements of the GOA circuit 711 have been described in detail before, and are not described herein again.

The display panel 70 may be a liquid crystal display panel, an OLED display panel, or an AMOLED display panel.

Adopt this application GOA circuit's display panel, can be when the outage, control each grade GOA unit output high level's of GOA circuit grid drive signal to can solve the low-power consumption and awaken the time consumption problem on the high side, can also improve the heavy load horizontal stripe problem.

The above description of the embodiments is only for assisting understanding of the technical solutions and the core ideas thereof; those of ordinary skill in the art will understand that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications or substitutions do not depart from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A GOA circuit comprises a plurality of cascaded GOA units; wherein, nth grade GOA unit includes:

a forward and reverse scanning control module, for outputting a first node control signal at a first node and a second node control signal at a second node according to the forward scanning DC control signal or the reverse scanning DC control signal;

an output module, coupled to the first node and receiving an nth-level clock signal, for outputting an nth-level gate driving signal according to the first node control signal and the nth-level clock signal during a forward scan or a reverse scan of the GOA circuit;

a pull-down maintaining module, coupled to the first node, the second node and an output terminal of the output module, for maintaining a low level of the first node control signal and the nth stage gate driving signal and a high level of the second node control signal;

the forward and reverse scanning control module is further used for responding to a third global control signal when the power is off so as to generate a first power-off control signal; the output module is further used for outputting a high-level nth-level gate driving signal according to the first power-off control signal and a high-level nth-level clock signal.

2. The GOA circuit of claim 1, wherein the pull-down maintaining module is further configured to generate a second power-down control signal in response to a fourth global control signal to stop outputting low signals to the first node and the output terminal of the output module when the power is down.

3. The GOA circuit of claim 1, wherein the forward scan control module and the reverse scan control module are further configured to control a path of the forward scan DC control signal and the reverse scan DC control signal to leak to the first node.

4. The GOA circuit of claim 1, wherein the forward-reverse scan control module comprises: the first thin film transistor, the second thin film transistor, the sixth thin film transistor, the seventh thin film transistor and the first capacitor; the output module includes: a ninth thin film transistor;

a first end of the first thin film transistor receives the forward scanning direct current control signal, a control end of the first thin film transistor receives an nth-m level grid driving signal, and a second end of the first thin film transistor is connected to a first sub-node, wherein n and m are natural numbers, and n is larger than m;

the first end of the second thin film transistor receives the reverse scanning direct current control signal, the control end of the second thin film transistor receives an n + m-th-level gate driving signal, and the second end of the second thin film transistor is connected to the first sub-node;

a first end of the sixth thin film transistor receives a constant voltage low level, a control end of the sixth thin film transistor is connected to the first sub-node, and a second end of the sixth thin film transistor is connected to the second node;

a first end of the seventh thin film transistor is connected to the first sub-node, a control end of the seventh thin film transistor receives the third global control signal, and a second end of the seventh thin film transistor is connected to the first node;

one end of the first capacitor is connected to the first node, and the other end of the first capacitor receives the constant voltage low level;

a first end of the ninth thin film transistor receives the nth-stage clock signal, a control end of the ninth thin film transistor is connected to the first node, and a second end of the ninth thin film transistor is used as an output end of the output module;

when the power is off, the forward scanning direct current control signal, the reverse scanning direct current control signal, the third global control signal and the nth-level clock signal all provide high-level signals so as to control the ninth thin film transistor to output a high-level nth-level gate driving signal.

5. The GOA circuit of claim 4, wherein the forward/reverse scan control module further comprises: a fourteenth thin film transistor and a fifteenth thin film transistor;

a first end of the fourteenth thin film transistor receives the forward scanning direct current control signal, a control end of the fourteenth thin film transistor receives an n-m level clock signal, and a second end of the fourteenth thin film transistor is connected to the first end of the first thin film transistor;

the first end of the fifteenth thin film transistor receives the reverse scanning direct current control signal, the control end of the fifteenth thin film transistor receives the n + m-th-level clock signal, and the second end of the fifteenth thin film transistor is connected to the first end of the second thin film transistor.

6. The GOA circuit of claim 1, wherein the pull-down maintenance module comprises: a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a tenth thin film transistor, and a second capacitor;

a first end of the third thin film transistor receives an n-m level clock signal, a control end of the third thin film transistor receives the forward scanning direct current control signal, and a second end of the third thin film transistor is coupled to the second node, wherein n and m are natural numbers, and n is greater than m;

a first end of the fourth thin film transistor receives the (n + m) th-level clock signal, a control end of the fourth thin film transistor receives the inverse scan direct current control signal, and a second end of the fourth thin film transistor is coupled to the second node;

a first end of the fifth thin film transistor is connected to the first sub-node, a control end of the fifth thin film transistor is connected to the second node, and a second end of the fifth thin film transistor receives a constant voltage low level;

a first end of the tenth thin film transistor is connected to an output end of the output module, a control end of the tenth thin film transistor is connected to the second node, and a second end of the tenth thin film transistor receives a constant voltage low level;

one end of the second capacitor is connected to the second node, and the other end of the second capacitor receives a constant voltage low level.

7. The GOA circuit of claim 6, wherein the pull-down maintenance module further comprises: an eighth thin film transistor; a first end of the eighth thin film transistor receives a fourth global control signal, a control end of the eighth thin film transistor is connected to a second end of the third thin film transistor and a second end of the fourth thin film transistor at the same time, and a second end of the eighth thin film transistor is connected to the second node;

when the power is off, all the clock signals provide high level signals, and the fourth global control signal provides low level signals to stop outputting low level signals to the first node and the output end of the output module.

8. The GOA circuit of claim 1, wherein the nth stage GOA unit further comprises:

a first global control module, coupled to the output end of the output module, for responding to a first global control signal and outputting a high level signal to the output end of the output module;

and the second global control module is coupled to the output end of the output module and used for responding to a second global control signal and outputting a low level signal to the output end of the output module.

9. The GOA circuit of claim 8, wherein the first global control module comprises: an eleventh thin film transistor and a twelfth thin film transistor; the second global control module comprises: a thirteenth thin film transistor;

the first end and the control end of the eleventh thin film transistor are short-circuited and used for receiving the first global control signal, and the second end of the eleventh thin film transistor is connected to the output end of the output module;

a first end of the twelfth thin film transistor receives a constant voltage low level, a control end of the twelfth thin film transistor receives the first global control signal, and a second end of the twelfth thin film transistor is connected to the second node;

a first end of the thirteenth thin film transistor receives the constant voltage low level, a control end of the thirteenth thin film transistor receives the second global control signal, and a second end of the thirteenth thin film transistor is connected to an output end of the output module;

the first global control signal provides a high-level signal in the all-gate-line full-open stage; the second global control signal provides a high level signal during all gate line fully-off phase.

10. A display panel, comprising:

an array substrate comprising the GOA circuit of any one of claims 1-9.