Loop quick response circuit suitable for high-voltage BUCK and implementation method
Technical Field
The invention relates to the technical field of circuits, in particular to a loop quick response circuit.
Background
With rapid development of technology, electronic products are continuously updated, and requirements on input voltage of a power supply, stability and quality of a chip are higher and higher. The BUCK chip is used as one of the power supply chips, and has the characteristics of high conversion efficiency, low cost and good dynamic performance, and becomes an indispensable chip in the power supply module. However, with the increase of input voltage and the increase of application range of load, the BUCK chip cannot be adjusted in time to generate unstable or voltage and current overshoot phenomenon when the load changes, so that the chip or the output end is burnt out. It is desirable to design a BUCK chip that can respond quickly and has a good recovery function, and can cope well with the effect of a quick stabilizing circuit when a load changes under high-voltage input conditions.
Disclosure of Invention
In order to overcome the defects of the prior art, the invention provides a loop quick response circuit suitable for high-voltage BUCK, which is used in the field of related protection circuits, and the circuit automatically adjusts the parameters of a main loop of the circuit by detecting the output voltage of VOUT and adjusting the loop, so that the circuit achieves the effects of detection, feedback and adjustment in a short time. Therefore, the method suitable for loop quick response of the high-voltage BUCK can effectively solve the technical problems in the related field.
The technical scheme adopted for solving the technical problems is as follows:
A loop quick response circuit suitable for high-voltage BUCK comprises an N-channel enhancement type MOS tube NM0_NM1, an inductor L, resistors R0-R2, a capacitor C0, a low-voltage driving circuit module, a high-voltage driving circuit module, a charge pump module, a PWM regulating circuit module, an EA module, an A/D converter module, a VIN input port, a VREF input port and a VOUT output port.
The source electrode of the N-channel enhancement MOS tube NM0 is connected with the VIN input port, the grid electrode of the N-channel enhancement MOS tube NM0 is connected with the output port of the high-voltage driving circuit module, and the drain electrode of the N-channel enhancement MOS tube NM1 is connected with one end of a resistor R2 and one end of an inductor L; the source electrode of the N-channel enhancement MOS tube NM1 is grounded, the grid electrode is connected with the output port of the low-voltage driving circuit module, and the drain electrode is connected with the drain electrode of the N-channel enhancement MOS tube NM0, one end of the resistor R2 and one end of the inductor L; the other end of the inductor L is connected with one end of the resistor R0 and the VOUT output port; the other end of the resistor R0 is connected with one end of the resistor R1 and the 3 input port of the EA module; the other end of the resistor R is grounded; the other end of the resistor R2 is connected with an upper polar plate of the capacitor C0 and an input port of the A/D converter module; the lower polar plate of the capacitor C0 is grounded; the output end of the A/D converter module is connected with the 2 input port of the EA module; the input port of the EA module 1 is connected with the VREF input port, and the output port is connected with the input end of the PWM regulating circuit module; the input port of the PWM regulating circuit module is connected with the output port of the EA module, the output 1 port is connected with the input end of the high-voltage driving circuit module 1, and the output 2 port is connected with the input port of the low-voltage driving circuit module; the input port of the low-voltage driving circuit module is connected with the 2 output port of the PWM regulating circuit, and the output port is connected with the grid electrode of the N-channel enhancement type MOS tube NM 1; the input end of the high-voltage driving circuit module 1 is connected with the 1 output port of the PWM regulating circuit, the 2 input port is connected with the output port of the charge pump module, and the output port is connected with the grid electrode of the N-channel enhancement type MOS tube NM 0; the input end of the charge pump is connected with the VIN input port and the drain electrode of the N channel enhancement MOS tube NM0, and the output end of the charge pump is connected with the input end of the high-voltage driving circuit module 2.
The implementation method of the loop quick response circuit suitable for the high-voltage BUCK comprises the following steps:
When the response circuit works, the charge pump module provides a driving voltage for the grid electrode of the N-channel enhancement type MOS tube NM0 through the high-voltage driving circuit by using the voltage pump at the VIN input end which is higher than the VIN voltage. The circuit compares the feedback voltage of the voltage dividing resistor R0 and the intermediate node VFB of R1 connected with the output end of the VOUT with the VREF reference voltage through the EA module, then transmits the result to the PWM regulating circuit module for PWM waveform adjustment, and then controls the grid electrodes of the P-channel enhancement type MOS tube PM0 and the N-channel enhancement type MOS tube NM0 of the upper power tube and the lower power tube through the driving circuit module, so that SW switch waveforms are generated at the drain electrode of the P-channel enhancement type MOS tube PM0, and a main loop is formed by the circuit. The SW waveform is filtered and then transmitted to the A/D converter module by adding a filter formed by a resistor R2 and a capacitor C0 at the SW end, when the system is disturbed to enable the output voltage to drop, the A/D converter converts the SW waveform analog signal into a corresponding digital signal, the digital signal enters the EA module, a corresponding control circuit for controlling the bandwidth to be increased is started, the duty ratio of the circuit is increased in this way, and the output voltage is also rapidly increased to offset the disturbance. The same applies when the output voltage is disturbed to rise.
The invention has the beneficial effects that:
1. The whole circuit is simple in design, completely suitable for a high-voltage CMOS process, simpler and faster in loop detection SW waveform, and capable of well transmitting the stable condition of output to a main loop of the circuit for rapid adjustment.
2. The number of bits output by the A/D converter can be increased according to actual demands, so that the adjustment of the gain of the EA module can be stepped, and the gain which needs to be increased can be selected in real time according to actual output waveforms.
Drawings
FIG. 1 is a schematic diagram of a method for loop fast response for high voltage BUCK according to the present invention.
Detailed Description
The invention will be further described with reference to the drawings and examples.
A loop fast response circuit suitable for high voltage BUCK, as shown in fig. 1: the MOS transistor mainly comprises an N-channel enhancement type MOS transistor NM0_NM1, an inductor L, resistors R0-R2, a capacitor C0, a low-voltage driving circuit module, a high-voltage driving circuit module, a charge pump module, a PWM regulating circuit module, an EA module, an A/D converter module, a VIN input port, a VREF input port and a VOUT output port.
The source electrode of the N-channel enhancement MOS tube NM0 is connected with the VIN input port, the grid electrode is connected with the output port of the high-voltage driving circuit module, the drain electrode is connected with the drain electrode of the N-channel enhancement MOS tube NM1, one end of a resistor R2 and one end of an inductor L; the source electrode of the N-channel enhancement MOS tube NM1 is grounded, the grid electrode is connected with the output port of the low-voltage driving circuit module, the drain electrode is connected with the drain electrode of the N-channel enhancement MOS tube NM0 and one end of the resistor R2, and one end of the inductor L; one end of the inductor L is connected with one end of the N-channel enhancement type MOS tube NM0, one end of the N-channel enhancement type MOS tube NM1 and one end of the resistor R2, and the other end of the inductor L is connected with one end of the resistor R0 and the output port of VOUT; one end of the resistor R0 is connected with the other end of the inductor L and the output port of the VOUT, and the other end of the resistor R1 is connected with one end of the resistor R1 and the 3 input port of the EA module; one end of the resistor R1 is connected with the other end of the resistor R0 and the 3 input port of the EA module, and the other end of the resistor R1 is grounded; one end of the resistor R2 is connected with one end of the N-channel enhancement type MOS tube NM0, one end of the N-channel enhancement type MOS tube NM1 and one end of the inductor L, and the other end of the resistor R2 is connected with an upper polar plate of the capacitor C0 and an input port of the A/D converter module; the upper polar plate of the capacitor C0 is connected with the other end of the resistor R2 and the input port of the A/D converter module, and the lower polar plate is grounded; the input port of the A/D converter module is connected with the other end of the resistor R2 and the upper polar plate of the capacitor C0, and the output end of the A/D converter module is connected with the 2 input port of the EA module; the input port of the EA module 1 is connected with the VREF input port, the input port of the EA module 2 is connected with the output port of the A/D converter, the input port of the EA module 3 is connected with the other end of the resistor R0 and one end of the resistor R1, and the output port of the EA module is connected with the input end of the PWM regulating circuit module; the input port of the PWM regulating circuit module is connected with the output port of the EA module, the output 1 port is connected with the input end of the high-voltage driving circuit module 1, and the output 2 port is connected with the input port of the low-voltage driving circuit module; the input port of the low-voltage driving circuit module is connected with the 2 output port of the PWM regulating circuit, and the output port is connected with the grid electrode of the N-channel enhancement type MOS tube NM 1; the input end of the high-voltage driving circuit module 1 is connected with the 1 output port of the PWM regulating circuit, the 2 input port is connected with the output port of the charge pump module, and the output port is connected with the grid electrode of the N-channel enhancement type MOS tube NM 0; the input end of the charge pump is connected with the VIN input port and the drain electrode of the N channel enhancement MOS tube NM0, and the output end of the charge pump is connected with the input end of the high-voltage driving circuit module 2.
With reference to fig. 1, the implementation method of the loop fast response circuit suitable for the high-voltage BUCK is as follows: when the circuit works, the charge pump module provides a driving voltage for the grid electrode of the N-channel enhancement type MOS tube NM0 through the high-voltage driving circuit by using the voltage pump at the VIN input end which is higher than the VIN voltage. The circuit compares the feedback voltage of the voltage dividing resistor R0 and the intermediate node VFB of R1 connected with the output end of the VOUT with the VREF reference voltage through the EA module, then transmits the result to the PWM regulating circuit module for PWM waveform adjustment, and then controls the grid electrodes of the P-channel enhancement type MOS tube PM0 and the N-channel enhancement type MOS tube NM0 of the upper power tube and the lower power tube through the driving circuit module, so that SW switch waveforms are generated at the drain electrode of the P-channel enhancement type MOS tube PM0, and a main loop is formed by the circuit. According to the invention, a filter formed by a resistor R2 and a capacitor C0 is added at the SW end, the SW waveform is filtered and then is transmitted to the A/D converter module, when the system is disturbed to enable the output voltage to drop, the A/D converter converts the SW waveform analog signal into a corresponding digital signal, the digital signal enters the EA module, a corresponding control circuit for controlling the bandwidth to be increased is started, the circuit increases the duty ratio in such a way, the output voltage can be rapidly increased to offset the disturbance, and the output voltage is disturbed to rise similarly.
In summary, the invention provides a loop quick response circuit suitable for high-voltage BUCK and an implementation method thereof, which can effectively regulate a circuit loop. Compared with the previous BUCK loop regulation method, the whole circuit is simple in design and has a quick response speed, the added SW detection circuit does not occupy excessive area, the internal power consumption of the circuit is small, and quick circuit stability regulation can be realized.