CN112164683A - Bare chip packaging structure with metal layer on back surface - Google Patents
Bare chip packaging structure with metal layer on back surface Download PDFInfo
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- CN112164683A CN112164683A CN202010856422.4A CN202010856422A CN112164683A CN 112164683 A CN112164683 A CN 112164683A CN 202010856422 A CN202010856422 A CN 202010856422A CN 112164683 A CN112164683 A CN 112164683A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49568—Lead-frames or other flat leads specifically adapted to facilitate heat dissipation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
- H01L23/3736—Metallic materials
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
- H10D64/251—Source or drain electrodes for field-effect devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
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- Condensed Matter Physics & Semiconductors (AREA)
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- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
本发明公开一种背面设有金属层的裸芯封装结构，属于半导体的技术领域，该背面设有金属层的裸芯封装结构包括基板，基板一侧表面形成有导电层；晶片本体，晶片本体相对的两侧表面分别形成连接面以及散热面，晶片本体的连接面朝向基板并固定于导电层表面；连接面上具有至少两个电极，电极均与导电层电连接；散热面上形成有金属导热层。使晶片本体的封装过程相比传统封装方式能够节省多个制程，从而提高晶片产能；提高晶片本体的散热性能，更有利于晶片领域的发展；可避免胶材自身所存在的厚度导致产品在高温高湿条件下产生短路等问题，提高产品可靠性。
The invention discloses a bare core package structure with a metal layer on the back, belonging to the technical field of semiconductors. The bare core package structure with a metal layer on the back comprises a substrate, a conductive layer is formed on one side surface of the substrate; a chip body, a chip body The opposite side surfaces respectively form a connection surface and a heat dissipation surface, the connection surface of the wafer body faces the substrate and is fixed on the surface of the conductive layer; the connection surface has at least two electrodes, and the electrodes are electrically connected to the conductive layer; the heat dissipation surface is formed with metal Thermal layer. Compared with the traditional packaging method, the packaging process of the chip body can save multiple processes, thereby increasing the chip production capacity; improving the heat dissipation performance of the chip body is more conducive to the development of the chip field; it can avoid the thickness of the adhesive material itself causing the product to be exposed to high temperatures. Problems such as short circuits occur under high humidity conditions, improving product reliability.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a bare chip packaging structure with a metal layer on the back surface.
Background
The semiconductor is a material with the conductivity between a conductor and a non-conductor, and the semiconductor element belongs to a solid element according to the characteristics of the semiconductor material, and the volume of the semiconductor element can be reduced to a small size, so that the power consumption is low, the integration level is high, and the semiconductor element is widely applied to the technical field of electronics.
The semiconductor packaging refers to a process of processing a wafer passing a test according to a product model and a functional requirement to obtain an independent chip. The packaging process comprises the following steps: the wafer from the previous process of the wafer is cut into small chips through a scribing process, then the cut chips are pasted on the corresponding small islands of the substrate frame through glue, and then the bonding pads of the chips are connected to the corresponding pins of the substrate through superfine metal wires or conductive resin to form a required circuit; and then packaging and protecting the independent wafer by using a plastic shell, carrying out a series of operations after plastic packaging, carrying out finished product testing after packaging, generally carrying out the processes of inspection, testing, packaging and the like, and finally warehousing and shipping.
Among them, heat dissipation performance becomes one of the important indexes of semiconductor devices, and maintaining the operational reliability of semiconductor devices in a high temperature working environment is a very important issue, but the conventional semiconductor packaging method has a poor heat dissipation effect due to the lead frame limited by the chip structure, and especially has a large influence on a high-power chip, and the chip is heated rapidly during operation, so that the chip is easily damaged, and the development of the chip is hindered.
Disclosure of Invention
The embodiment of the invention aims to: the utility model provides a bare chip packaging structure with metal layer on the back, through set up the electrode concentrate on the same face of wafer body to set up the metal heat-conducting layer on the another side of wafer body, saved a plurality of processes and improved its radiating effect, thereby solve the above-mentioned problem that exists among the prior art.
In order to achieve the purpose, the invention adopts the following technical scheme:
a bare chip packaging structure with a metal layer on the back comprises a substrate, wherein a conductive layer is formed on the surface of one side of the substrate; the wafer body, the surface of both sides opposite to the said wafer body forms connecting surface and radiating surface separately, the said connecting surface of the said wafer body faces the said base plate and is fixed to the surface of the said conductive layer; the connecting surface is provided with at least two electrodes which are electrically connected with the conducting layer; and a metal heat conduction layer is formed on the heat dissipation surface.
Furthermore, the number of the electrodes is three, and the three electrodes are respectively a source electrode, a grid electrode and a drain electrode.
Further, the substrate further comprises a heat dissipation layer for forming a main body structure of the substrate and dissipating heat; the insulating layer is arranged on the surface of the heat dissipation layer; the conducting layer is arranged on the surface of one side, far away from the heat dissipation layer, of the insulating layer; the conducting layer is partitioned to form a plurality of mutually isolated connecting areas, and the connecting areas form connecting circuits and are respectively correspondingly connected with the corresponding electrodes.
Furthermore, a plurality of heat dissipation grooves are formed in the surface of one side, away from the heat dissipation surface, of the metal heat conduction layer.
Further, the extending directions of the plurality of heat dissipation grooves are parallel to each other.
Furthermore, the heat dissipation grooves are arranged at intervals, and the distance between any two adjacent heat dissipation grooves is equal.
Further, the metal heat conduction layer is one of copper, aluminum, silver and gold.
Further, the surface of one side, away from the radiating surface, of the metal heat conduction layer is covered with a graphene heat conduction layer.
Furthermore, a solder paste layer is printed on the area, corresponding to the electrode, of the connecting surface, and the solder paste layer is welded with the electrode protruding out of the connecting surface and electrically connected with the wafer body.
Furthermore, an insulating protective film covers the connecting surface, and the electrode penetrates out of the insulating protective film and is electrically connected with the conducting layer.
The invention has the beneficial effects that: the electrodes are uniformly arranged on the connecting surface of the wafer body, so that compared with the traditional packaging mode, the packaging process of the wafer body can save a plurality of processes, thereby improving the wafer productivity;
compared with the traditional mode that a lead frame is arranged on the wafer body or a heat dissipation layer is added between the lead frame and the wafer body, the heat dissipation effect is better, the overall thickness and size of the product can be thinner, and the development of the wafer field is facilitated;
furthermore, on the basis of the structure, the packaging structure is not required to be filled with the adhesive material, so that the problems that the product is short-circuited under the high-temperature and high-humidity condition due to the thickness of the adhesive material can be avoided, and the reliability of the product is improved.
Drawings
The invention is explained in more detail below with reference to the figures and examples.
Fig. 1 is a schematic cross-sectional view of a die package structure with a metal layer on a back surface thereof according to an embodiment of the invention;
fig. 2 is a schematic cross-sectional view of a die package structure with a metal layer on the back surface according to a second embodiment of the present invention;
fig. 3 is a schematic cross-sectional view of a die package structure with a metal layer on a back surface according to a third embodiment of the present invention.
In the figure: 10. a substrate; 11. a conductive layer; 12. an insulating layer; 13. a heat dissipation layer; 20. a wafer body; 21. a connecting surface; 22. a heat dissipating surface; 23. an electrode; 24. a metal heat conducting layer; 241. a heat dissipation groove; 25. a graphene heat conducting layer; 26. a solder paste layer; 27. and an insulating protective film.
Detailed Description
In order to make the technical problems solved, technical solutions adopted, and technical effects achieved by the present invention clearer, the technical solutions of the embodiments of the present invention are described in further detail below, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the description of the present invention, unless otherwise expressly specified or limited, the terms "connected," "connected," and "fixed" are to be construed broadly, e.g., as meaning permanently connected, removably connected, or integral to one another; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In the present invention, unless otherwise expressly stated or limited, "above" or "below" a first feature means that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact with each other via another feature therebetween. Also, the first feature being "on," "above" and "over" the second feature includes the first feature being directly on and obliquely above the second feature, or merely indicating that the first feature is at a higher level than the second feature. A first feature being "under," "below," and "beneath" a second feature includes the first feature being directly under and obliquely below the second feature, or simply meaning that the first feature is at a lesser elevation than the second feature.
The first embodiment is as follows:
as shown in fig. 1, in order to improve the productivity, heat dissipation performance and reliability of a semiconductor chip, the embodiment provides a die package structure with a metal layer on a back surface, the structure is used for matching with a chip to improve the stability and heat dissipation performance of the chip, the die package structure with the metal layer on the back surface includes a substrate 10 as a support main body of the structure, a conductive layer 11 is formed on a surface of one side of the substrate 10, and in an actual packaging process, the conductive layer 11 can be provided with corresponding pins, so that the chip connected with the conductive layer 11 of the substrate 10 can be connected with the outside.
A wafer body 20, wherein in order to facilitate a comprehensive understanding of the solution, two opposite side surfaces of the wafer body 20 respectively form a connection surface 21 for being fixed on the substrate 10 and a heat dissipation surface 22 for dissipating heat from the wafer body 20, and in a state where the wafer body 20 is fixed on the substrate 10, the connection surface 21 of the wafer body 20 faces the substrate 10 and is fixed on the surface of the conductive layer 11, and is connected with the conductive layer 11; it is specific, connect and have two at least electrodes 23 on the face 21, electrode 23 all is connected with conducting layer 11 electricity, unified setting of electrode 23 is on the face 21 is connected with one side of wafer body 20, can omit a plurality of processing procedure steps in the manufacturing of wafer body 20 and later stage packaging process, thereby improve the production of wafer body 20 and packaging process, the production efficiency, improve the productivity in this field greatly, it is simpler to have saved the structure that the processing procedure also can let wafer body 20 structure tradition both sides all have electrode 23, thereby wafer body 20's the production degree of difficulty has been reduced.
In order to realize the technical effect that this scheme will reach, be formed with metal heat-conducting layer 24 on the cooling surface 22, metal heat-conducting layer 24 sets up on the side that deviates from base plate 10, namely on the back of wafer body 20, can improve the heat dispersion of wafer body 20, compare and rely on bare core heat dissipation alone or like traditional packaging structure, set up the lead frame on the chip, and on the lead frame, or it is better to set up its radiating effect of mode of heat radiation structure between lead frame and chip, the heat that produces on the wafer body 20 can be transmitted to metal heat-conducting layer 24, and evenly transmit in the whole of metal heat-conducting layer 24, thereby carry out the heat transfer through metal heat-conducting layer 24 and external environment, reach the radiating effect.
In this embodiment, the metal heat conduction layer 24 is made of copper, aluminum, silver, or gold, and in this embodiment, the metal heat conduction layer 24 is made of copper, which has a lower cost and a higher comprehensive performance price than gold and silver, although the heat dissipation performance of copper is inferior to that of gold and silver, so that copper is used as the material of the metal heat conduction layer 24, and the copper metal heat conduction layer 24 can be formed by bonding or directly growing on the surface of the chip body 20.
The structure simplifies the packaging structure, can effectively reduce the total thickness of packaged products, reduces the size of the products, thins the products, can be more fully applied to more fields, and is more favorable for the development of the fields.
On the basis of the structure, the packaging structure is not required to be filled with the adhesive material, so that the problems that the product is short-circuited under the high-temperature and high-humidity condition due to the thickness of the adhesive material can be avoided, and the reliability of the product is improved.
In the preferred embodiment of the above configuration, the number of the electrodes 23 is three, and the three electrodes 23 are a source electrode, a gate electrode, and a drain electrode, respectively.
The substrate 10 further comprises a heat dissipation layer 13 for forming a body structure of the substrate 10 and dissipating heat; an insulating layer 12, wherein the insulating layer 12 is arranged on the surface of the heat dissipation layer 13; the conductive layer 11 is arranged on the surface of one side of the insulating layer 12 far away from the heat dissipation layer 13 and is isolated from the heat dissipation layer 13 by the insulating layer 12; the conductive layer 11 is partitioned to form a plurality of connection regions isolated from each other, and the connection regions form connection circuits and are respectively connected to the corresponding electrodes 23, thereby preventing short circuits between the connection circuits and the heat dissipation layer 13. The conductive layer 11 can be formed by sticking a metal foil on the insulating layer 12 and heating and curing, and is simple and convenient to manufacture and easy to operate.
The heat dissipation layer 13 is generally configured to be a plate-shaped structure, and can be made of metal to form a metal plate, such as an aluminum plate, an iron plate, and the like, so that the heat dissipation layer is relatively simple to manufacture, has good structural strength and heat dissipation performance, and can also have good anti-corrosion performance and light weight. The heat dissipation layer 13 may also be made of graphene, and compared with a metal plate, the plate-shaped structure made of graphene may be thinner, have higher strength, and have better heat dissipation performance.
The heat dissipation layer 13 can be isolated from other components by the insulating layer 12, and short-circuiting of other components is avoided. The insulating layer 12 may be a cured product of a curable resin composition containing a heat-resistant resin, a curing agent, and an inorganic filler, and has both heat dissipation performance and insulating performance. The heat-resistant resin may be an epoxy resin, a silicone resin, a phenol resin, an imide resin, or the like, and the inorganic filler may be an oxide ceramic such as alumina, silica, or magnesia, or a nitride ceramic such as aluminum nitride, silicon nitride, or boron nitride, a carbide ceramic, or the like. In the curable resin composition, a silane coupling agent, a titanate coupling agent, a stabilizer, a curing accelerator, and the like may be used as necessary.
Example two:
as shown in fig. 2, in the first embodiment, a plurality of heat dissipation grooves 241 are formed on a surface of the metal heat conduction layer 24 away from the heat dissipation surface 22, and the heat dissipation grooves 241 are formed to allow the surface of the metal heat conduction layer 24 to have a plurality of heat dissipation structures like heat dissipation fins, so as to increase a contact area of the metal heat conduction layer 24 contacting with the outside, and further increase the heat dissipation performance of the chip body 20.
The heat dissipation groove 241 can be formed by etching, photolithography and chemical etching, and compared with the method of directly processing on the metal heat conduction layer 24, the heat dissipation groove 241 formed by the above method has higher precision, higher controllability and reduced defective rate.
Further, the extension directions of the plurality of heat dissipation grooves 241 are parallel to each other, so that air flow channels in a uniform direction are formed among the plurality of heat dissipation grooves 241, and cold air can pass through the air flow channels to further improve the heat dissipation effect.
In order to ensure that the heat transfer on the metal heat conduction layer 24 is more uniform and the heat dissipation effect is better, the plurality of heat dissipation grooves 241 are arranged at intervals, and the distance between any two adjacent heat dissipation grooves 241 is equal.
Example three:
as shown in fig. 3, based on the first or second embodiment, the graphene heat conduction layer 25 covers the surface of the metal heat conduction layer 24 on the side away from the heat dissipation surface 22, the graphene has very high thermal conductivity and thermal radiation coefficient, and the thermal conductivity coefficient of the single-layer graphene can reach 5300W/mK, which is not only better than that of the carbon nanotube, but also much higher than that of silver, copper, gold, aluminum, etc. with the highest thermal conductivity coefficient in metal, so that the heat dissipation performance of the wafer body 20 can be further improved by using graphene as a heat conduction plastic or film for assisting heat dissipation on the surface of the metal heat conduction layer 24, and the graphene heat conduction layer 25 in this embodiment can cover the metal heat conduction layer 24 by coating.
As a further scheme of embodiments 1 to 3, a solder paste layer 26 is printed on a region corresponding to the electrode 23 on the connection surface 21, the electrode 23 protruding from the connection surface 21 is soldered on the solder paste layer 26, the electrode 23 is electrically connected to the wafer body 20, the connection surface 21 is covered with an insulating protective film 27, and the electrode 23 penetrates through the insulating protective film 27 and is electrically connected to the conductive layer 11.
The electrode 23 and the conductive layer 11 are directly connected through the protrusion, so that a lead frame and a metal wire are not required to be additionally arranged, the lead frame and the metal wire are not required to be packaged and fixed through materials such as epoxy resin, and the size of the package can be greatly reduced and the volume and the weight of the package can be reduced no matter the length, the width and the height of the package are greatly reduced by directly covering the connection surface 21 of the wafer body 20 with the insulating protection film 27.
In the description herein, it is to be understood that the terms "upper," "lower," "left," "right," and the like are used in an orientation or positional relationship merely for convenience in description and simplicity of operation, and do not indicate or imply that the referenced device or element must have a particular orientation, configuration, and operation in a particular orientation, and therefore should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used merely for descriptive purposes and are not intended to have any special meaning.
In the description herein, references to the description of "an embodiment," "an example" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example.
Furthermore, it should be understood that although the present description refers to embodiments, not every embodiment may contain only a single embodiment, and such description is for clarity only, and those skilled in the art should integrate the description, and the embodiments may be appropriately combined to form other embodiments as will be appreciated by those skilled in the art.
The technical principle of the present invention is described above in connection with specific embodiments. The description is made for the purpose of illustrating the principles of the invention and should not be construed in any way as limiting the scope of the invention. Based on the explanations herein, those skilled in the art will be able to conceive of other embodiments of the present invention without inventive effort, which would fall within the scope of the present invention.
Claims (10)
1. A kind of back is equipped with the bare chip encapsulated structure of the metal layer, characterized by that, comprising:
a substrate (10) having a conductive layer (11) formed on one surface of the substrate (10);
the chip comprises a chip body (20), wherein a connecting surface (21) and a heat dissipation surface (22) are respectively formed on two opposite side surfaces of the chip body (20), and the connecting surface (21) of the chip body (20) faces the substrate (10) and is fixed on the surface of the conductive layer (11);
the connecting surface (21) is provided with at least two electrodes (23), and the electrodes (23) are electrically connected with the conductive layer (11);
and a metal heat conduction layer (24) is formed on the heat dissipation surface (22).
2. The die package structure with metal layer on back side as claimed in claim 1, wherein the number of the electrodes (23) is three, and the three electrodes (23) are a source electrode, a gate electrode and a drain electrode respectively.
3. The die package structure with metal layer on back side as claimed in claim 1, wherein the substrate (10) further comprises a heat dissipation layer (13) for forming a main structure of the substrate (10) and dissipating heat; the insulating layer (12), the said insulating layer (12) is set up in the surface of the said heat-dissipating layer (13); the conducting layer (11) is arranged on the surface of one side, away from the heat dissipation layer (13), of the insulating layer (12); the conducting layer (11) is partitioned to form a plurality of mutually isolated connecting areas which form a connecting circuit and are respectively correspondingly connected with the corresponding electrodes (23).
4. The die package structure with the metal layer on the back side as claimed in claim 1, wherein a plurality of heat dissipation grooves are formed on a surface of the metal heat conduction layer (24) on a side away from the heat dissipation surface (22).
5. The die package structure with the metal layer on the back surface as claimed in claim 4, wherein the plurality of heat dissipation grooves extend in parallel to each other.
6. The die package structure with the metal layer on the back surface of the die package structure of claim 5, wherein a plurality of the heat dissipation grooves are arranged at intervals, and the intervals between any two adjacent heat dissipation grooves are equal.
7. The backside metal-clad die package structure of any one of claims 1-6, wherein the metal heat conducting layer (24) is one of copper, aluminum, silver, and gold.
8. The backside metal-clad die package structure according to any one of claims 1-6, wherein a surface of the metal heat conduction layer (24) away from the heat dissipation surface (22) is covered with a graphene heat conduction layer (25).
9. The die package structure with the metal layer on the back side as recited in claim 1, wherein a solder paste layer (26) is printed on a region of the connection surface (21) corresponding to the electrode (23), the electrode (23) protruding from the connection surface (21) is soldered on the solder paste layer (26), and the electrode (23) is electrically connected to the wafer body (20).
10. The die package structure with the metal layer on the back side as claimed in claim 9, wherein the connection surface (21) is covered with an insulating protection film (27), and the electrode (23) penetrates through the insulating protection film (27) and is electrically connected to the conductive layer (11).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN202010856422.4A CN112164683A (en) | 2020-08-24 | 2020-08-24 | Bare chip packaging structure with metal layer on back surface |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202010856422.4A CN112164683A (en) | 2020-08-24 | 2020-08-24 | Bare chip packaging structure with metal layer on back surface |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1758431A (en) * | 2004-05-21 | 2006-04-12 | 台湾积体电路制造股份有限公司 | Wafer-level package with integrated heat sink on crystal back and heat dissipation method for chip |
| CN1794445A (en) * | 2005-11-09 | 2006-06-28 | 江阴长电先进封装有限公司 | Micron scale chip size packaging radiation structure |
| CN101858586A (en) * | 2009-04-07 | 2010-10-13 | 璨圆光电股份有限公司 | The structure in which the light emitting diode circuit is integrated in the heat dissipation substrate |
| CN102201449A (en) * | 2011-05-27 | 2011-09-28 | 电子科技大学 | Low-heat-resistance packaging structure of power MOS (Metal Oxide Semiconductor) device |
| CN107203087A (en) * | 2017-06-21 | 2017-09-26 | 太仓派欧技术咨询服务有限公司 | A kind of projector thermal dispersant coatings system and its coating production |
-
2020
- 2020-08-24 CN CN202010856422.4A patent/CN112164683A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1758431A (en) * | 2004-05-21 | 2006-04-12 | 台湾积体电路制造股份有限公司 | Wafer-level package with integrated heat sink on crystal back and heat dissipation method for chip |
| CN1794445A (en) * | 2005-11-09 | 2006-06-28 | 江阴长电先进封装有限公司 | Micron scale chip size packaging radiation structure |
| CN101858586A (en) * | 2009-04-07 | 2010-10-13 | 璨圆光电股份有限公司 | The structure in which the light emitting diode circuit is integrated in the heat dissipation substrate |
| CN102201449A (en) * | 2011-05-27 | 2011-09-28 | 电子科技大学 | Low-heat-resistance packaging structure of power MOS (Metal Oxide Semiconductor) device |
| CN107203087A (en) * | 2017-06-21 | 2017-09-26 | 太仓派欧技术咨询服务有限公司 | A kind of projector thermal dispersant coatings system and its coating production |
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