CN112164678B - Semiconductor package and manufacturing method thereof - Google Patents

Abstract

The invention discloses a semiconductor package and a manufacturing method thereof. The manufacturing method of the semiconductor package comprises the following steps: providing a first substrate; providing a first wiring structure on the first substrate; the first wiring structure includes at least two first wiring layers; providing at least one second wiring structure; electrically connecting a plurality of the second wiring structures with a side of the first wiring structure facing away from the first substrate; each second wiring structure comprises at least two second wiring layers; providing at least one semiconductor element; each semiconductor element comprises a plurality of pins; and arranging one side of the semiconductor element, on which the pins are arranged, on one side of the second wiring structure, which is away from the first substrate. The embodiment of the invention can improve the utilization rate of the wafer and reduce the cost.

Description

A kind of semiconductor package and manufacturing method thereof

technical field

The invention relates to the field of display technology, in particular to a semiconductor package and a manufacturing method thereof.

Background technique

In semiconductor technology, semiconductor packaging technology has played an important role in the development of the semiconductor industry. With the development of technologies such as artificial intelligence, 5G technology and smart phones, the requirements for semiconductor packaging technology are also increasing. Semiconductor packaging needs to achieve smaller dimensions, lighter, thinner, more pins, and high reliability. and lower cost.

In the prior art, the wafer-level packaging technology is mostly used, and the wafer is used as the substrate for the chip packaging process, but the cost of the wafer-level packaging technology is relatively high, and the utilization rate of the wafer is low, which increases the cost.

Contents of the invention

The invention provides a semiconductor package and a manufacturing method thereof, which can improve the utilization rate of wafers and reduce costs.

In a first aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor package, including:

providing a first substrate;

A first wiring structure is arranged on the first substrate; the first wiring structure includes at least two first wiring layers, and a first insulating layer is arranged between two adjacent first wiring layers; An insulating layer includes a plurality of first through holes, and the first wiring layers of two adjacent layers are electrically connected through the first through holes;

providing at least one second wiring structure; each of the second wiring structures includes at least two second wiring layers; a second insulating layer is arranged between two adjacent second wiring layers of the same second wiring structure, The second insulating layer includes a plurality of second through holes, and the second wiring layers of two adjacent layers are electrically connected through the second through holes;

electrically connecting a plurality of the second wiring structures to a side of the first wiring structure away from the first substrate;

providing at least one semiconductor element; each semiconductor element comprising a plurality of pins;

A side of the semiconductor element provided with pins is disposed on a side of the second wiring structure away from the first substrate.

In a second aspect, an embodiment of the present invention provides a semiconductor package, which is formed by using any method for manufacturing a semiconductor package provided in the first aspect. The semiconductor package includes:

The first wiring structure; the first wiring structure includes at least two first wiring layers, and a first insulating layer is arranged between two adjacent first wiring layers; the first insulating layer includes a plurality of first a through hole, the first wiring layers of two adjacent layers are electrically connected through the first through hole;

At least one second wiring structure; each of the second wiring structures includes at least two second wiring layers, and a second insulating layer is arranged between two adjacent second wiring layers; the second insulating layer includes A plurality of second through holes, two adjacent layers of the second wiring layer are electrically connected through the second through holes; a plurality of the second wiring structures are located on one side of the first wiring structure; each of the The second wiring structures are all electrically connected to the first wiring structure;

At least one semiconductor element, each semiconductor element including a plurality of pins; the semiconductor element is located on a side of the second wiring structure away from the first wiring structure, and the semiconductor element is electrically connected to the first wiring structure.

In the technical solution provided by the embodiment of the present invention, at least one fabricated semiconductor element is arranged by arranging at least one fabricated second wiring structure on the side of the first wiring structure away from the first substrate, and electrically connecting with the first wiring structure. The semiconductor element is arranged on the side of the second wiring structure away from the first substrate, and is electrically connected to the first wiring structure through the second wiring structure. Since each second wiring structure is independent of each other, when designing the second wiring structure master, there is no need to consider the distance between adjacent second wiring structures, and it is only necessary to form a plurality of independent second wiring structures after cutting the second wiring structure master. After wiring the structures, the distance between adjacent second wiring structures can be adjusted. If a wafer-level process is used to form the second wiring structure, when designing the second wiring structure master, the spacing limitation between adjacent second wiring structures can be ignored, and the adjacent second wiring in the second wiring structure master can be set The pitch of the structure is small, thereby increasing the quantity of the second wiring structure in the master plate of the second wiring structure on a single wafer, thereby improving the utilization rate of the wafer and reducing the production cost.

Description of drawings

In order to illustrate the technical solutions of the exemplary embodiments of the present invention more clearly, the following briefly introduces the drawings used in describing the embodiments. Apparently, the drawings introduced are only the drawings of a part of the embodiments to be described in the present invention, rather than all the drawings. Those of ordinary skill in the art can also obtain the Other attached drawings.

FIG. 1 is a schematic top view structure diagram of an existing wafer;

2 is a schematic cross-sectional structure diagram of a semiconductor package formed in each step of a conventional manufacturing method of a semiconductor package;

3 is a schematic flowchart of a method for manufacturing a semiconductor package provided by an embodiment of the present invention;

4 is a schematic structural diagram of a semiconductor package formed in each step of a method for manufacturing a semiconductor package provided by an embodiment of the present invention;

5 is a schematic structural diagram of a semiconductor package formed in each step of another semiconductor package manufacturing method provided by an embodiment of the present invention;

FIG. 6 is a schematic flowchart of another method for manufacturing a semiconductor package provided by an embodiment of the present invention;

7 is a schematic structural diagram of a semiconductor package formed in each step of another semiconductor package manufacturing method provided by an embodiment of the present invention;

FIG. 8 is a schematic flowchart of a method for manufacturing a second wiring structure provided by an embodiment of the present invention;

9 is a schematic structural diagram of a second wiring structure formed in each step of a manufacturing method of a second wiring structure according to an embodiment of the present invention;

10 is a schematic structural diagram of a semiconductor package formed in each step of another semiconductor package manufacturing method provided by an embodiment of the present invention;

FIG. 11 is a schematic structural diagram of a semiconductor package provided by an embodiment of the present invention;

FIG. 12 is a schematic structural diagram of another semiconductor package provided by an embodiment of the present invention.

Detailed ways

The application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present application, but not to limit the present application. In addition, it should be noted that, for the convenience of description, only some structures related to the present application are shown in the drawings but not all structures.

Fig. 1 is a schematic top view structure diagram of a wafer in the prior art, Fig. 2 is a schematic cross-sectional structure diagram of a semiconductor package formed in each step of a semiconductor package manufacturing method, the semiconductor package formed in Fig. 2 steps The structure is along the section structure of AA' in Fig. 1 . With reference to Fig. 1 and Fig. 2, the existing manufacturing method of semiconductor package includes:

S11 , placing a plurality of semiconductor elements 11 on the wafer 12 .

S12 , plastic-encapsulate the semiconductor element 11 to form the first plastic-encapsulation layer 13 ; grind the first plastic-encapsulation layer 13 to expose the leads of the semiconductor element 11 .

S13 , forming multilayer wiring layers 14 in descending order of precision on the semiconductor element 11 .

Specifically, in the prior art, it is necessary to adopt a wafer-level process to directly fabricate the multilayer wiring layer 14 on the wafer 12 sequentially. There is a certain distance between the electrically connected high-precision multilayer wiring layers 14 , which causes waste of the wafer 12 , making the utilization rate of the wafer 12 low.

In view of this, an embodiment of the present invention provides a method for manufacturing a semiconductor package, and the method may be suitable for manufacturing a package including a plurality of semiconductor elements. Fig. 3 is a schematic flow chart of a manufacturing method of a semiconductor package provided by an embodiment of the present invention, and Fig. 4 is a schematic structural view of a semiconductor package formed in each step of a manufacturing method of a semiconductor package provided by an embodiment of the present invention, as shown in FIG. As shown in Figure 3, the manufacturing method of the semiconductor package includes:

S110, providing a first substrate.

Exemplarily, as shown in FIG. 4 , a first substrate 110 is provided. Optionally, the first substrate can be used in a panel-level process, for example: the first substrate can be glass, copper plate or steel plate. Compared with wafer-level The substrate under the panel-level process is larger in size, and the use of the panel-level process is conducive to the production of more semiconductor packages on the basis of larger substrates, which is conducive to the mass production of semiconductor packages.

S120, disposing a first wiring structure on the first substrate.

Wherein, the first wiring structure includes at least two first wiring layers, and a first insulating layer is arranged between two adjacent first wiring layers; the first insulating layer includes a plurality of first through holes, Two adjacent layers of the first wiring layer are electrically connected through the first through hole.

Exemplarily, as shown in FIG. 4 , a first wiring structure 120 is provided on a first substrate 110. The first wiring structure 120 includes three layers of first wiring layers 121, and two adjacent layers of first wiring layers 121 are provided with The first insulating layer 122 ; the first insulating layer 122 includes a plurality of first through holes 123 , and two adjacent first wiring layers 121 are electrically connected through the first through holes 123 . Along the direction perpendicular to the first substrate 110 and along the direction from the first substrate 110 to the first wiring structure 120, the precision of the first wiring layer 121 gradually increases and the line width gradually decreases, which is beneficial to the first wiring structure 120. Continue to set the second wiring structure 130 with higher precision. FIG. 4 exemplarily shows that the first wiring structure 120 includes three layers of the first wiring layer 121. In practical applications, the number of layers of the first wiring layer 121 can be determined according to the size of the semiconductor package, the size of the semiconductor element 140, and the process accuracy. .

S130, providing at least one second wiring structure.

Wherein, each of the second wiring structures includes at least two second wiring layers; a second insulating layer is arranged between two adjacent second wiring layers of the same second wiring structure, and the second insulating layer A plurality of second through holes are included, and the second wiring layers of two adjacent layers are electrically connected through the second through holes.

Exemplarily, as shown in FIG. 4, two second wiring structures 130 are provided, wherein each second wiring structure 130 includes three layers of second wiring layers 131; A second insulating layer 132 is disposed between the wiring layers 131 , and the second insulating layer 132 includes a plurality of second through holes 133 , and two adjacent second wiring layers 131 are electrically connected through the second through holes 133 . Along the direction perpendicular to the first substrate 110 and along the direction in which the first wiring structure 120 points to the second wiring structure 130, the precision of the second wiring layer 131 gradually increases, and the line width gradually decreases, which is beneficial to the second wiring structure. 130 continues to set up the semiconductor element 140 . FIG. 4 exemplarily provides two second wiring structures 130, and each second wiring structure 130 includes three layers of second wiring layers 131. In practical applications, the number of second wiring structures 130 can be based on the number of semiconductor elements 140 Flexible setting, the number of layers of the second wiring layer 131 can be determined according to the size of the semiconductor package, the size of the semiconductor element 140 and the process precision.

Specifically, the distance between adjacent connection points on the side of the first wiring structure 120 close to the second wiring structure 130 will limit the distance between adjacent second wiring structures 130 . Exemplarily, as shown in FIG. 4, the spacing between adjacent connection points of the first wiring layer 121 closest to the second wiring structure 130 is S1, which determines that the spacing between adjacent second wiring structures 130 is S2, because The second wiring structures 130 in the embodiment of the present invention are independent of each other, so when designing the second wiring structure master, there is no need to consider the distance between adjacent second wiring structures, only need to cut the second wiring structure master After a plurality of independent second wiring structures 130 are formed, the distance between adjacent second wiring structures 130 can be set to S2. If the second wiring structure 130 is formed by a wafer-level process, then when designing the second wiring structure master, the distance limit between adjacent second wiring structures can be ignored, and the adjacent first wiring structure in the second wiring structure master The distance between the two wiring structures is small, which can reduce the distance between adjacent second wiring structures on the second wiring structure master, thereby increasing the number of second wiring structures in the second wiring structure master on a single wafer, thereby improving the wafer The utilization rate of the circle reduces the production cost.

S140. Electrically connect the plurality of second wiring structures to a side of the first wiring structure away from the first substrate.

Exemplarily, as shown in FIG. 4 , multiple second wiring structures 130 are electrically connected to the side of the first wiring structure 120 away from the first substrate 110 , and the second wiring structures 130 are electrically connected to one semiconductor element 140 in one-to-one correspondence. In other implementation manners, two or more semiconductor elements 140 may also be electrically connected to one second wiring structure 130 , which is not specifically limited in this application.

S150, providing at least one semiconductor element; each semiconductor element includes a plurality of pins.

Exemplarily, as shown in FIG. 4 , at least one semiconductor element 140 is provided, each semiconductor element 140 includes two pins 141 , and the pins 141 are used for electrical connection with the second wiring structure 130 . The semiconductor element 140 may be a bare die fabricated on a wafer using a wafer-level process. In other implementation manners, each semiconductor element 140 may also include three or more pins 141 , which is not specifically limited in the present application.

S160, disposing a side of the semiconductor element provided with pins on a side of the second wiring structure away from the first substrate.

Exemplarily, as shown in FIG. 4 , the side of the semiconductor element 140 provided with the lead 141 is disposed on the side of the second wiring structure 130 away from the first substrate 110 . In the second wiring structure 130, the second wiring layer 131 closest to the semiconductor element 140 has the smallest line width and the highest precision, and the farther away from the semiconductor element 140, the second wiring layer 131 has a larger line width and lower precision. The size of the structure 130 is larger than the size of the semiconductor element 140 . The first wiring structure 120 is located on the side of the second wiring structure 130 away from the semiconductor element 140, the first wiring layer 121 of the first wiring structure 120 closest to the first substrate 110 has the largest line width and the smallest precision, and the farther away from the semiconductor element 140 The larger the line width of the first wiring layer 121, the smaller the precision. Therefore, the size of the first wiring structure 120 is larger than the size of all the second wiring structures 130 electrically connected to the first wiring structure 120, that is, the size of the semiconductor element 140 smaller than the size of the semiconductor package.

In the technical solution provided by the embodiment of the present invention, at least one fabricated semiconductor element is arranged by arranging at least one fabricated second wiring structure on the side of the first wiring structure away from the first substrate, and electrically connecting with the first wiring structure. The semiconductor element is arranged on the side of the second wiring structure away from the first substrate, and is electrically connected to the first wiring structure through the second wiring structure. Since each second wiring structure is independent of each other, when designing the second wiring structure master, there is no need to consider the distance between adjacent second wiring structures, and it is only necessary to form a plurality of independent second wiring structures after cutting the second wiring structure master. After wiring the structures, the distance between adjacent second wiring structures can be adjusted. If a wafer-level process is used to form the second wiring structure, when designing the second wiring structure master, the spacing limitation between adjacent second wiring structures can be ignored, and the adjacent second wiring in the second wiring structure master can be set The pitch of the structure is small, thereby increasing the quantity of the second wiring structure in the master plate of the second wiring structure on a single wafer, thereby improving the utilization rate of the wafer and reducing the production cost.

It should be noted that FIG. 3 and FIG. 4 only illustrate a semiconductor package including a plurality of semiconductor elements 140. When the semiconductor package needs to implement multiple functions, for example, the semiconductor package implements analog-to-digital conversion and digital signal processing. Function, the semiconductor components that realize analog-to-digital conversion and the semiconductor components that realize digital signal processing can be packaged together to save space. In practical applications, the semiconductor package can only realize a single function, so the semiconductor package can include a semiconductor element, the preparation process of the semiconductor package is shown in Figure 5, and Figure 5 shows two semiconductor packages by way of example, Adjacent packages are insulated from each other.

Optionally, continuing to refer to FIG. 4 , the line width of the second wiring layer 131 is smaller than the line width of the first wiring layer 121 .

Exemplarily, as shown in FIG. 4 , the distance between the pins 141 in the semiconductor element 140 is small, and the distance between the connection points of the semiconductor package is relatively large, so that the semiconductor package can be electrically connected to an external circuit. . The distance between the connection points on the first wiring layer 121 closest to the first substrate 110 is the distance between the connection points of the semiconductor package, and the distance between the connection points on the second wiring layer 131 closest to the semiconductor element 140 is the pin. The distance between 141, in order to realize that the distance between the connection points of the semiconductor package is greater than the distance between the pins 141 in the semiconductor element 140, along the direction perpendicular to the first substrate 110, and along the semiconductor element 140 pointing to the first In the direction of the substrate 110 , the line width of the wiring layer gradually increases and the accuracy gradually decreases, that is, the line width of the second wiring layer 131 is smaller than the line width of the first wiring layer 121 .

Optionally, the semiconductor element includes a first semiconductor element and a second semiconductor element; a vertical projection of the first semiconductor element on the first substrate is larger than a vertical projection of the second semiconductor element on the first substrate. FIG. 6 is a schematic flow chart of another method for manufacturing a semiconductor package provided by an embodiment of the present invention, and FIG. 7 is a schematic structural diagram of a semiconductor package formed in each step of a method for manufacturing a semiconductor package provided by an embodiment of the present invention. , as shown in Figure 6, the manufacturing method of the semiconductor package includes:

S110, providing a first substrate.

S120, disposing a first wiring structure on the first substrate.

S130, providing at least one second wiring structure.

S140. Electrically connect the plurality of second wiring structures to a side of the first wiring structure away from the first substrate.

S150, providing at least one semiconductor element; each semiconductor element includes a plurality of pins.

Exemplarily, as shown in FIG. 7, the semiconductor element 140 includes a first semiconductor element 140a and a second semiconductor element 140b, a first semiconductor element 140a and a second semiconductor element 140b are provided, and the first semiconductor element 140a is formed on the first substrate The vertical projection on 110 is larger than the vertical projection of the second semiconductor element 140b on the first substrate 110 , that is, the distance between the internal leads 141 of the first semiconductor element 140a is greater than the distance between the internal leads 141 of the second semiconductor element 140b. FIG. 6 only exemplarily shows that the semiconductor element 140 includes a first semiconductor element 140a and a second semiconductor element 140b. In practical applications, the number of the first semiconductor element 140a and the second semiconductor element 140b is not limited.

S161, arranging the side of the first semiconductor element provided with pins on the side of the first wiring structure away from the first substrate; arranging the side of the second semiconductor element provided with pins on The side of the second wiring structure away from the first substrate.

Exemplarily, as shown in FIG. 7, the distance between the internal pins 141 of the first semiconductor element 140a is large enough to match the line width of the first wiring layer 121 closest to the second semiconductor element 140b. Therefore, the second A side of a semiconductor element 140 a provided with pins is disposed on a side of the first wiring structure 120 away from the first substrate 110 , and the first semiconductor element 140 a is directly electrically connected to the first wiring structure 120 . However, the distance between the internal pins 141 of the second semiconductor element 140b is too small to match the line width of the first wiring layer 121, because the line width of the second wiring layer 131 is smaller than the line width of the first wiring layer 121, so , the distance between the internal pins 141 of the second semiconductor element 140b can match the line width of the second wiring layer 131, and the side of the second semiconductor element 140b provided with pins is arranged on the second wiring structure 130 away from the first substrate 110 , the second semiconductor element 140 b is electrically connected to the first wiring structure 120 through the second wiring structure 130 .

In the embodiment of the present invention, by disposing the small-sized semiconductor element on the side of the second wiring structure 130 away from the first substrate 110, and disposing the large-sized semiconductor element on the side of the first wiring structure 120 away from the first substrate 110, it is possible to Wiring structures are respectively provided for semiconductor elements of different sizes, so that the wiring structures of large-sized semiconductor elements can be simplified.

Optionally, when step S140 is executed, the specific steps include:

S141. Detect whether each of the second wiring structures is qualified.

S142. Electrically connect the qualified second wiring structure to a side of the first wiring structure away from the first substrate.

Specifically, after making the second wiring structure, check whether each second wiring structure is qualified, reject the unqualified second wiring structure, and arrange the qualified second wiring structure on the side of the first wiring structure away from the first substrate , so that the second wiring structure is electrically connected to the first wiring structure. Since the second wiring structures are independent of each other, the damage of a single second wiring structure will not affect other second wiring structures, and the de-correlation between the second wiring structures is realized, thereby improving the utilization of the second wiring structures rate, if the second wiring structure is fabricated on the wafer using wafer-level technology, the second wiring structure on the master plate of the second wiring structure is unqualified, and after cutting, the unqualified second wiring structure will not affect other second wiring structures The performance of the structure avoids scrapping the entire wafer due to unqualified part of the second wiring structure, thereby improving the utilization rate of the wafer and saving costs.

Optionally, when step S160 is performed, the arrangement position of the semiconductor element may also be adjusted according to the position of the second wiring structure.

Specifically, since there are offset and error positions in the process of manufacturing the second wiring structure and the process of electrically connecting a plurality of second wiring structures with the first wiring structure, adjusting the position of the semiconductor element can improve the performance of the semiconductor element. The alignment accuracy between the pin and the connection point of the second wiring structure is improved, thereby improving the yield rate of the semiconductor package.

Optionally, FIG. 8 is a schematic flowchart of a method for manufacturing a second wiring structure provided by an embodiment of the present invention, and FIG. A structural schematic diagram of the wiring structure, as shown in FIG. 8, the method for making the second wiring structure includes:

S131, providing a second substrate.

Exemplarily, as shown in FIG. 9 , a second substrate 134 is provided, and the second substrate 134 may be a wafer used in a wafer-level process. Compared with the panel-level process, the wafer-level process has a smaller line width and higher precision, so the second wiring structure 130 with higher precision and smaller line width can be formed.

S132. Arrange at least two layers of the second wiring layer on the second substrate, and a second insulating layer is arranged between two adjacent layers of the second wiring layer; the second insulating layer includes a plurality of second wiring layers. Through holes, the second wiring layers of two adjacent layers are electrically connected through the second through holes, so as to form a second wiring structure master.

Exemplarily, as shown in FIG. 9, three layers of second wiring layers 131 are arranged on the second substrate 134, and a second insulating layer 132 is arranged between two adjacent layers of second wiring layers 131; the second insulating layer 132 includes A plurality of second through holes 133, through which two adjacent second wiring layers 131 are electrically connected to form a second wiring structure master 130a. Optionally, the accuracy of the second wiring layer 131 fabricated on the second substrate 134 is stacked and arranged sequentially from low to high, so as to match the line width of the first wiring structure 120 and the pitch of the internal pins 141 of the semiconductor element 140 respectively. . FIG. 9 only exemplarily shows that three layers of second wiring layers 131 are disposed on the second substrate 134 . In practical applications, it is determined according to the size of the semiconductor package, the size of the semiconductor element 140 and the precision of the process.

S133, cutting the second wiring structure master, and peeling off the second substrate to form a plurality of second wiring structures.

Exemplarily, as shown in FIG. 9 , the second wiring structure master 130 a is cut, and the second substrate 134 is peeled off to form a plurality of second wiring structures 130 . After cutting the second wiring structure master 130a, multiple independent second wiring structures 130 are formed. There are offsets and errors in the process of making the first wiring structure, and the second wiring can be flexibly adjusted according to the offset and error of the first wiring structure. The position of the structure 130 is used to improve the alignment accuracy between the second wiring structure 130 and the first wiring structure, thereby improving the yield of the semiconductor package.

Optionally, after performing step S160, the manufacturing method of the semiconductor package further includes:

S170, plastic-encapsulate the semiconductor element.

Exemplarily, FIG. 10 is a structural schematic diagram of a semiconductor package formed in each step of another semiconductor package manufacturing method provided by an embodiment of the present invention. The side of the semiconductor element 140 provided with pins 141 is provided on the second wiring After the side of the structure 130 facing away from the first substrate 110 , the semiconductor element 140 is molded to form a molded structure 150 , as shown in FIG. 10 . The material of the plastic encapsulation structure 150 includes epoxy resin molding compound, for example, the plastic encapsulation structure 150 is formed by an injection molding process. Optionally, a plastic encapsulation structure 150 is formed on the side of the first wiring structure 120 and the second wiring structure 130 away from the first substrate 110 and around the semiconductor element 140, that is, the plastic encapsulation structure 150 covers the semiconductor element 140, and the plastic encapsulation structure 150 can realize The semiconductor device 140 is protected, and a heat dissipation path is provided for the semiconductor device 140 .

S180, peeling off the first substrate.

S190, planting balls on a side of the first wiring structure away from the semiconductor element to form solder balls.

Exemplarily, as shown in FIG. 10 , the first substrate 110 is peeled off to expose the first wiring layer 121 with the lowest precision, and balls are planted on the side of the first wiring structure 120 away from the semiconductor element 140 to form solder balls 160. The solder balls 160 It is electrically connected to the first wiring layer 121 with the lowest precision to realize the electrical connection between the solder ball 160 and the pin 141 of the semiconductor element 140 . The solder ball 160 is the connection point of the semiconductor package, and is used to realize the wire connection between the pin 141 of the semiconductor element 140 and the external circuit. Optionally, the solder ball 160 may be formed of metals such as tin, lead, copper, silver, gold or alloys thereof.

Optionally, after step S160 is performed, the following steps need to be performed:

S1100, cutting the first wiring structure to form a plurality of semiconductor packages; each of the semiconductor packages includes at least one semiconductor element.

Exemplarily, the first wiring structure is cut to form a plurality of semiconductor packages, and each semiconductor package includes two semiconductor elements. If the semiconductor elements are bare crystals, a multi-chip package is formed; if the sizes of the semiconductor elements are different, Packages for chips of different sizes can be formed.

Based on the same inventive concept, an embodiment of the present invention further provides a semiconductor package, which is formed by using any method for manufacturing a semiconductor package provided in the above-mentioned application embodiments.

FIG. 11 is a schematic structural diagram of a semiconductor package provided by an embodiment of the present invention. As shown in FIG. 11, the semiconductor package 100 includes:

The first wiring structure 120, wherein the first wiring structure 120 includes at least two first wiring layers 121, a first insulating layer 122 is arranged between two adjacent first wiring layers 121, and the first insulating layer 122 includes a plurality of The first through hole 123 electrically connects two adjacent first wiring layers 121 through the first through hole 123 .

At least one second wiring structure 130, wherein each second wiring structure 130 includes at least two second wiring layers 131, a second insulating layer 132 is arranged between adjacent two second wiring layers 131, and the second insulating layer 132 includes a plurality of second through holes 133 through which two adjacent second wiring layers 131 are electrically connected. A plurality of second wiring structures 130 are located on one side of the first wiring structure 120 , and each second wiring structure 130 is electrically connected to the first wiring structure 120 .

At least one semiconductor element 140 , each semiconductor element 140 includes a plurality of pins 141 ; the semiconductor element 140 is located on the side of the second wiring structure 130 away from the first wiring structure 120 , and the semiconductor element 140 is electrically connected to the first wiring structure 120 .

Exemplarily, as shown in FIG. 11 , the first wiring structure 120 includes three first wiring layers 121 , and each second wiring structure 130 includes three second wiring layers 131 . The distance between adjacent connection points of the first wiring structure 120 on the side close to the second wiring structure 130 will limit the distance between adjacent second wiring structures 130 . Exemplarily, the spacing between adjacent connections on the first wiring layer 121 closest to the second wiring structure 130 is S1, which determines that the spacing between adjacent second wiring structures 130 is S2. The second wiring structures 130 are independent of each other, so when designing the second wiring structure master, there is no need to consider the distance between adjacent second wiring structures, and only need to cut the second wiring structure master to form a plurality of independent first wiring structures. After the second wiring structure 130 , the distance between adjacent second wiring structures 130 can be set to S2 . If the second wiring structure 130 is formed by a wafer-level process, then when designing the second wiring structure master, the distance limit between adjacent second wiring structures can be ignored, and the adjacent first wiring structure in the second wiring structure master The distance between the two wiring structures is small, which can reduce the distance between adjacent second wiring structures on the second wiring structure master, thereby increasing the number of second wiring structures in the second wiring structure master on a single wafer, thereby improving the wafer The utilization rate of the circle reduces the production cost.

It should be noted that FIG. 11 only exemplarily shows that the first wiring structure 120 includes three layers of first wiring layers 121, and each second wiring structure 130 includes three layers of second wiring layers 131. In practical applications, for the first The number of layers of the wiring layer 121 and the second wiring layer 131 is not specifically limited.

Optionally, continuing to refer to FIG. 11 , the line width of the second wiring layer 131 is smaller than the line width of the first wiring layer 121 .

Exemplarily, as shown in FIG. 11 , the distance between the pins 141 in the semiconductor element 140 is small, and the distance between the connection points of the semiconductor package 100 is relatively large, so that the semiconductor package 100 can be connected with an external circuit. electrical connection. The distance between the connection points on the first wiring layer 121 farthest from the second wiring structure 130 is the distance between the connection points of the semiconductor package 100, and the distance between the connection points on the second wiring layer 131 closest to the semiconductor element 140 is The distance between the pins 141, in order to realize that the distance between the connection points of the semiconductor package is greater than the distance between the pins 141 in the semiconductor element 140, is along a direction perpendicular to the plane where the first wiring structure 120 is located, and along the semiconductor The element 140 points to the direction of the first wiring structure 120 , the line width of the wiring layer gradually increases, and the precision gradually decreases, that is, the line width of the second wiring layer 131 is smaller than the line width of the first wiring layer 121 .

Optionally, FIG. 12 is a schematic structural diagram of another semiconductor package provided by an embodiment of the present invention. As shown in FIG. 11, the semiconductor element 140 includes a first semiconductor element 140a and a second semiconductor element 140b. The vertical projection of the first semiconductor element 140a on the plane where the first wiring structure 120 is located is larger than that of the second semiconductor element 140b on the plane of the first wiring structure. Vertical projection on the plane where 120 is located.

Wherein, the side of the first semiconductor element 140 a provided with the pin 141 is located on the side of the first wiring structure 120 close to the second wiring structure 130 , and the first semiconductor element 140 a is electrically connected to the first wiring structure 120 . The side of the second semiconductor element 140 b provided with the pin 141 is located on the side of the second wiring structure 130 away from the first wiring structure 120 , and the second semiconductor element 140 b is electrically connected to the first wiring structure 120 through the second wiring structure 130 .

Exemplarily, as shown in FIG. 12, the semiconductor element 140 includes a first semiconductor element 140a and a second semiconductor element 140b, and the vertical projection of the first semiconductor element 140a on the plane where the first wiring structure 120 is located is larger than that of the second semiconductor element 140a. The vertical projection of 140b on the plane where the first wiring structure 120 is located means that the distance between the internal pins 141 of the first semiconductor element 140a is greater than the distance between the internal pins 141 of the second semiconductor element 140b. The distance between the internal pins 141 of the first semiconductor element 140a is large enough to match the line width of the first wiring layer 121 closest to the second semiconductor element 140b. Therefore, the first semiconductor element 140a is directly connected to the first wiring structure 120 electrical connection. However, the distance between the internal pins 141 of the second semiconductor element 140b is too small to match the line width of the first wiring layer 121, because the line width of the second wiring layer 131 is smaller than the line width of the first wiring layer 121, so The distance between the internal pins 141 of the second semiconductor element 140 b can match the line width of the second wiring layer 131 , and the second semiconductor element 140 b is electrically connected to the first wiring structure 120 through the second wiring structure 130 .

In the embodiment of the invention, by disposing the small-sized semiconductor element on the side of the second wiring structure 130 away from the first wiring structure 120, and disposing the large-sized semiconductor element on the side of the first wiring structure 120 away from the first substrate 110, it is possible to Wiring structures are respectively provided for semiconductor elements of different sizes, so that the wiring structures of large-sized semiconductor elements can be simplified.

It should be noted that FIG. 12 only exemplarily shows that the semiconductor element 140 includes a first semiconductor element 140a and a second semiconductor element 140b. In practical applications, the number of the first semiconductor element 140a and the second semiconductor element 140b is different Make specific restrictions.

Optionally, referring to FIG. 11 , the line width of the first wiring layer 121 on the side of the first wiring structure 120 close to the second wiring structure 130 is smaller than that of the first wiring on the side of the first wiring structure 120 away from the second wiring structure 130 Layer 121 line width.

The line width of the second wiring layer 131 on the side of the second wiring structure 130 away from the first wiring structure 120 is smaller than the line width of the second wiring layer 131 on the side of the second wiring structure 130 close to the first wiring structure 120 .

Exemplarily, as shown in FIG. 11 , along a direction perpendicular to the plane where the first wiring structure 120 is located, and along the first wiring structure 120 toward the wiring structure 130 , the line width of the first wiring layer 121 in the first wiring structure 120 gradually The precision gradually increases, and the distance between the connection points of the semiconductor package 100 can be shortened through the first wiring structure 120 to ensure that the connection points of the semiconductor package 100 can be electrically connected to the pins 141 of the semiconductor element 140 . Along the direction perpendicular to the plane where the first wiring structure 120 is located, and along the first wiring structure 120 to the wiring structure 130, the line width of the second wiring layer 131 in the second wiring structure 130 gradually decreases, and the accuracy gradually increases. Through the second The wiring structure 130 further reduces the distance between the connection points of the semiconductor package 100 to ensure that the connection points of the semiconductor package 100 can be electrically connected to the semiconductor element 140 with a smaller size.

Optionally, referring to FIG. 11 and FIG. 12 , the semiconductor package 100 further includes:

The solder ball 160 is located on a side of the first wiring structure 120 away from the second wiring structure 130 , and the solder ball 160 is electrically connected to the first wiring structure 120 .

The plastic encapsulation structure 150 at least surrounds the semiconductor element 140 and the second wiring structure 130 .

Exemplarily, as shown in FIG. 11 and FIG. 12, the first wiring layer 121 on the side of the first wiring structure 120 away from the second wiring structure 130 is electrically connected to the solder ball 160, and the solder ball 160 is connected to the first wiring layer with the lowest precision. 121 is electrically connected to realize the electrical connection between the solder ball 160 and the pin 141 of the semiconductor element 140 . The solder ball 160 is the connection point of the semiconductor package 100 , and is used to realize the wire connection between the pin 141 of the semiconductor element 140 and the external circuit. The plastic encapsulation structure 150 surrounds the semiconductor element 140 and the second wiring structure 130 , can protect the semiconductor element 140 and the second wiring structure 130 , and provide a heat dissipation path for the semiconductor element 140 . Optionally, the plastic encapsulation structure 150 may also surround the first wiring structure 120 to protect the first wiring structure 120 .

The foregoing are only preferred embodiments of the present invention and the applied technical principles. The present invention is not limited to the specific embodiments here, and various obvious changes, readjustments and substitutions that can be made by those skilled in the art will not depart from the protection scope of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and can also include more other equivalent embodiments without departing from the concept of the present invention, and the present invention The scope is determined by the scope of the claims.

Claims (9)

1. A method of fabricating a semiconductor package, comprising:

providing a first substrate;

providing a first wiring structure on the first substrate; the first wiring structure comprises at least two first wiring layers, and a first insulating layer is arranged between every two adjacent first wiring layers; the first insulating layer comprises a plurality of first through holes, and two adjacent first wiring layers are electrically connected through the first through holes;

providing a plurality of second wiring structures formed in advance; each second wiring structure comprises at least two second wiring layers; a second insulating layer is arranged between two adjacent second wiring layers of the same second wiring structure, the second insulating layer comprises a plurality of second through holes, and the two adjacent second wiring layers are electrically connected through the second through holes;

wherein a plurality of the second wiring structures are formed by cutting a second wiring structure motherboard and are mutually independent;

electrically connecting a plurality of the second wiring structures with a side of the first wiring structure facing away from the first substrate;

providing at least one semiconductor element; each semiconductor element comprises a plurality of pins;

and arranging one side of the semiconductor element, on which the pins are arranged, on one side of the second wiring structure, which is away from the first substrate.

2. The method of manufacturing a semiconductor package according to claim 1, wherein a line width of the second wiring layer is smaller than a line width of the first wiring layer.

3. The method of manufacturing a semiconductor package according to claim 2, wherein the semiconductor element includes a first semiconductor element and a second semiconductor element; the vertical projection of the first semiconductor element on the first substrate is larger than the vertical projection of the second semiconductor element on the first substrate;

the step of disposing the side of the semiconductor element provided with the pins on the side of the second wiring structure facing away from the first substrate includes:

arranging one side of the first semiconductor element, on which the pins are arranged, on one side of the first wiring structure, which is away from the first substrate; and arranging one side of the second semiconductor element, on which the pins are arranged, on one side of the second wiring structure, which is away from the first substrate.

4. The method of manufacturing a semiconductor package according to claim 1, wherein the electrically connecting the plurality of second wiring structures and the side of the first wiring structure facing away from the first substrate further comprises:

detecting whether each second wiring structure is qualified;

and electrically connecting the qualified second wiring structure with one side of the first wiring structure, which is away from the first substrate.

5. The method according to claim 1, wherein when the side of the semiconductor element on which the leads are provided is disposed on the side of the second wiring structure away from the first substrate, further comprising:

and adjusting the setting position of the semiconductor element according to the position of the second wiring structure.

6. The method of manufacturing a semiconductor package according to claim 1, wherein said providing at least one second wiring structure comprises:

providing a second substrate;

at least two layers of second wiring layers are arranged on the second substrate, and a second insulating layer is arranged between two adjacent layers of second wiring layers; the second insulating layer comprises a plurality of second through holes, and two adjacent layers of second wiring layers are electrically connected through the second through holes so as to form a second wiring structure mother board;

cutting the second wiring structure mother plate, and stripping the second substrate to form a plurality of second wiring structures.

7. The method of manufacturing a semiconductor package according to claim 6, wherein,

the first substrate comprises glass, steel plate or copper plate;

the second substrate includes a wafer.

8. The method according to claim 1, wherein the step of disposing the side of the semiconductor element on which the leads are disposed on the side of the second wiring structure away from the first substrate, further comprises:

plastic packaging the semiconductor element;

stripping the first substrate;

and implanting balls at one side of the first wiring structure, which is away from the semiconductor element, to form solder balls.

9. The method according to claim 1, wherein the step of disposing the side of the semiconductor element on which the leads are disposed on the side of the second wiring structure away from the first substrate, further comprises:

dicing the first wiring structure to form a plurality of the semiconductor packages; each of the semiconductor packages includes at least one of the semiconductor elements.

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