CN112164418B - A memory single event effect testing system, method and device - Google Patents
A memory single event effect testing system, method and device Download PDFInfo
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Abstract
本申请公开了一种存储器单粒子效应的测试系统、方法及装置，所述测试系统包括辐照板，其上设置有存储器；测试板，其上设置有FPGA器件，所述FPGA器件与所述存储器电连接，对所述存储器进行数据写入和/或数据读出；发射装置，用于发射重离子微束；控制平台，用于控制所述辐照板相对所述发射装置进行水平和/或上下位移；其中，所述FPGA器件上设置有第一反馈线路和第二反馈线路，分别用于输出不同的单粒子效应反馈信号。本申请实施例通过为不同单粒子效应设置不同的反馈线路和反馈机制，使得被测器件上的单粒子翻转效应区域和单粒子瞬态效应区域能够得到快速识别。
The present application discloses a test system, method and device for memory single event effect. The test system includes an irradiation board on which a memory is provided; a test board on which is provided an FPGA device, the FPGA device and the The memory is electrically connected to write data and/or read data to the memory; the emission device is used to emit heavy ion microbeams; the control platform is used to control the irradiation plate to level and/or relative to the emission device Or up and down displacement; wherein, the FPGA device is provided with a first feedback circuit and a second feedback circuit, which are respectively used to output different single event effect feedback signals. In the embodiments of the present application, by setting different feedback circuits and feedback mechanisms for different single-event effects, the single-event inversion effect area and the single-event transient effect area on the device under test can be quickly identified.
Description
Technical Field
The application relates to the technical field of single event effect testing, in particular to a system, a method and a device for testing single event effect of a memory.
Background
With the development of aerospace technology, people's demand for aerospace tasks is increasing day by day, and more electronic components are applied to aerospace systems. The electronic components are affected by the space radiation environment and often fail, thereby bringing devastating attacks to the whole system and even the whole spacecraft. The failures are mainly caused by radiation effects of high-energy particles and rays in the space on electronic components, including Single Event Effect (SEE), total dose Effect, displacement loss Effect and the like. The single event effect causes the most serious influence, and the damage events of the spacecraft caused by the single event effect account for 70 percent of all the damage events of the spacecraft according to statistics. The definition of the single event effect means that single high-energy particles such as protons, neutrons, heavy ions and the like in a space radiation environment are incident into an electronic component and interact with a device material to generate a large number of electron-hole pairs, and the electron-hole pairs are collected at certain sensitive circuit nodes in the device and influence or even destroy the normal operation of the device through a series of butterfly effects.
The single particle effect can be further divided into: soft errors such as Single Event Upset (SEU) and Single Event Transient (SET), and hard errors such as Single event latch-up and Single event burnout. The single event upset is the upset of data of some memory cells in the memory, and the upset is always kept in the memory; the single-event transient effect is that the read function of the memory cannot be correctly executed due to the fact that the single-event effect generates transient current at certain circuit nodes of a chip layout, although a large amount of error data are read out, the data in the memory are not turned over actually, and as long as the transient current is released and disappears, the recovery error of the read function disappears.
Existing microbeam scanning techniques include laser microbeam scanning and heavy ion microbeam scanning. For example, the application number CN201310675790.9 entitled "an experimental method for laser single event effect back irradiation of memory circuit" uses laser microbeam to enter from the back of the memory, thereby obtaining a single event effect sensitive node of the device. The laser microbeam can simulate the single event effect rule caused by the heavy ion microbeam to a certain extent, but the single event effect test cannot be completely replaced by the heavy ion microbeam due to the difference of physical mechanisms, and the test result of the technology cannot accurately represent the physical mechanism of the single event effect; the application number CN201711248623.0 entitled "positioning the sensitive region of the sige transistor based on the heavy ion microbeam" positions the sensitive region of the sige transistor by using the heavy ion microbeam. A problem with this heavy ion microbeam-based technique is that the test object is typically a single transistor.
Therefore, in a large-scale integrated circuit test experiment, how to overcome the problems of high price and short time and labor of heavy ion microbeam and quickly identify and determine a single-particle upset effect region and a single-particle transient effect region on a tested device, thereby providing effective reference for device design, and becoming a problem to be solved in the industry.
Disclosure of Invention
Objects of the invention
In order to overcome the defects in the prior art, the application provides a memory single event effect test system, method and device, wherein the test system enables a single event upset effect area and a single event transient effect area on a tested device to be rapidly identified by setting different feedback circuits and feedback mechanisms for different single event effects.
(II) technical scheme
In a first aspect, an embodiment of the present application provides a system for testing a single event effect of a memory, including:
an irradiation plate on which a memory is disposed;
the test board is provided with an FPGA device which is electrically connected with the memory and is used for writing data into and/or reading data out of the memory;
the emitting device is used for emitting the heavy ion microbeam;
the control platform is used for controlling the irradiation plate to horizontally and/or vertically displace relative to the transmitting device;
the FPGA device is provided with a first feedback circuit and a second feedback circuit which are respectively used for outputting different single event effect feedback signals.
In some embodiments, the first feedback line is configured to output a toggle effect feedback signal corresponding to an increase in the amount of erroneous data read from the memory by the FPGA device; the second feedback line is configured to output a transient effect feedback signal corresponding to a reduction in the amount of erroneous data read from the memory by the FPGA device.
In some embodiments, the FPGA device is connected to an upper computer.
In some embodiments, the upper computer comprises:
the test unit is used for indicating the FPGA device to write data into the memory and/or read data out of the memory and outputting different feedback signals according to the quantity change of read error data;
and the coordinate recording unit is used for receiving the feedback signal and reading the horizontal position coordinate of the irradiation plate relative to the emitting device when receiving the feedback signal.
In a second aspect, an embodiment of the present application provides a method for testing a single event effect of a memory, including:
performing periodic heavy ion microbeam scanning on a subregion in a single event effect sensitive region of the memory by using the test system of any one of the first aspect;
reading all data in the memory through an FPGA device, and recording the number of error data in the read data in the ith scanning period as Ni, wherein i is a natural number which is more than or equal to 1;
when N is presentiGreater than Ni-1Then, a first feedback circuit of the FPGA device outputs a first feedback signal;
when N is presentiLess than Ni-1And then, a second feedback circuit of the FPGA device outputs a second feedback signal.
In some embodiments, after the first and second feedback lines of the FPGA device output the first and second feedback signals, respectively, the method further includes:
when the test board in the test system is connected with an upper computer, and the upper computer receives the first feedback signal or the second feedback signal, the upper computer obtains a first horizontal position coordinate of the irradiation board relative to the emitting device through the control platform, and marks a first sub-area corresponding to the first horizontal position coordinate as a single event upset effect generation area; or
And the upper computer acquires a second horizontal position coordinate of the irradiation plate relative to the emission device through the control platform, and records a second subregion corresponding to the second horizontal position coordinate as a single-event transient effect generation region.
In some embodiments, after recording the first sub-region or the second sub-region corresponding to the first or the second horizontal position coordinate as a single event upset effect occurrence region or a single event transient effect occurrence region, the method further includes:
the upper computer acquires a first quantity of the error data in the FPGA device simultaneously when acquiring the coordinate of the first horizontal position according to the first feedback signal;
the upper computer acquires a second quantity of the error data in the FPGA device simultaneously when acquiring the coordinate of the second horizontal position according to the second feedback signal;
taking the single event effect sensitive area as an XY plane;
rendering the first sub-area corresponding to the first horizontal position coordinate into a first color;
rendering the second sub-area corresponding to the second horizontal position coordinate into a second color;
taking the first number as the Z-axis height of the first subarea corresponding to the first color;
taking the second number as the Z-axis height of the second subarea corresponding to the second color;
and outputting a histogram on the XY plane according to the color, the horizontal position and the Z-axis height corresponding to the first sub-area or the second sub-area.
In some embodiments, before performing the periodic heavy ion microbeam scanning on the sub-region of the single event effect sensitive region of the memory using the test system of any of claims 1-4, the method further comprises:
determining a single event effect sensitive area on the surface of a chip layout of the memory by laser scanning;
and averagely dividing the single event effect sensitive area into a plurality of sub-areas according to the direction of XY coordinate axes.
In a third aspect, an embodiment of the present application provides a device for testing a single event effect of a memory, including:
a scanning module, configured to perform periodic heavy ion microbeam scanning on all sub-regions of the single event effect sensitive region of the memory one by using the test system according to any one of claims 1 to 4;
a reading module for reading all data in the memory through the FPGA device and recording the number of error data in the read data in the ith scanning period as NiI is a natural number greater than or equal to 1;
an output module for when NiGreater than Ni-1Then, a first feedback circuit of the FPGA device outputs a first feedback signal;
the output module is also used for counting NiLess than Ni-1And then, a second feedback circuit of the FPGA device outputs a second feedback signal.
In some embodiments, the test device further comprises:
the sensitive region determining module is used for determining a single event effect sensitive region on the surface of a chip layout of the memory by utilizing laser scanning;
and the sub-region dividing module is used for averagely dividing the single event effect sensitive region into a plurality of sub-regions according to the vertical and horizontal coordinates.
(III) advantageous effects
The method and the device have the advantages that the single event upset effect area and the single event transient effect area on the tested device can be rapidly identified by setting different feedback lines and feedback mechanisms for different single event effects.
Drawings
FIG. 1 is a block diagram of a test system according to an embodiment of the present application;
FIG. 2 is a schematic flow chart of a testing method according to an embodiment of the present application;
FIG. 3 is a diagram of a corresponding apparatus of the embodiment of FIG. 2;
FIG. 4(a) is a schematic diagram of a memory chip layout surface and a single event effect sensitive area therein determined by laser microbeam scanning in the embodiment of the present application;
FIG. 4(b) is a schematic diagram of a plurality of sub-regions into which the single event effect sensitive region in FIG. 4(a) is averagely divided;
FIG. 5 is a schematic diagram illustrating a single event upset effect and a single event transient effect of a memory according to an embodiment of the present application;
FIG. 6 is a schematic diagram of a feedback signal in an embodiment of the present application;
FIG. 7(a) is a schematic diagram of the distribution of the positions of the sub-regions with different effects in the single event effect sensitive region on the layout surface of the memory chip according to the embodiment of the present application;
fig. 7(b) is a histogram of different single event effect sub-regions on the surface of the memory chip layout in the embodiment of the present application on the XY plane determined by the single event effect sensitive region.
Reference numerals:
10: a test board; 11: an FPGA device; 111: a first feedback line; 112: a second feedback line.
20: an irradiation plate; 21: a memory.
30: and a transmitting device.
40: and (5) controlling the platform.
50: an upper computer; 51: a coordinate recording unit; 52: and a test unit.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is further described in detail below with reference to the accompanying drawings in combination with the detailed description. It should be understood that the description is intended to be exemplary only, and is not intended to limit the scope of the present application. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present application.
In the description of the present application, it is noted that the terms "first", "second", and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Fig. 1 is a block diagram of a test system according to an embodiment of the present application.
As shown in fig. 1, a system for testing single event effect of a memory includes:
an irradiation board 20 on which a memory 21 is provided;
the test board 10 is provided with an FPGA device 11, the FPGA device 11 is electrically connected with the memory 21, and data writing and/or data reading are carried out on the memory 21;
an emitting device 30 for emitting heavy ion microbeams;
the control platform 40 is used for controlling the irradiation plate 20 to horizontally and/or vertically displace relative to the emitting device 30;
the FPGA device 11 is provided with a first feedback line 111 and a second feedback line 112, which are respectively used for outputting different single event effect feedback signals.
Optionally, in some embodiments, the first feedback line 111 is configured to output a flip-effect feedback signal corresponding to an increase in the number of error data read from the memory 21 by the FPGA device 11; the second feedback line 112 is used to output a transient effect feedback signal corresponding to a reduction in the amount of erroneous data read by the FPGA device 11 from the memory 21.
The number of the error data is increased or decreased, and the number of the memory cells where the error data actually reflects is increased or decreased, because each memory cell stores the same data in the test, when all data in the memory is read out in each reading cycle, the number of the error data read out is actually the number of the memory cells where the single event effect occurs.
The single event upset effect can cause the data of some memory cells in the memory to be overturned, and the upset can be always kept in the memory. Therefore, the error data read in the next reading period is certainly not less than the error data read in the previous reading period, on the contrary, the occurrence of the flip effect in the storage can be determined through the comparison result that the number of the error data read in the next reading period is greater than the number of the error data read in the previous reading period, and at this time, the FPGA device 11 which reads and compares the data of the memory 21 can enable the first feedback line 111 to output a high level, that is, when the first feedback line 111 outputs a high level, the flip effect in the memory 21 is indicated.
The single-event transient effect is that the single-event effect generates transient current at some circuit nodes of a chip layout, so that the reading function of the memory cannot be correctly executed, although a large amount of error data is read out, the data in the memory is not inverted actually, and as long as the transient current is released and disappears, the reading function is recovered, and the number of the corresponding read error data is reduced. Similarly, conversely, the comparison result that the number of the error data read in the next read cycle is smaller than the number of the error data read in the previous read cycle can determine that the transient effect occurs in the memory, and at this time, the FPGA device 11 that reads and compares the data from the memory 21 can make the second feedback line 112 output a high level, that is, when the second feedback line 112 outputs a high level, it indicates that the transient effect occurs in the memory 21.
According to the embodiment, different feedback lines and feedback mechanisms are set for different single event effects, so that the single event upset effect region and the single event transient effect region on the tested device can be rapidly identified.
In some embodiments, the FPGA device 11 is connected to an upper computer 50.
Optionally, the upper computer 50 includes:
the test unit 52 is configured to instruct the FPGA device 11 to perform data writing and/or data reading on the memory 21, and output different feedback signals according to the number change of the read error data;
and the coordinate recording unit 51 is used for receiving the feedback signal and reading the horizontal position coordinate of the irradiation plate 20 relative to the emitting device 30 when receiving the feedback signal.
Fig. 2 is a schematic flowchart of a testing method according to an embodiment of the present application.
As shown in fig. 2, a method for testing single event effect of a memory includes:
s110: the test system of the embodiment is used for carrying out periodical heavy ion microbeam scanning on the subarea in the single event effect sensitive area of the memory;
s120: in the ith scanning period, reading all data in the memory through an FPGA device, and recording the number of error data in the memory as Ni, wherein i is a natural number more than or equal to 1;
s130: when Ni is larger than Ni-1, a first feedback circuit of the FPGA device outputs a first feedback signal;
s140: and when Ni is less than Ni-1, a second feedback line of the FPGA device outputs a second feedback signal.
In some embodiments, after the first and second feedback lines of the FPGA device output the first and second feedback signals, respectively, the method further includes:
when the test board in the test system is connected with an upper computer, and the upper computer receives the first feedback signal or the second feedback signal, the upper computer obtains a first horizontal position coordinate of the irradiation board relative to the emitting device through the control platform, and marks a first sub-area corresponding to the first horizontal position coordinate as a single event upset effect generation area; or
And the upper computer acquires a second horizontal position coordinate of the irradiation plate relative to the emission device through the control platform, and records a second subregion corresponding to the second horizontal position coordinate as a single-event transient effect generation region.
In some embodiments, after recording the first sub-region or the second sub-region corresponding to the first or the second horizontal position coordinate as a single event upset effect occurrence region or a single event transient effect occurrence region, the method further includes:
the upper computer acquires a first quantity of the error data in the FPGA device simultaneously when acquiring the coordinate of the first horizontal position according to the first feedback signal;
the upper computer acquires a second quantity of the error data in the FPGA device simultaneously when acquiring the coordinate of the second horizontal position according to the second feedback signal;
taking the single event effect sensitive area as an XY plane;
rendering the first sub-area corresponding to the first horizontal position coordinate into a first color;
rendering the second sub-area corresponding to the second horizontal position coordinate into a second color;
taking the first number as the Z-axis height of the first subarea corresponding to the first color;
taking the second number as the Z-axis height of the second subarea corresponding to the second color;
and outputting a histogram on the XY plane according to the color, the horizontal position and the Z-axis height corresponding to the first sub-area or the second sub-area. Optionally, the first color is red, and the second color is green.
This embodiment provides a methodological process for combining the final data with the chip layout surface of memory 21 to form a visible histogram of test results.
In some embodiments, before periodically scanning a heavy ion microbeam on a sub-region in a single event effect sensitive region of the memory by using a test system, determining the single event effect sensitive region on the chip layout surface of the memory by using laser scanning; and averagely dividing the single event effect sensitive area into a plurality of sub-areas according to the direction of XY coordinate axes.
The embodiment mainly aims to eliminate the influence of a non-sensitive area by using cheaper laser micro-beams, so that heavy ion micro-beam detection is more targeted, the beam utilization rate is improved, and the cost is reduced. And further, carrying out XY coordinate axis direction average division on the chip layout surface sensitive area of the memory 21 preliminarily determined by the laser microbeam to form a plurality of sub-areas, so that a histogram with strong visibility can be output by combining the sub-area division condition of the single event effect sensitive area.
Further implementation procedures of the above embodiments may include:
step 1: memory samples for testing were selected and pre-processed.
1a) And selecting a memory model and performing de-encapsulation processing.
In order to ensure good consistency of the tested memory devices, more than 15 devices were selected from the same batch of products from the same manufacturer as the experimental samples, in this example, the memory manufactured by cypress corporation, the device model being FM22L 16-55-TG. Because the penetration capacity of the laser microbeam and the heavy ion microbeam is limited, the experimental sample needs to be subjected to de-encapsulation treatment, a plastic encapsulation layer on the front surface of the chip is removed, and the chip layout is exposed.
1b) The devices are tested and selected.
The memory of 1a) is connected to the memory test system, the functional and electrical parameters of the device are checked, and the surface of the device is observed with a microscope. And selecting a device with normal read-write function, static current of more than 1mA, dynamic current of more than 10mA, clear layout and no pollution as a test sample.
Step 2: and designing a feedback signal of the single event upset and the single event transient from hardware.
2a) Signals SEU _ flag and SET _ flag are defined that flag SEU and SET effects.
The prior art for testing single event effect of electronic components generally relies on Field Programmable Gate Array (FPGA) devices in terms of hardware. Firstly, defining two empty pins of the FPGA as a feedback signal SEU _ flag and an SET _ flag by using a Verilog hardware language to mark the occurrence of a single event upset effect and a single event transient effect. And on the layout wiring of the PCB, the two signals are led out in an SMA interface mode and are respectively connected into an upper computer through two channels.
2b) The generation conditions of the SEU _ flag and the SET _ flag are SET.
As shown in fig. 5, which shows the expression of typical SEU and SET in the memory irradiation experiment, the variation trend of the number of errors in the memory and the test time has two characteristics: first, the number of errors rises in a step, which is caused by the single event upset effect (SEU); second, the number of errors increases abnormally and disappears rapidly at some point, which is caused by a Single Event Transient (SET) effect.
Therefore, the basis for judging the single event upset and the single event transient here is as follows: if the number of errors in the memory is increased, a single event upset effect occurs, and an SEU _ flag signal triggers; if the number of errors in the memory is reduced, the single event transient effect is considered to occur, and the SET _ flag signal is triggered.
The concrete implementation is as follows: in each test period i, the FPGA device on the test board will continuously read the error from the memory and count the number Ni, which is compared with the number Ni-1 of error cells read last time. If N is presenti-Ni-1>0, outputting a high-level digital signal from the SEU _ flag pin as a feedback signal; if N is presenti-Ni-1<And 0, outputting a high-level digital signal from the SET _ flag pin as a feedback signal, wherein the two high-level feedback signals have the same waveform parameter, and have the period of 30ms and the peak value of 3.3V as shown in FIG. 6.
It should be added that, in the above judgment bases for SEU and SET, the data number Ni read out in each test cycle refers to the number of cells where errors exist rather than the number of error data itself, that is, the number of addresses rather than the number of binary numbers. Between the two, each address contains a multi-bit binary (for the present example, each address can store a 16-bit binary). The reason for this is that due to the design of the peripheral circuits, single event effects (e.g., single event multi-bit flip) of some memories affect multi-bit binary data in the same address. It is simpler and more accurate to use the number of affected addresses as a basis for the determination.
2c) And designing and manufacturing the PCB required in the test.
Designing and manufacturing a PCB (printed circuit board) required by a test process, wherein as shown in FIG. 5, an FPGA (field programmable gate array) device and a test device are respectively and independently designed on a test board and an irradiation board, and the FPGA of the test board is connected with a signal of the test device on the irradiation board and effect feedback signals SEU _ flag and SET _ flag through a cable; the SEU _ flag and SET _ flag feedback signals are connected with an upper computer through an SMA interface; the test board is connected to the upper computer through a network cable and is controlled by the upper computer.
And step 3: and designing upper computer software to receive the SEE feedback signal.
And (3) designing upper computer software-a coordinate recording system by using a Labview program, wherein the system mainly realizes the identification and capture of the feedback signal in the step (1). First, the feedback signals SEU _ flag and SET _ flag in step 1 are captured via path A, B, respectively, and can be recognized by the upper computer software when their high levels are triggered. Secondly, the upper computer software can synchronize the coordinate information of the heavy ion microbeam moving platform, and when the feedback signal is triggered, the system can immediately record the incident coordinate of the heavy ions.
And 4, step 4: and roughly positioning the single event effect sensitive area by using the laser microbeam.
Because heavy ion microbeams are expensive and lack of beam current, the utilization efficiency of heavy ion beam current needs to be improved to the maximum extent. In the layout of the device, not all circuit modules are sensitive to the single event effect, so that a sensitive area in a chip needs to be preliminarily positioned. As mentioned in the background, although the laser microbeam cannot replace the heavy ion microbeam to perform the single event effect test, the laser microbeam can trigger the single event effect through photon energy, and thus can be used for initially positioning the SEE sensitive area. Furthermore, not all tests are required, even for sensitive areas. Since there are a large number of redundant cells (especially memory arrays of the memory) in a large scale integrated circuit layout, the purpose of this step is to initially locate some of the sensitive cells. Therefore, the cells do not need to be scanned completely, and only a part of the partial circuits with all the characteristics need to be scanned.
4a) And fixing and connecting the PCB irradiation board.
Connecting the whole test system according to the description in the step 2c), and fixing the irradiation PCB to the control platform of the laser microbeam.
4b) And moving the position of the control platform to focus the microscope on the surface of the chip layout.
Opening an optical imaging system above a laser microbeam control platform, firstly moving a tested device to the center of the visual field of a microscope by adjusting the positions of an X axis and a Y axis of the control platform, then adjusting the height of a Z axis of the control platform, focusing the microscope on the surface of a memory layout, and finally selecting a position with obvious characteristics as an origin O for identification.
4c) Scanning by a laser micro-beam, and roughly positioning the SEE sensitive area.
Data AA55 is written into the memory by a memory test system, and laser micro-beams with the step size of 100 mu m, the frequency of 40plus/s, the wavelength of 532nm and the energy of 4nj are selected to scan the whole chip area of the device. During the scan, the test system repeatedly reads the in-memory data and compares it with the previously written data AA55, and if the data has changed, the area is considered to be a SEE sensitive area. The test system records and counts the detailed information of all error data in the memory (including the number of error data, the address and the number of memory cells where the error data are located, and the like) and the coordinate information of the laser incidence position relative to the origin O.
It should be noted that, for the memory in this example, the laser wavelength selected in this step is 532nm, experiments show that the memory single event effect cannot be triggered from the front side by selecting laser with a wavelength of 1064nm, and the effect can be achieved only by irradiation from the back side.
4d) Dividing the roughly positioned region in 4c) into a plurality of regions
After the step 4c), the single event effect sensitive region of the memory is preliminarily determined, in this example, the result of testing the object memory is shown in fig. 4(a), and the single event effect sensitive region of the device is concentrated in the peripheral circuit region in the middle of the layout, namely, in the yellow frame in the drawing. Due to the large area of the SEE sensitive region which is preliminarily positioned, in order to facilitate the test by using the heavy ion microbeam, the whole sensitive region can be divided into a plurality of small regions C1/C2/C3 … …, as shown in FIG. 4 (b).
And 5: and further positioning the single event effect sensitive area of the device by using the heavy ion microbeam.
5a) And fixing and connecting the PCB irradiation plate to a control platform of the heavy ion microbeam.
Repeating the operation in step 4a) except that this step fixes the PCB irradiation plate to the control platform of the heavy ion microbeam.
5b) Focusing the device, setting the origin position and inputting the coordinates of the scanning area
Firstly, repeating the step 4b) on the heavy ion microbeam control platform, wherein the position O selected in the step 4b) is taken as an origin, and then setting the coordinates of the SEE sensitive areas preliminarily determined in the step 4d) as scanning areas respectively.
5c) Setting beam parameters and scanning parameters of heavy ion microbeam
86Kr25+ ions with an ion energy of 473MeV were selected, which had an LET value of 37.6MeV/(mg/cm2) and a penetration depth of 57.5 μm in the Si material. The penetration depth is enough to allow 86Kr25+ ions to pass through the metal wiring layer of the memory to reach the sensitive area of the chip, and the single event effect LET threshold of the memory is higher than 37.6MeV/(mg/cm2), so that the single event effect of the memory can be triggered.
Considering the factors of single event effect irradiation experiment standard, chip layout area and the like, the beam spot size of the heavy ion microbeam is set to be 20 multiplied by 20 mu m2, and the scanning step length is 20 mu m. The scanning speed of the heavy ion microbeam was 20 μm/s and the ion fluence rate was 40ions/s, i.e., the heavy ions scanned a 20X 20 μm2 area per second, each area being incident with 40 Kr ions. To match the scan speed of the heavy ion microbeam, the test frequency of the memory test system is set to perform two read operations per second. Therefore, the test system can read out data from the device twice in the incident time of a heavy ion microbeam, and can judge whether the heavy ion microbeam affects the data in the memory or not by comparing the data twice.
5d) And (4) scanning the heavy ion micro-beam to further position the SEE sensitive area of the device.
Firstly, the test system carries out read-back test on the memory, then the heavy ion microbeam is opened, scanning is carried out from the first area selected in the step 3d), and the X-Y control platform of the heavy ion microbeam is stepped according to the step length and the speed selected in the step 4 c). When the single event effect occurs in the memory, the FPGA device can automatically distinguish whether the effect is the single event upset effect or the single event transient effect, and transmits the effect to a coordinate recording system through a feedback signal, and the coordinate recording system records the incident coordinate of the heavy ions at the moment. And after the scanning of the first area is finished, continuing to scan the second area until the scanning of a plurality of areas is finished. As mentioned in the background, the single event effect of this step is caused by heavy ions, which results in higher accuracy and stronger persuasion, compared to the SEE sensitive region located in step 4 d).
Step 6: the test results are collated and plotted
After the accurate positioning of the heavy ion microbeam is finished, by combining the single event effect information recorded by the test system and the single event effect coordinate position recorded by the coordinate recording system, the SEE sensitive position and the sensitivity degree in each specific sensitive region can be obtained, as shown in (a) of fig. 7, the SEE sensitive position and the sensitivity degree in the first sensitive region in step 3d) are shown schematically, the Z axis is the number of memory cells influenced by the single event effect, cyan represents the single event upset effect, and red represents the single event transient effect.
After the two SEE sensitive positions are respectively corresponding to the layout of the whole sensitive area, the SEE sensitive positions in the whole chip can be obtained, and as shown in the diagram (b) in FIG. 7, a plurality of circuit areas sensitive to the single event effect can be obtained. Subsequent analysis of the design of these circuits may provide more valuable and targeted reinforcement.
Fig. 3 is a diagram of a structure of a device corresponding to the embodiment of fig. 2.
As shown in fig. 3, a device for testing single event effect of a memory includes:
a scanning module 03, configured to perform periodic heavy ion microbeam scanning on all sub-regions of the single event effect sensitive region of the memory one by using the test system according to any one of claims 1 to 4;
a reading module 04, configured to read all data in the memory through the FPGA device, and record the number of error data in the read data in the ith scanning cycle as NiI is a natural number greater than or equal to 1;
an output module 05 for counting NiGreater than Ni-1Then, a first feedback circuit of the FPGA device outputs a first feedback signal;
the output module 05 is also used for counting NiLess than Ni-1And then, a second feedback circuit of the FPGA device outputs a second feedback signal.
In some embodiments, the apparatus further comprises:
the sensitive region determining module 01 is used for determining a single event effect sensitive region on the surface of a chip layout of the memory by laser scanning;
and the sub-region dividing module 02 is used for averagely dividing the single event effect sensitive region into a plurality of sub-regions according to the vertical and horizontal coordinates.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
It will be apparent to those skilled in the art that embodiments of the present application may be provided as a method or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
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