CN112151641A - Method for preparing N-type battery by using insulating edge protection layer - Google Patents

Abstract

The invention discloses a method for preparing an N-type battery by using an insulating edge protection layer. The method comprises the following specific steps: (1) selecting an N-type monocrystalline silicon wafer, cleaning and texturing, diffusing boron and removing BSG; (2) uniformly coating a dielectric layer film on the edge of the silicon wafer by using a roller transmission device; (3) micro-sintering the dielectric layer and the silicon wafer by using high temperature before phosphorus diffusion is carried out by using diffusion or before polycrystalline silicon is deposited by LPCVD; (4) degumming, namely stripping the insulated dielectric layer and the phosphorus deposited on the dielectric layer by using HF; (5) after the RCA PSG layer or the polysilicon layer is removed, AlOx and SiNx passivation is carried out on the front surface, SiNX passivation is carried out on the back surface, silver paste is printed on the front surface, and sintering is carried out. The method can effectively solve the problem of electric leakage at the edge of the N-type silicon wafer.

Description

A method for preparing N-type battery using insulating edge protection layer

technical field

The invention provides a method for solving edge leakage in the process of preparing an N-type battery by using insulating materials, and the invention relates to the technical field of solar cells.

Background technique

With the rapid development of the photovoltaic industry, the market urgently needs an industrialized preparation technology of solar cells with simple process flow and high photoelectric conversion efficiency to reduce the cost of photovoltaic power generation, so that the cost of photovoltaic power generation can reach the same price as or lower than the price of commercial power. The goal. The P-type PERC has only one diffusion process of phosphorus diffusion, so when removing phosphorus wrapping and leakage, the phosphorus washing step can be completed at the same time. However, with the gradual reduction of the cost of N-type silicon wafers, the efficiency of N-type silicon wafers such as Topcon cells reaches 23.5%, and the N-type market is gradually developed by the market. However, the N-type needs to prepare a PN junction and a back electric field during the production process, that is, both boron expansion and phosphorus expansion or phosphorus injection are required. and Topcon's puzzle. Among them, phosphorus implantation uses ion implantation to inject phosphorus into the silicon wafer. Ion implantation can effectively avoid the problems of surrounding plating and edge leakage, but the ion implantation equipment is expensive, the maintenance cost is high, and the production cost is high, which is not conducive to mass production; and The traditional insulating layer has relatively large damage to the cell, and the slice insulation will lose the cell, and there is a damaged layer in the edge splinter. The use of low-cost phosphorus diffusion must solve the problems of phosphorus wrapping and phosphorus edge leakage. One of the methods is to use laser for insulation, but laser insulation damages the silicon wafer greatly, and is prone to production cracks, cracks and other damages. There is a damaged layer in the split, which also has a great influence on the efficiency of the cell.

Among them, CN201010228706.5 is a manufacturing process of a solar cell with a mask blocking edge diffusion. Before the diffusion step, a mask for blocking diffusion is covered around the edge of the silicon wafer, and the mask for blocking diffusion is a silicon dioxide film or a silicon nitride film. . The PECVD and furnace tube growth SiNx or SiO ₂ are used for insulation, and it is not stated whether it is after boron expansion or phosphorus expansion. And _SiO2 wrapping problem, and the SiNx or SiO2 insulating layer is not removed, there is a risk of leakage around the edge of phosphorus wrapping, still can not solve the risk of PECVD tube deposition SiNx and SiO2 wrapping problem.

Therefore, how to solve the problem of edge wrapping and edge leakage caused by the diffusion of boron and phosphorus is a major problem that plagues N-type silicon wafers (non-heterojunction cells). The edge insulation treatment method not only has extremely low production cost, but also facilitates subsequent removal, and effectively solves problems such as edge short circuits.

SUMMARY OF THE INVENTION

In the present invention, in the current preparation process of N-type PERT and Topcon, it is difficult to solve the problem of leakage around the edge during the process of boron expansion and phosphorus expansion or phosphorus ion implantation, which ultimately affects the overall efficiency of the cell. In the present invention, the dielectric layer film prepared by using glass powder is evenly coated on the edge after phosphorus washing, and then advanced by high temperature diffusion to protect the edge, isolate the edge, and then use HF to peel off the edge of the cell. The protection effect will not have adverse effects on the cells, and can effectively solve problems such as edge short circuits and improve the photoelectric efficiency of the cells.

The technical scheme adopted in the present invention is as follows:

(1) Select N-type single crystal silicon wafers, and go through conventional processes for cleaning, texturing, boron diffusion, and BSG removal;

As a preference: the silicon wafer after surface texturing treatment is placed in the furnace tube for boron diffusion. The boron source used can be either liquid BBr ₃ or gaseous BCl ₃ , the diffusion temperature is 800-1200°C, and the diffusion time is 1 ~3h;

BSG removal: Place the boron-diffused silicon wafer into a BSG removal device for back-throwing and BSG-removing treatment. The solution used for back-throwing is HCl/HNO ₃ or NH ₃ H ₂ O/H ₂ O ₂ or KOH/additive One of the combinations is back cast, and 3% to 30% HF is used to remove the surface BSG layer for BSG removal.

(2) Using the roller transfer device, evenly apply the dielectric layer film on the side edge of the silicon wafer (the edge of the silicon wafer here only refers to the side of the edge, excluding the bottom)

Using the roller transmission device, the dielectric layer film is evenly spread on the edge of the silicon wafer. The equipment used can evenly spread the dielectric layer to a thickness of 0.1-5mm. The material of the dielectric layer is mainly glass powder and additives. . The glass powder contains 80-100% by mass of glass powder and 0-20% by mass of ceramic powder, wherein: the glass powder is composed of the following components, calculated by mass percentage, 3-25% BaO, 25-60% ZnO, 15-35% B ₂ O ₃ , 3-30% SiO ₂ , 0.2-6% Li ₂ O and 0-1.5% Al ₂ O ₃ ; the ceramic powder is selected from alumina, zirconia, zircon, titania, At least one of cordierite, mullite, silica, willemite, tin oxide, and zinc oxide.

The additive consists of an organic solvent and an organic binder. Organic solvents are generally alcohols, esters, ketones, such as one of terpineol, tributyl citrate, acetate, etc. The organic binders are generally polymer resins, such as ethyl cellulose, benzene, etc. One of ethylene, nitrocellulose, etc.

Preferably, the material of the dielectric layer is obtained by mixing 20% glass frit, 35% ethyl cellulose and 45% terpineol by mass percentage.

(3) Micro-sintering the dielectric layer and the silicon wafer at high temperature before phosphorus diffusion by diffusion or LPCVD deposition of polysilicon;

Before phosphorus expansion or preparation of polysilicon, micro-sintering is performed by using a furnace tube, wherein the process N ₂ is 100-5000 sccm, the temperature is set at 500-900° C., and the time is set at 1-30 minutes.

The process is superimposed on the phosphorus expansion or LPCVD deposition polycrystalline process, the phosphorus expansion temperature is set at 800-880°C, and the time is set between 60-150min. The temperature for LPCVD deposition of polysilicon is set at 500-800° C., and the time is set at 60-120 min.

(4) Degumming, using HF to peel off the insulating dielectric layer and the phosphorus deposited on the dielectric layer together;

The insulating dielectric layer and the phosphorus deposited on the dielectric layer are peeled off together with HF, wherein the concentration of HF is set to be 1% to 15% by mass, and the time is set to be 30s to 600s.

(5) After the RCA is removed from the PSG layer or the polysilicon layer, AlOx and SiNx passivation is performed on the front side, and SiNX passivation is performed on the back side;

(6) The silver paste is printed on the front and then sintered. This method can effectively solve the edge leakage problem of the N-type silicon wafer.

Compared with the prior art, the present invention has the following excellent effects: the present invention uses glass frit as the material of the dielectric layer to prepare edge insulation before phosphorus diffusion is performed on the silicon wafer or before polysilicon is deposited by LPCVD, so that the silicon wafer can be diffused during the diffusion process. During the process, PN junctions are not formed around the edges, and the PN junctions on the front and back of the silicon wafer are isolated, so there is no need to perform edge etching on the silicon wafer. Corrosion causes damage to the cell and loss of efficiency, and improves the photoelectric efficiency of the cell, and the edge insulation can be stripped of the insulating dielectric layer and the phosphorus deposited on the dielectric layer with HF. The operation is simple and suitable for industrial production.

Description of drawings

FIG. 1 is a flow chart comparison of the N-type battery prepared by the traditional method and the N-type battery prepared by the method of the present invention.

FIG. 2 is a flow chart of the steps of preparing an N-type battery according to the present invention.

FIG. 3 is a structural diagram of an N-type battery prepared by the present invention.

Detailed ways

In order to better understand the present invention, the technical solutions of the present invention are described in detail below with specific examples, but the invention is not limited thereto.

N-type single crystal silicon wafers are prepared by traditional methods. The preparation process is cleaning and texturing, front-side boron diffusion to form BSG, BSG removal, phosphorus diffusion to form PSG layer, PSG removal, ALD removal, positive plating, and back plating. , printing to obtain an N-type single crystal silicon wafer.

As shown in FIG. 1, the present invention uses high temperature to micro-sinter the dielectric layer and the edge of the silicon wafer before phosphorus diffusion by diffusion or LPCVD deposition of polysilicon; phosphorus diffusion is performed after micro-sintering, and the edge protection layer is cleaned after diffusion. remove.

Example 1

Wherein as preferably, the concrete operating condition of the high-efficiency N-type TOPCon battery of embodiment 1 is:

(1) Cleaning and texturing treatment: N-type crystalline silicon substrate is selected, metal ions are removed for N-type silicon wafers, and surface texturing is performed;

(2) Front-side boron diffusion: place the silicon wafer processed in step (1) in a furnace tube for boron diffusion. The boron source used can be either liquid BBr ₃ or gaseous BCl ₃ , and the diffusion temperature is between 800 and 1200° C. , the diffusion time is 2h;

(3) BSG removal: place the silicon wafer after step (2) in the BSG removal equipment, and perform back throwing and BSG removal treatment, wherein the solution used for back throwing is HCl/HNO ₃ or NH ₃ ﹒ One of the combinations of H ₂ O/H ₂ O ₂ or KOH/additives was back-polished, and 15% HF was used to remove the surface BSG layer for BSG removal.

(4) Using the roller transmission device, evenly apply the dielectric film on the edge of the silicon wafer:

Using the roller transmission device, the dielectric layer film is evenly spread on the edge of the silicon wafer. The equipment used can evenly spread the dielectric layer to a thickness of 0.1mm. The material of the dielectric layer is based on mass percentage, from 20% It is obtained by mixing glass powder, 35% ethyl cellulose and 45% terpineol. The glass powder contains 80% by mass of glass powder and 20% by mass of ceramic powder, wherein: the glass powder is composed of the following components, calculated by mass percentage, 25% BaO, 25% ZnO, 15% B ₂ O ₃ , 29% SiO ₂ , 5% Li ₂ O and 1.0% Al ₂ O ₃ ; the ceramic powder is mixed with alumina and titania in a mass ratio of 7:3.

(5) Micro-sintering the dielectric layer and the silicon wafer at high temperature before phosphorus diffusion by diffusion or LPCVD deposition of polysilicon;

The dielectric layer and the silicon wafer are micro-sintered at high temperature prior to phosphorus diffusion by diffusion or prior to LPCVD deposition of polysilicon. Before phosphorus expansion or preparation of polysilicon, micro-sintering is performed by using a furnace tube, wherein the process is N ₂ : 4000sccm, the temperature is set to 800°C, and the time is set to 25min. This process is superimposed on the phosphorus expansion or LPCVD deposition polycrystalline process, the phosphorus expansion temperature is set at 800-880°C, and the time is set between 100min. The temperature for LPCVD deposition of polysilicon was set at 600° C., and the time was set between 100 min.

(6) Degumming, using HF to peel off the insulating dielectric layer and the phosphorus deposited on the dielectric layer together;

The insulating dielectric layer and the phosphorus deposited on the dielectric layer are peeled off together with HF, wherein the concentration of HF is set to 10% by mass, and the time is set to 100s.

(7) After the RCA is removed from the PSG layer or the polysilicon layer, AlOx and SiNx passivation is performed on the front side, and SiNX passivation is performed on the back side;

(8) Sintering is carried out after printing the silver paste on the front side.

The method can effectively solve the edge leakage problem of the N-type silicon wafer.

The structure of the N-type TOPCon battery is finally obtained as shown in Figure 1.

Example 2 (where the unrestricted conditions are the same as in Example 1)

(1) Select N-type single crystal silicon wafer, after cleaning and texturing, boron diffusion, and phosphorus washing;

(2) Using the roller transmission device, evenly smear the dielectric layer film on the edge of the silicon wafer;

Using the roller transmission device, the dielectric layer film is evenly spread on the edge of the silicon wafer. The equipment used can evenly spread the dielectric layer to a thickness of 3mm. The material of the dielectric layer is mainly glass powder and additives. The glass powder contains 90% by mass of glass powder and 10% by mass of ceramic powder, wherein: the glass powder is composed of the following components, calculated by mass percentage, 10% BaO, 25% ZnO, 30% B ₂ O ₃ , 30% %SiO ₂ , 3.5% Li ₂ O and 1.5% Al ₂ O ₃ ; the ceramic powder is obtained by mixing alumina, zirconia, tin oxide and zinc oxide in an equal mass ratio.

(3) Micro-sintering the dielectric layer and the silicon wafer at high temperature before phosphorus diffusion by diffusion or LPCVD deposition of polysilicon;

The dielectric layer and the silicon wafer are micro-sintered at high temperature prior to phosphorus diffusion by diffusion or prior to LPCVD deposition of polysilicon. Wherein, before phosphorus expansion or preparation of polysilicon, micro-sintering is performed by using a furnace tube, wherein the process is N ₂ : 1000 sccm, the temperature is set to 900° C., and the time is set to 5 minutes.

(4) Degumming, using HF to peel off the insulating dielectric layer and the phosphorus deposited on the dielectric layer together;

The insulating dielectric layer and the phosphorus deposited on the dielectric layer are peeled off together with HF, wherein the concentration of HF is set to 10% by mass, and the time is set to 100s.

(5) After the RCA is removed from the PSG layer or the polysilicon layer, AlOx and SiNx passivation is performed on the front side, and SiNX passivation is performed on the back side;

(6) Sintering is carried out after printing silver paste on the front side.

Comparative Example 1

The difference between Comparative Example 1 and Example 1 is that the protection of the dielectric layer film in steps (3) and (4) is omitted, other operations and structures are identical to those of Example 1, and an N-type battery is prepared.

The electrical properties of the N-type batteries prepared in Example 1 and Comparative Example 1 were compared, and the comparison results were as follows:

Taking the above ideal embodiments according to the present invention as inspiration, and through the above description, relevant personnel can make various changes and modifications without departing from the technical idea of the present invention. The technical scope of the present invention is not limited to the contents in the specification, and the technical scope must be determined according to the scope of the claims.

Claims (5)

1. A method for preparing an N-type battery utilizing an insulating edge protective layer, comprising the following steps: (1) Select N-type single crystal silicon wafer, after cleaning, texturing, boron diffusion, and BSG removal; (2) Using the roller transmission device, evenly smear the dielectric layer film on the edge of the silicon wafer; (3) Micro-sintering the dielectric layer and the silicon wafer at high temperature before phosphorus diffusion by diffusion or LPCVD deposition of polysilicon; (4) Degumming, using HF to peel off the insulating dielectric layer and the phosphorus deposited on the dielectric layer together; (5) After the RCA is removed from the PSG layer or the polysilicon layer, AlOx and SiNx passivation is performed on the front side, and SiNX passivation is performed on the back side; (6) Sintering is carried out after printing silver paste on the front side. 2. The method for preparing an N-type battery using insulating edge protection according to claim 1, wherein the step (2) utilizes a roller conveying device to evenly spread the dielectric layer film on the edge of the silicon wafer, which The equipment used can evenly coat the dielectric layer with a thickness of 0.1-5mm, and the material of the dielectric layer is mainly glass powder and additives. 3. The method according to claim 2, wherein the glass powder contains 80-100% by mass of glass powder and 0-20% by mass of ceramic powder, wherein: glass powder It is composed of the following components, calculated by mass percentage, 3-25% BaO, 25-60% ZnO, 15-35% B ₂ O ₃ , 3-30% SiO ₂ , 0.2-6% Li ₂ O and 0- 1.5% Al ₂ O ₃ ; the ceramic powder is at least one selected from the group consisting of alumina, zirconia, zircon, titania, cordierite, mullite, silica, willemite, tin oxide and zinc oxide. 4. The method for preparing an N-type battery by utilizing insulating edge protection according to claim 1, characterized in that: (3) utilizing diffusion to perform phosphorus diffusion or LPCVD deposition of polysilicon, utilize high temperature to separate the dielectric layer and the silicon wafer Micro-sintering is performed; wherein, before phosphorus diffusion or polysilicon preparation, micro-sintering is performed by using a furnace tube, wherein the process N ₂ is 100-5000 sccm, the temperature is set at 500-900° C., and the time is set at 1-30 min. 5. The method for preparing an N-type battery using insulating edge protection according to claim 1, wherein the (4) degumming is performed by using HF to perform the insulating dielectric layer and the phosphorus deposited on the dielectric layer together. For peeling, the concentration of HF is set to be 1% to 15% by mass, and the time is set to be 30s to 600s.

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