CN112151471A - A kind of multi-chip integrated packaging structure and preparation method thereof - Google Patents

Abstract

The invention discloses a multi-core particle integrated packaging structure, comprising a plurality of core particles plastic-encapsulated by a plastic sealing layer, a core-particle interconnecting structure electrically connected with the plastic-encapsulated core-particle contacts, and being arranged in the core-particle interconnecting structure to complete the core-particle contacting The wiring lead-out structure provided on the other side of the point electrical connection and the solder balls arranged at the corresponding pads of the wiring lead-out structure, the contacts of the core particles include a first contact that needs to be interconnected with each other and a lead for direct lead-out. For the second contacts, on the core particle interconnection structure, a communication groove between the first contacts required to be interconnected between the core particles and a lead-out groove capable of leading out the second contact are formed, and the communication groove and the lead-out groove are filled with metal seeds. The invention also discloses a preparation method of the package structure. By adopting the design scheme of the present invention, the package structure is simpler, and the shortcomings of the traditional fan-out package that the RDL wiring process accuracy is insufficient and the ultra-precise interconnection cannot be performed are made up.

Description

A kind of multi-chip integrated packaging structure and preparation method thereof

technical field

The invention relates to the technical field of semiconductor packaging, in particular to a multi-chip integrated packaging structure and a preparation method thereof.

Background technique

With the continuous development of the chip's front-end manufacturing technology, the technology node has been updated to 7nm/5nm or even smaller, gradually approaching the physical limit, the chip's front-end manufacturing process has become extremely complex, its manufacturing yield has gradually decreased, and manufacturing costs have risen sharply. In order to further optimize the chip design and front-end manufacturing process, and effectively control the overall cost, the industry has gradually begun to transform the original single-chip SoC mode into a chiplet mode, that is, a "small chip" mode, which decomposes the original single chip into multiple Each "chiplet" is designed, and the appropriate process node is flexibly selected according to the properties of each chip for front-end manufacturing, and then these manufactured "chiplets" are integrated and packaged to build a similar Functional modules on a single chip. For this chiplet-based method, how to integrate and package multiple different kinds of "small chips" together to achieve high-speed and high-bandwidth interconnection, and together form a powerful system with relatively small volume power consumption, which becomes the A major challenge in the field of semiconductor chip packaging.

At present, for high-density multi-chip integrated packaging, the industry often uses through-silicon (TSV), silicon interposer (Siinterposer) and other methods to lead out and effectively interconnect the ultra-fine pins of the chip to form a system. The high cost of this technology limits its scope of application. Fan-out packaging technology provides a good platform for realizing multi-chip integrated packaging by using recon wafer and RDL rewiring, but the process accuracy of RDL rewiring in fan-out packaging is limited. (The minimum line width is usually 2-5um or more), and it is impossible to perform low-latency, high-density interconnection of precision signal pins between small chips to achieve high-speed and high-bandwidth purposes.

SUMMARY OF THE INVENTION

Purpose of the invention: The purpose of the present invention is to solve the problem of unreasonable wiring lead-out structure based on the existing core particles.

Technical scheme: in order to solve the above-mentioned problems, the present invention provides the following technical scheme:

A multi-core particle integrated packaging structure includes a plurality of core particles that are plastic-encapsulated by a plastic sealing layer, a core-particle interconnection structure that is electrically connected to the plastic-encapsulated core-particle contacts, and a core-particle interconnection structure that is arranged in the core-particle interconnection structure to complete the electrical connection of the core particle contacts. The wiring lead-out structure provided on the other side and the solder balls arranged at the corresponding pads of the wiring lead-out structure, the contacts of the core particles include a first contact that needs to be interconnected with each other and a second contact for direct lead-out and forming a communication groove between the first contacts required to be interconnected between the core particles and a lead-out groove capable of leading out the second contact on the core particle interconnection structure, and the communication groove and the lead-out groove are filled with metal seeds.

The contacts of the chip are divided into two categories, one is the first contact that needs to be interconnected, it is the bumps at those signal pins to be interconnected with other chips, located at the edge of the chip (with other chips). The core particles are adjacent); the other type is the second contact that needs to be led out directly, which are the remaining bumps of the quotation marks pins on the core particles that need to be led out.

Metal seeds are usually Ti, Cu and other metals.

Further, the core-particle interconnection structure includes at least two dielectric layers, the first dielectric layer forms a plurality of first grooves that can lead out the first contacts and the second contacts, and the second dielectric layer forms The second groove that communicates with the first contacts that need to be interconnected between the particles and the third groove that are directly drawn out. The first groove and the second groove corresponding to the first contacts that need to be interconnected form a communication groove, which is directly drawn out. The first groove and the third groove corresponding to the second contact form a lead-out groove.

The chip interconnection structure is an integrated structure of through holes and interconnections. The process steps are simple, and sub-micron interconnect lines (line widths of 0.4-1um or even smaller) can be fabricated to connect the first contacts on the chip that need to be interconnected. Make electrical connections for high-speed, high-bandwidth interconnects between cores.

Further, the wiring lead-out structure includes at least one redistribution layer, and the redistribution layer includes a third dielectric layer and a fourth recess formed on the third dielectric layer and corresponding to the metal contact formed after filling the lead-out groove with the metal seed. grooves, and filling the fourth groove with metal seeds to form metal pads on the outer surface of the third dielectric layer.

Further, the diameter and spacing of the first contacts are both less than 30 μm, and the diameter and spacing of the second contacts are greater than 50 μm.

Compared with the second contact, the first contact has the same height and their upper surfaces are flush, but the first contact has a smaller diameter and spacing (<30um or less), so that the core particle More interconnect pins can be placed between them to achieve larger-scale signal interconnection and improve data interaction speed and capacity. The diameter and spacing of the second contacts are not so precise, usually about 50-90um or even larger.

Further, the first dielectric layer and the second dielectric layer are both photosensitive polyimide-based organic resins, and the third dielectric layer is an organic photosensitive dielectric layer.

A preparation method of a multi-chip integrated packaging structure, comprising the following steps:

1) Prepare a temporary slide, and adhere the temporary bonding adhesive layer on the surface of the temporary slide;

The material of the temporary slide can be metal or silicon wafer, glass, quartz and other materials with moderate rigidity.

2) Mount the core particles on the surface of the temporary bonding adhesive layer, and place the devices with metal contacts on the core particles facing up;

3) Then plastic-encapsulate the mounted core particles (or other components) to form a plastic-encapsulated layer, and grind the upper surface of the plastic-encapsulated layer to expose the first and second contacts of the core particles;

4) Making a core particle interconnection structure on the plastic encapsulation layer;

5) For the second contacts that need to be drawn out except for the first contacts that need to be interconnected on the core particles, continue to make a wiring lead-out structure that can lead them out;

6) Install the solder balls on the metal pads on the finished wiring lead-out structure to complete the soldering of the solder balls;

7) The temporary carrier is removed by means of thermomechanical debonding or laser debonding, and the package body having completed the packaging process is cut.

Further, in the step 4), making the core particle interconnection structure specifically includes the following steps:

4. a) Coating the first dielectric layer on the surface of the plastic encapsulation layer;

4.b) exposing and developing the first dielectric layer first, forming a first groove at the position of the first dielectric layer corresponding to the contact on the core particle;

4.c) Continue on the first dielectric layer, coat the second dielectric layer with the same method and carry out exposure and development, and form a second recess for forming interconnection between core particles on the first groove. a groove and a third groove for lead-out;

4.d) then deposit a thin layer of metal by plasma vapor deposition;

4.e) then use the method of electrochemical plating to deposit metal seed on the thin layer metal, fill the first groove, the second groove and the third groove;

The thin layer metal is usually Cu or other metallic materials.

4.f) Grinding the upper surface of the metal seed deposition to planarize the surface and to expose the upper surface of the second dielectric layer in the regions of the second groove and the third groove.

Further, in the step 5), making a wiring lead-out structure specifically includes the following steps:

5. a) on the upper surface of the second dielectric layer, coating a third dielectric layer;

5.b) The photolithography process of exposing and developing is performed at the position corresponding to the metal seed on the second dielectric layer that needs to be drawn out to form a fourth groove, so that the surface of the core particle interconnection structure under the third dielectric layer needs to be The extracted metal seeds are exposed;

5.c) depositing metal seeds in the fourth groove;

5.d) Coating a layer of photoresist, using exposure and developing processes to open grooves on the photoresist to expose the metal seeds that need to be drawn out;

5.e) Continue the metal electroplating process, and metal seed filling will be formed in the photoresist grooved area;

5.f) Remove the photoresist and the metal seeds at the bottom of the photoresist by wet etching, and form a rewiring layer.

Further, the process steps 5.a to 5.f are repeated to manufacture a wiring lead-out structure including at least two rewiring layers.

Beneficial effect: the present invention compares with prior art:

1) The process structure of high-density, high-speed, high-bandwidth interconnection and integrated packaging between chips with ultra-fine pin structure is realized;

2) For integrated packaging that requires interconnection between ultra-high-density chips, there is no need to use high-cost complex structures such as through-silicon vias (TSVs) and silicon interposers;

3) This packaging method simplifies the signal interconnection and extraction process of the chip, and reduces the volume of the integrated package while realizing high-speed and high-bandwidth interconnection.

Description of drawings

Fig. 1 is the product structure schematic diagram of the present invention;

Fig. 2 is the structural representation after the completion of step 1 of the present invention;

Fig. 3 is the structural representation after the completion of step 2 of the present invention;

Fig. 4 is the structural representation after the completion of step 3 of the present invention;

Fig. 5 is the structural representation after the completion of step 4.a of the present invention;

Fig. 6 is the structural representation after the completion of step 4.b of the present invention;

Fig. 7 is the structural representation after the completion of step 4.c of the present invention;

Fig. 8 is the structural representation after the completion of step 4.d of the present invention;

Fig. 9 is the structural representation after the completion of step 4.e of the present invention;

Fig. 10 is the structural representation after the completion of step 4.f of the present invention;

Figure 11 is a schematic plan view of the present invention after step 4.f is completed;

Fig. 12 is the structural representation after the completion of step 5.a of the present invention;

Fig. 13 is the structural representation after the completion of step 5.b of the present invention;

Fig. 14 is the structural representation after the completion of step 5.c of the present invention;

Fig. 15 is the structural representation after the completion of step 5.d of the present invention;

Fig. 16 is the structural representation after the completion of step 5.e of the present invention;

Fig. 17 is the structural representation after the completion of step 5.f of the present invention;

18 is a schematic structural diagram of the present invention after repeating steps 5.a to 5.f again;

Fig. 19 is the structural representation after the completion of step 6 of the present invention;

20 is a schematic structural diagram of Embodiment 3 of the present invention;

21 is a schematic structural diagram of a conductive column in Embodiment 3 of the present invention;

Detailed ways

The present invention will be further described below with reference to the accompanying drawings and embodiments.

Example 1

As shown in FIG. 1 to FIG. 21 , a multi-core integrated package structure includes a plurality of cores 3 encapsulated by a plastic encapsulation layer 4 , and a core interconnection structure electrically connected to the contacts of the encapsulated cores 3 . The core-die interconnecting structure completes the wiring lead-out structure provided on the other side of the electrical connection of the core-die contacts and the solder balls 15 arranged at the corresponding pads of the wiring-lead-out structure. The contacts of the core die 3 include the contacts that need to be interconnected The first contact 301 and the second contact 302 for direct lead-out are formed on the interconnect structure of the die 3 to form a communication groove between the first contacts 301 required to be interconnected between the die, and the second contact 302 can be led out The lead-out groove, the communication groove and the lead-out groove are filled with metal seeds 8.

The contacts of the chip are divided into two categories, one is the first contact that needs to be interconnected, it is the bumps at those signal pins to be interconnected with other chips, located at the edge of the chip (with other chips). The core particles are adjacent); the other type is the second contact that needs to be led out directly, which are the remaining bumps of the quotation marks pins on the core particles that need to be led out.

Metal seeds are usually Ti, Cu and other metals.

The core-die interconnection structure includes at least two dielectric layers. The first dielectric layer 5 forms a number of first grooves 200 that can lead out the first contacts 301 and the second contacts 302, and the second dielectric layer 6 forms the cores. The second groove 201 and the directly drawn third groove 202 for the first contacts 301 that need to be interconnected between the particles, the first groove 200 and the second groove 201 corresponding to the first contacts 301 to be interconnected A communication groove is formed, and the first groove 201 and the third groove 202 corresponding to the directly drawn second contact 302 form a lead-out groove.

The chip interconnection structure is an integrated structure of through holes and interconnections. The process steps are simple, and sub-micron interconnect lines (line widths of 0.4-1um or even smaller) can be fabricated to connect the first contacts on the chip that need to be interconnected. Make electrical connections for high-speed, high-bandwidth interconnects between cores.

The wiring lead-out structure includes at least one redistribution layer, and the redistribution layer includes a third dielectric layer 9 and a fourth recess formed on the third dielectric layer 9 corresponding to the metal contact formed after filling the metal seed 8 in the lead-out groove The groove 203 is formed, and the metal seed 8 is filled in the fourth groove 203 to form a metal pad on the outer surface of the third dielectric layer 9 .

The diameter and spacing of the first contacts 301 are both less than 30 μm, and the diameter and spacing of the second contacts 302 are greater than 50 μm.

Compared with the second contact, the first contact has the same height and their upper surfaces are flush, but the first contact has a smaller diameter and spacing (<30um or less), so that the core particle More interconnect pins can be placed between them to achieve larger-scale signal interconnection and improve data interaction speed and capacity. The diameter and spacing of the second contacts are not so precise, usually about 50-90um or even larger.

The first dielectric layer 5 and the second dielectric layer 6 are both photosensitive polyimide organic resins (eg, PI, PBO), and the third dielectric layer 9 is an organic photosensitive dielectric layer.

Example 2

The first contact that needs to be interconnected does not refer to a simple one-to-one correspondence, it can be one-to-one or one-to-many, that is, one of the first contacts of a core particle and the other One of the first contacts of the core particle is connected, and this relationship may be to have one first contact or to have multiple first contacts; or one of the first contacts of a core particle and the other core particle of which a plurality of first contacts are connected.

Therefore, in this embodiment, compared with Embodiment 1, three core particles 3 are used for interconnection, and there are one-to-one correspondence, two-to-two correspondence and three-to-three correspondence among the three core particles 3 respectively.

In this embodiment, there is not only a one-to-one correspondence, but also a one-to-many situation, in which the first contact of one core particle is connected to the two first contacts of the other core particle.

Example 3

On the basis of Embodiment 1, one or more conductive column structures are added in the plastic encapsulation layer, and "16" in the figure is a conductive column structure. The specific structure of the conductive column is shown in FIG. 21 , including a copper column 162 and an insulator 161 surrounding the copper column and wrapping the copper column;

In the embodiment shown in FIG. 20 , the conductive pillar structures 16 penetrate through the upper and lower surfaces of the plastic packaging layer, and the copper pillars 162 in the conductive pillars can interconnect the signal pins of the core particles or components on the upper and lower surfaces of the plastic packaging layer, so that the On the basis of Example 1, some already packaged chips or components 17 are stacked on top of the plastic packaging layer, and the chips or components 17 are electrically connected with metal contacts 171 to the conductive pillar structure, so as to realize the connection with the existing core particles in the plastic packaging layer. The three-dimensional interconnection saves the area of the package.

Example 4

A preparation method of a multi-chip integrated packaging structure, comprising the following steps:

1) Prepare a temporary slide 1, and adhere the temporary bonding adhesive layer 2 on the surface of the temporary slide 1, as shown in Figure 2;

The material of the temporary slide can be metal or silicon wafer, glass, quartz and other materials with moderate rigidity.

2) Mount the core particles 3 on the surface of the temporary bonding adhesive layer 2, and place the devices with metal contacts on the core particles 3 facing up, as shown in Figure 3;

3) Then the mounted core particles 3 (or other components) are plastic-sealed to form a plastic-sealing layer 4, and the upper surface of the plastic-sealing layer 4 is ground to expose the first contacts 301 and the second contacts 302 of the core particles 3, As shown in Figure 4;

4) making a core particle interconnection structure on the plastic encapsulation layer 4; specifically, the following steps are included:

4.a) Coating a first dielectric layer 5 (such as PI, PBO) on the surface of the plastic encapsulation layer 4, as shown in Figure 5;

4.b) exposing and developing the first dielectric layer 5, and forming a first groove 200 at the position of the first dielectric layer 5 corresponding to the contact on the core particle, as shown in FIG. 6 ;

4.c) Continue on the first dielectric layer 5, coat the second dielectric layer 6 with the same method and carry out exposure and development, and form the interconnection between the core particles on the first groove 200. The second groove 201 and the third groove 202 for lead-out are shown in FIG. 7 ;

4.d) then deposit a thin layer of metal seed 7 by plasma vapor deposition, as shown in Figure 8;

4.e) then use the method of electrochemical plating to deposit metal 8 on the thin layer of metal seed 7 to fill the first groove 200, the second groove 201 and the third groove 202, as shown in FIG. 9;

The deposition metal is usually Cu or other metallic materials.

4.f) Grinding the upper surface of the deposited metal 8 to flatten the surface and expose the upper surface of the second dielectric layer 6 in the regions of the second groove 201 and the third groove 202 , as shown in FIG. 10 .

FIG. 11 is a top plan view after this step is completed. In the figure, 3 is a core particle, 4 is a plastic package, and the first contacts 301 between the core particles have been interconnected.

5) For the second contacts 302 that need to be drawn out except for the first contacts 301 that need to be interconnected on the die 3, continue to make a wiring lead-out structure that can lead them out; specifically, the following steps are included:

5.a) On the upper surface of the second dielectric layer 6, coat the third dielectric layer 9, as shown in Figure 12;

5.b) The photolithography process of exposing and developing is performed at the position corresponding to the required extraction of the deposited metal 8 on the second dielectric layer 6 to form the fourth groove 203, so that the core particles under the third dielectric layer 9 are formed. The deposited metal 8 that needs to be drawn out from the surface of the interconnect structure is exposed, as shown in Figure 13;

5.c) deposit a thin layer of metal seed 8 by physical vapor deposition in the fourth groove 203, as shown in Figure 14;

5.d) Coating a layer of photoresist 11, using exposure and developing process to open grooves on the photoresist to expose the metal seeds 8 that need to be drawn out, as shown in Figure 15;

5.e) Continue to carry out the metal electroplating process, and the metal seed 8 will be filled in the area where the photoresist 11 is grooved, as shown in FIG. 16 ;

5.f) The photoresist 11 and the metal seed 8 at the bottom of the photoresist are removed by wet etching to form a rewiring layer, as shown in FIG. 17 .

Repeat the process steps 5.a to 5.f to fabricate a wiring lead-out structure including at least two rewiring layers, as shown in FIG. 18 .

6) Install the solder balls 15 on the metal pads on the fabricated wiring lead-out structure to complete the soldering of the solder balls 15, as shown in Figure 19;

7) Finally, the temporary carrier sheet 1 is removed by thermomechanical debonding or laser debonding, and the package body on which the packaging process is completed is cut.

Claims (9)

1. A multi-core particle integrated packaging structure is characterized in that: it comprises several core particles plastic-encapsulated by a plastic encapsulation layer, a core particle interconnection structure electrically connected with the plastic-encapsulated core particle contacts, and is arranged on the core particle interconnection structure to complete the core particle. The wiring lead-out structure provided on the other side of the electrical connection of the chip contacts and the solder balls arranged at the corresponding pads of the wiring lead-out structure, the contacts of the core particles include a first contact that needs to be interconnected and a solder ball for direct connection. The lead-out second contact is formed on the core particle interconnection structure to form a communication groove between the first contacts that need to be interconnected between the core particles and a lead-out groove that can lead out the second contact, and the communication groove and the lead-out groove are filled with metal seed. 2 . The multi-chip integrated package structure according to claim 1 , wherein the chip interconnection structure comprises at least two dielectric layers, and the first dielectric layer forms a plurality of The first groove of the two contacts, the second dielectric layer forms the second groove that can communicate the first contacts that need to be interconnected between the core particles and the third groove that directly leads out, the first contact that needs to be interconnected The first groove and the second groove corresponding to the point form a communication groove, and the first groove and the third groove corresponding to the second contact directly drawn out form a lead-out groove. 3. The package structure of claim 1, wherein the wiring lead-out structure comprises at least one rewiring layer, the rewiring layer comprises a third dielectric layer and is formed on the third dielectric layer The fourth groove corresponding to the lead-out groove is filled with metal seeds to form metal contacts, and the fourth groove is filled with metal seeds to form metal pads on the outer surface of the third dielectric layer. 4 . The package structure of claim 1 , wherein the diameter and spacing of the first contacts are both less than 30 μm, and the diameter and spacing of the second contacts are greater than 50 μm. 5 . 5. The multi-core integrated package structure according to claim 2 or 3, wherein the first dielectric layer and the second dielectric layer are both photosensitive polyimide organic resins, and the third The dielectric layer is an organic photosensitive dielectric layer. 6. A method for preparing a multi-chip integrated packaging structure as claimed in claim 1, characterized in that: comprising the following steps: 1) Prepare a temporary slide, and adhere the temporary bonding adhesive layer on the surface of the temporary slide; 2) Mount the core particles on the surface of the temporary bonding adhesive layer, and place the devices with metal contacts on the core particles facing up; 3) Then plastic-encapsulate the mounted core particles to form a plastic-encapsulated layer, and grind the upper surface of the plastic-encapsulated layer to expose the first and second contacts of the core particles; 4) Making a core particle interconnection structure on the plastic encapsulation layer; 5) For the second contacts that need to be drawn out except for the first contacts that need to be interconnected on the core particles, continue to make a wiring lead-out structure that can lead them out; 6) Install the solder balls on the metal pads on the finished wiring lead-out structure to complete the soldering of the solder balls; 7) The temporary carrier is removed by means of thermomechanical debonding or laser debonding, and the package body having completed the packaging process is cut. 7 . The method for preparing a multi-chip integrated package structure according to claim 6 , wherein: in the step 4), the fabrication of the chip interconnect structure specifically includes the following steps: 8 . 4. a) Coating the first dielectric layer on the surface of the plastic encapsulation layer; 4.b) exposing and developing the first dielectric layer first, forming a first groove at the position of the first dielectric layer corresponding to the contact on the core particle; 4.c) Continue on the first dielectric layer, coat the second dielectric layer with the same method and perform exposure and development, and form a second recess for forming interconnection between the core particles on the first groove. a groove and a third groove for lead-out; 4.d) then deposit a thin layer of metal by plasma vapor deposition; 4.e) then use the method of electrochemical plating to deposit metal seed on the thin layer metal, fill the first groove, the second groove and the third groove; 4.f) Grinding the top surface of the metal seed deposition to planarize the surface and to expose the top surfaces of the second dielectric layer in the second groove and third groove regions. 8 . The method for preparing a multi-chip integrated package structure according to claim 6 , wherein: in the step 5), making a wiring lead-out structure specifically includes the following steps: 9 . 5. a) on the upper surface of the second dielectric layer, coating a third dielectric layer; 5.b) The photolithography process of exposing and developing is performed at the position corresponding to the required extraction of the metal seeds on the second dielectric layer to form a fourth groove, so that the surface of the core particle interconnection structure under the third dielectric layer needs to be The extracted metal seeds are exposed; 5.c) depositing metal seeds in the fourth groove; 5.d) Coating a layer of photoresist, using exposure and developing processes to open grooves on the photoresist to expose the metal seeds that need to be drawn out; 5.e) Continue the metal electroplating process, and metal seed filling will be formed in the photoresist grooved area; 5.f) Remove the photoresist and the metal seeds at the bottom of the photoresist by wet etching, and form a rewiring layer. 9 . The method for preparing a multi-chip integrated package structure according to claim 8 , wherein the process steps 5.a to 5.f are repeated to produce a wiring lead-out structure comprising at least two rewiring layers. 10 . .

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