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CN112151398B - 一种芯片封装方法 - Google Patents

一种芯片封装方法 Download PDF

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Publication number
CN112151398B
CN112151398B CN201910560967.8A CN201910560967A CN112151398B CN 112151398 B CN112151398 B CN 112151398B CN 201910560967 A CN201910560967 A CN 201910560967A CN 112151398 B CN112151398 B CN 112151398B
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CN
China
Prior art keywords
chip packaging
conductive bump
chip
bump structure
laser annealing
Prior art date
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Application number
CN201910560967.8A
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English (en)
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CN112151398A (zh
Inventor
张为国
张俊
唐世弋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Xinshang Microelectronics Technology Co ltd
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Shanghai Micro Electronics Equipment Co Ltd
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Application filed by Shanghai Micro Electronics Equipment Co Ltd filed Critical Shanghai Micro Electronics Equipment Co Ltd
Priority to CN201910560967.8A priority Critical patent/CN112151398B/zh
Priority to PCT/CN2019/103036 priority patent/WO2020258493A1/zh
Publication of CN112151398A publication Critical patent/CN112151398A/zh
Application granted granted Critical
Publication of CN112151398B publication Critical patent/CN112151398B/zh
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  • Engineering & Computer Science (AREA)
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  • Manufacturing & Machinery (AREA)
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Abstract

本发明实施例公开了一种芯片封装方法。该芯片封装方法包括：提供一载板；在所述载板上形成重布线层；在所述重布线层上形成导电凸点结构；将芯片管脚与所述导电凸点结构焊接，并形成芯片封装结构；在所述导电凸点结构的所在区域施加均匀压力，同时对所述导电凸点结构的所在区域进行激光退火。本发明实施例解决了现有技术中重布线层容易发生翘曲，影响芯片封装结构中电气结构的位置，导致芯片质量不良的问题，可以通过激光退火和施加压力的配合缓解甚至消除重布线层的翘曲，避免芯片封装结构中的电气连接不良，保证封装芯片的质量。

Description

一种芯片封装方法
技术领域
本发明实施例涉及半导体技术，尤其涉及一种芯片封装方法。
背景技术
芯片封装就是指把芯片上的电路管脚，用导线接引到外部接头处，以便与其它器件连接。封装形式是指安装半导体集成电路芯片用的外壳。它不仅起着安装、固定、密封、保护芯片及增强电热性能等方面的作用，而且还通过芯片上的接点用导线连接到封装外壳的引脚上，这些引脚又通过印刷电路板上的导线与其他器件相连接，从而实现内部芯片与外部电路的连接。
目前的封装方式通常是将芯片与一载板焊接，其中载板上设置有重布线层以及与芯片焊接的导电凸点，通过将芯片的管脚与导电凸点焊接，再由重布线层将芯片的电路管脚引出。然而，载板中的重布线层形成后，由于后续的封装步骤中存在加热过程，例如焊接时采用的回流焊工艺中，需要将焊锡融化进行焊接，此时重布线层材料在温度升降的过程中容易因热膨胀系数不同，从而在与导电凸点等材料接触的位置发生形变，即引起了重布线层翘曲的问题，导致重布线层及其他结构的位置发生变动，影响了封装芯片中导电结构的接触效果，使得封装芯片质量下降。
发明内容
本发明提供一种芯片封装方法，以消除或削弱载板上重布线层的翘曲，保证封装芯片的质量。
第一方面，本发明实施例提供了一种芯片封装方法，包括：
提供一载板；
在所述载板上形成重布线层；
在所述重布线层上形成导电凸点结构；
将芯片管脚与所述导电凸点结构焊接，并形成芯片封装结构；
在所述导电凸点结构的所在区域施加均匀压力，同时对所述导电凸点结构的所在区域进行激光退火。
可选地，所述对所述导电凸点结构的所在区域进行激光退火，包括：
采用脉冲激光对所述导电凸点结构的所在区域进行激光退火。
可选地，所述脉冲激光的波长范围为0.8-2μm。
可选地，所述脉冲激光的功率范围为0.01-30W。
可选地，所述在所述导电凸点结构的所在区域施加均匀压力，包括：
将所述芯片封装结构放置于一工作台上，且所述芯片封装结构的所述载板背离所述工作台；
在所述载板背离所述工作台的一侧放置一透明压板；
向所述透明压板施加均匀压力。
可选地，所述在所述导电凸点结构的所在区域施加均匀压力，包括：
将所述芯片封装结构放置于一工作台上，且所述芯片封装结构的所述载板背离所述工作台；
通过供气装置在所述载板背离工作台的一侧，向所述导电凸点结构的所在区域施加均匀压力。
可选地，所述工作台温度范围在20-40℃。
可选地，所述均匀压力产生的压强范围为100-1000pa。
可选地，在所述导电凸点结构的所在区域施加均匀压力，同时对所述导电凸点结构的所在区域进行激光退火之前，还包括：
将所述芯片封装结构放置于惰性气体环境中。
可选地，所述导电凸点结构包括金属导电柱，所述在所述重布线层上形成导电凸点结构，包括：
在所述重布线层上形成金属种子层图案；
在所述金属种子层图案上形成金属导电柱图案。
可选地，在所述重布线层上形成金属种子层图案之后，还包括：
对所述金属种子层图案的所在区域进行初步激光退火；
和/或，在所述金属种子层图案上形成金属导电柱图案之后，还包括：
对所述金属导电柱图案的所在区域进行初步激光退火。
可选地，所述初步激光退火的激光波长范围为1-20μm。
可选地，所述初步激光退火的激光功率范围为1-300mW。
本发明实施例提供的芯片封装方法，通过提供一载板，在载板上形成重布线层，并在重布线层上形成导电凸点结构，再将芯片管脚与导电凸点结构焊接，形成芯片封装结构，最后在导电凸点结构所在区域施加均匀压力，并进行激光退火，一方面为形成的芯片封装结构中产生翘曲的重布线层施加平整力，一方面利用激光退火处理对翘曲的重布线层进行应力释放，从而改变重布线层的形态，使翘曲的重布线层恢复平整，解决了现有技术中重布线层容易发生翘曲，影响芯片封装结构中电气结构的位置，导致芯片质量不良的问题，本发明实施例提供的芯片封装方法，可以改善重布线层的翘曲，避免芯片封装结构中的电气连接不良，保证封装芯片的质量。
附图说明
图1是本发明实施例提供的一种芯片封装方法的流程图；
图2是图1所示芯片封装方法的结构流程图；
图3是本发明实施例提供不同波长在硅内穿透深度的曲线图；
图4是本发明实施例提供的另一种芯片封装方法的流程图；
图5是图4所示芯片封装方法的结构流程图；
图6是本发明实施例提供的又一种芯片封装方法的流程图；
图7是图6所示芯片封装方法的结构流程图；
图8是本发明实施例提供的又一种芯片封装结构的流程图；
图9是本发明实施例提供的金属吸收系数及导热系数曲线。
其中，10-载板，20-重布线层，30-导电凸点结构，40-芯片，50-芯片封装结构，60-工作台，70-透明压板，80-供气装置。
具体实施方式
下面结合附图和实施例对本发明作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释本发明，而非对本发明的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与本发明相关的部分而非全部结构。
图1是本发明实施例提供的一种芯片封装方法的流程图，图2是图1所示芯片封装方法的结构流程图，参考图1和图2，该芯片封装方法包括：
S110、提供一载板10；
参考图2的步骤a)，在倒装芯片结构中，通常需要设置一载板，用以将芯片的电气面键合在载板上，通过载板进行电气线的导出，并利用载板封装和保护芯片。载板通常可选用硅片。
S120、在载板10上形成重布线层20；
参考图2的步骤b)，载板10上的电气结构包括有重布线层20，重布线层20将芯片管脚引出，用以电性连接外界的电子装置。
S130、在重布线层20上形成导电凸点结构30；
参考图2的步骤c)，重布线层20与芯片焊接时需要在重布线层20上设置用以焊接芯片管脚的导电凸点结构30，常见的导电凸点结构30包括锡铅柱、金球凸块、铜柱、导电胶凸块以及高分子凸块等型态，其中又以铜柱应用最为广泛。
S140、将芯片40管脚与导电凸点结构30焊接，并形成芯片封装结构50；
参考图2的步骤d)，导电凸点结构30与芯片40管脚的焊接过程通常可以在导电凸点结构上形成焊锡球，在将芯片40对位贴片在载板上，然后通过回流焊工艺融化焊锡球从而实现焊接过程。在焊接完芯片后，需要再在载板中填充有机材料以及介质层，以保护载板上的重布线层和芯片，最终形成芯片封装结构40。如图2所示的芯片封装结构40中，铜柱的高度通常为5～80um。
S150、在导电凸点结构30的所在区域施加均匀压力，同时对导电凸点结构30的所在区域进行激光退火。
参考图2的步骤e)，在形成芯片封装结构40的步骤中，例如导电凸点结构30的形成过程以及与芯片40管脚的焊接过程中，会引起温度的上升或需要进行加热的过程，温度上升和下降的过程会使得重布线层20和导电凸点结构30发生形变，而由于重布线层20与导电凸点结构30材质不同，热膨胀系数不同，使得重布线层20会发生翘曲现象。因此，重布线层20发生翘曲的位置多在导电凸点结构30所在的区域，针对该区域施加一均匀压力，可以平整翘曲的重布线层20，同时再利用激光退火处理该区域(图中未示意)，此处的重布线层20则会在吸收和释放激光热量时发生形变，从而释放导致翘曲的应力。并且在均匀的平整压力的作用下，可以改变重布线层20的形态至平整状态，从而削弱甚至消除重布线层20的翘曲现象。
本发明实施例提供的芯片封装方法，通过提供一载板，在载板上形成重布线层，并在重布线层上形成导电凸点结构，再将芯片管脚与导电凸点结构焊接，形成芯片封装结构，最后在导电凸点结构所在区域施加均匀压力，并进行激光退火，一方面为形成的芯片封装结构中产生翘曲的重布线层施加平整力，一方面利用激光退火处理对翘曲的重布线层进行应力释放，从而改变重布线层的形态，使翘曲的重布线层恢复平整，解决了现有技术中重布线层容易发生翘曲，影响芯片封装结构中电气结构的位置，导致芯片质量不良的问题，本发明实施例提供的芯片封装方法，可以改善重布线层的翘曲，避免芯片封装结构中的电气连接不良，保证封装芯片的质量。
考虑到芯片封装结构已初步完成芯片在结构上的封装，而通过激光退火处理导电凸点结构所在区域的重布线层，需要避免激光能量过高而破坏芯片封装结构中其他的电气结构。因此，步骤S150中，可选地，对导电凸点结构的所在区域进行激光退火，包括：采用脉冲激光对导电凸点结构的所在区域进行激光退火。其中脉冲激光相对于连续的激光具有较低的激光能量，可以避免能量较大的激光破坏芯片封装结构中的内部电气结构。可选地，脉冲激光可选择0.01-30W功率范围，以保证在进行脉冲激光退火时可以有效控制激光产生的热量，从而方便对退火效果进行控制。为保证更优的控制效果，可以选择脉冲宽度在1-100ns的范围内，以进一步降低脉冲激光的瞬时能量。
另外，在进行激光退火时，需要从芯片封装结构的载板一侧提供激光，此时需要激光穿透载板，并作用于重布线层上。图3是本发明实施例提供不同波长在硅内穿透深度的曲线图，参考图3，考虑到载板所用硅片的厚度多在几十到几百微米，为了保证激光的穿透效果，可设置脉冲激光的波长不小于800nm。同时为了避免激光的穿透效果过高，而影响退火环境中的其他结构，可限制脉冲激光的波长不大于2μm。
为了在激光退火时配合提供一平整力，使翘曲的重布线层变回平整状态，需要对芯片封装结构施加一均匀压力。可选地，该均匀压力产生的压强范围应在100-1000pa的范围内，其中，压强范围小于100pa时，该均匀压力提供的平整力不足以改变翘曲的重布线层的形态，通过设置均匀压力的压强大于100pa，可以实现对翘曲重布线层的有效挤压，驱使重布线层恢复为平整状态。另外考虑到芯片封装结构强度较小，压强超过1000pa时，容易使芯片封装结构受压迫而损坏，故而可设均匀压力的压强不超过1000pa。
具体地，本发明实施例提供了两种对芯片封装结构施加压力的方式，可分为刚性结构机械式施压和高气压施压两种。图4是本发明实施例提供的另一种芯片封装方法的流程图，图5是图4所示芯片封装方法的结构流程图，参考图4和图5，该芯片封装方法包括：
S210、提供一载板10；
S220、在载板上形成重布线层20；
S230、在重布线层上形成导电凸点结构30；
S240、将芯片40管脚与导电凸点结构30焊接，并形成芯片封装结构50；
S250、将芯片封装结构50放置于一工作台60上，且芯片封装结构50的载板10背离工作台60；
参考图5中步骤e)，其中，工作台60的表面为一平整表面，并且芯片封装结构50会倒扣在工作台60上，即芯片封装结构50中的芯片贴近工作台，而载板10背离工作台，此时激光退火时可从载板10一侧发射激光，通过激光透射载板10实现激光退火处理。
S260、在载板10背离工作台60的一侧放置一透明压板70；
参考图5中步骤f)，其中，透明压板70可以选用刚性的玻璃基板，激光可透过玻璃基板作用在芯片封装结构50上。
S270、向透明压板70施加均匀压力，同时对导电凸点结构50的所在区域进行激光退火。
参考图5中步骤g)，向透明压板70施压均匀压力可以进一步挤压工作台60上的芯片封装结构50，保证芯片封装结构50存在一平整压力。
图6是本发明实施例提供的又一种芯片封装方法的流程图，图7是图6所示芯片封装方法的结构流程图，参考图6和图7，该芯片封装方法包括：
S310、提供一载板10；
S320、在载板10上形成重布线层20；
S330、在重布线层20上形成导电凸点结构30；
S340、将芯片40管脚与导电凸点结构30焊接，并形成芯片封装结构50；
S350、将芯片封装结构50放置于一工作台60上，且芯片封装结构50的载板10背离工作台60；
S360、通过供气装置80在载板10背离工作台60的一侧，向导电凸点结构30的所在区域施加均匀压力，同时对导电凸点结构30的所在区域进行激光退火。
参考图7中步骤f)，其中供气装置80设置在工作台60上方，通过气孔或气道向芯片封装结构50施加气压，利用气压压迫芯片封装结构形成一平整压力。相较于采用透明压板接触式施加压力的方式，气压施压的方式，可以方便调节和控制施加的压力，同时可以减少对芯片封装结构的物理破坏，保护芯片封装结构。需要说明的是，图中所示供气装置80的结构以及施加气压的方式仅为示例，本领域技术人员可以根据具体情况进行设计，此处不做限制。
进一步为了避免芯片封装结构中芯片被激光损伤，可设置工作台具备温度调节功能。可以理解的是，如上所示的两种施压平整力的方式中，均通过将芯片封装结构放置在工作台上，并且芯片封装结构的载板背离工作台，芯片贴近工作台。在进行激光退火的过程中，激光可能穿透载板而作用于芯片上，使芯片升温。此时，可在激光退火时，调节工作台的温度稳定在20-40℃，从而稳定贴近工作台的芯片的温度，避免芯片受激光作用而发生损伤。
激光退火的过程中，会使得芯片封装结构中重布线层的温度发生变化，而在较高温度下，芯片封装结构中的电气结构容易发生氧化或腐蚀，因此，可在导电凸点结构的所在区域施加均匀压力，同时对导电凸点结构的所在区域进行激光退火之前，将芯片封装结构放置于惰性气体环境中。该惰性气体环境可以是氮气环境等。
通常芯片封装结构中，导电凸点结构包括金属导电柱结构，而在重布线层上设置金属导电柱结构时，需要保证金属导电柱结构与重布线层的固定连接。因此，可选地，本发明实施例还提供了一种芯片封装方法，图8是本发明实施例提供的又一种芯片封装结构的流程图，参考图8，该芯片封装结构包括：
S410、提供一载板；
S420、在载板上形成重布线层；
S430、在重布线层上形成金属种子层图案；
重布线层上形成金属导电柱结构时，金属导电柱结构在重布线层上的粘结力较低，容易发生接触不良，为了更好地固定金属导电柱结构，可以先在重布线层上沉积金属种子层，再在金属种子层上制备形成金属导电柱结构，此时金属导电柱结构通过金属种子层与重布线层具有良好的粘接力，可以避免金属导电柱结构的连接不良。
S440、对金属种子层图案的所在区域进行初步激光退火；
金属种子层制备厚度在2-8μm，在形成金属种子层图案时温度升高，重布线层容易在沉积有金属种子层的位置产生形变应力，从而发生翘曲现象，该初步激光退火步骤可以对重布线层进行处理，帮助重布线层释放应力，减缓翘曲现象。
S450、在金属种子层图案上形成金属导电柱图案，其中导电凸点结构包括金属导电柱；
金属导电柱图案通常采用电镀工艺形成，高度约为10-100μm。在电镀过程中同样会发生温度的剧烈变化，此时也容易引起重布线层形变应力集中，而发生翘曲现象。
S460、对金属导电柱图案的所在区域进行初步激光退火；
此时初步激光退火步骤同样可以释放重布线层在金属导电柱图案制备形成时产生的形变应力，削弱翘曲现象。
S470、将芯片管脚与导电凸点结构焊接，并形成芯片封装结构；
S480、在导电凸点结构的所在区域施加均匀压力，同时对导电凸点结构的所在区域进行激光退火。
需要说明的是，在重布线层上形成金属种子层图案之后，对金属种子层图案的所在区域进行初步激光退火的步骤，和在金属种子层图案上形成金属导电柱图案之后，对金属导电柱图案的所在区域进行初步激光退火的步骤，本领域技术人员可根据实际的工艺流程进行选择添加，示例性地，也可以仅在金属导电柱图案形成之后进行初步激光退火步骤，此处不做限制。
为了方便对初步激光退火的效果控制，初步激光退火时也可选择脉冲激光。但由于金属种子层图案和金属导电柱图案形成之后才进行芯片的焊接，因此，在对金属种子层图案和金属导电柱图案进行初步激光退火时，不用考虑激可能对芯片造成损坏，故而可选择连续激光进行退火。在利用连续激光进行退火时同样需要考虑激光有效作用的功率范围，可选地初步激光退火的激光功率范围为1-300mW。另外需要注意的是，由于金属种子层和金属导电柱均为金属材质，并且通常为铜柱结构。图9是本发明实施例提供的金属吸收系数及导热系数曲线，参考图9，铜的导电材料的波长吸收范围小于1μm，为了避免金属导电柱响应初步激光退火时的激光，可选地，初步激光退火的激光波长范围为1-20μm。此时激光退火不会作用在金属种子层，故而激光退火处理不会影响金属导电柱结构。
注意，上述仅为本发明的较佳实施例及所运用技术原理。本领域技术人员会理解，本发明不限于这里所述的特定实施例，对本领域技术人员来说能够进行各种明显的变化、重新调整、相互结合和替代而不会脱离本发明的保护范围。因此，虽然通过以上实施例对本发明进行了较为详细的说明，但是本发明不仅仅限于以上实施例，在不脱离本发明构思的情况下，还可以包括更多其他等效实施例，而本发明的范围由所附的权利要求范围决定。

Claims (11)

1.一种芯片封装方法，其特征在于，包括：
提供一载板；
在所述载板上形成重布线层；
在所述重布线层上形成导电凸点结构；
将芯片管脚与所述导电凸点结构焊接，并形成芯片封装结构；
在所述导电凸点结构的所在区域施加均匀压力，同时对所述导电凸点结构的所在区域进行激光退火；
所述导电凸点结构包括金属导电柱，所述在所述重布线层上形成导电凸点结构，包括：
在所述重布线层上形成金属种子层图案；
在所述金属种子层图案上形成金属导电柱图案；
在所述重布线层上形成金属种子层图案之后，还包括：
对所述金属种子层图案的所在区域进行初步激光退火；
和/或，在所述金属种子层图案上形成金属导电柱图案之后，还包括：
对所述金属导电柱图案的所在区域进行初步激光退火。
2.根据权利要求1所述的芯片封装方法，其特征在于，所述对所述导电凸点结构的所在区域进行激光退火，包括：
采用脉冲激光对所述导电凸点结构的所在区域进行激光退火。
3.根据权利要求2所述的芯片封装方法，其特征在于，所述脉冲激光的波长范围为0.8-2μm。
4.根据权利要求2所述的芯片封装方法，其特征在于，所述脉冲激光的功率范围为0.01-30W。
5.根据权利要求1所述的芯片封装方法，其特征在于，所述在所述导电凸点结构的所在区域施加均匀压力，包括：
将所述芯片封装结构放置于一工作台上，且所述芯片封装结构的所述载板背离所述工作台；
在所述载板背离所述工作台的一侧放置一透明压板；
向所述透明压板施加均匀压力。
6.根据权利要求1所述的芯片封装方法，其特征在于，所述在所述导电凸点结构的所在区域施加均匀压力，包括：
将所述芯片封装结构放置于一工作台上，且所述芯片封装结构的所述载板背离所述工作台；
通过供气装置在所述载板背离工作台的一侧，向所述导电凸点结构的所在区域施加均匀压力。
7.根据权利要求5或6所述的芯片封装方法，其特征在于，所述工作台温度范围在20-40℃。
8.根据权利要求1所述的芯片封装方法，其特征在于，所述均匀压力产生的压强范围为100-1000pa。
9.根据权利要求1所述的芯片封装方法，其特征在于，在所述导电凸点结构的所在区域施加均匀压力，同时对所述导电凸点结构的所在区域进行激光退火之前，还包括：
将所述芯片封装结构放置于惰性气体环境中。
10.根据权利要求1所述的芯片封装方法，其特征在于，所述初步激光退火的激光波长范围为1-20μm。
11.根据权利要求1所述的芯片封装方法，其特征在于，所述初步激光退火的激光功率范围为1-300mW。
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Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1513206A (zh) * 2001-03-28 2004-07-14 ض� 无焊剂倒装芯片互连
JP2007005707A (ja) * 2005-06-27 2007-01-11 Sony Corp 部品接合方法および部品接合用治具
CN101295658A (zh) * 2007-04-24 2008-10-29 三星Techwin株式会社 加热芯片的设备、倒装芯片接合器及接合倒装芯片的方法
KR20120052486A (ko) * 2010-11-16 2012-05-24 주식회사 에이에스티젯텍 레이저를 이용한 전자부품의 본딩 방법 및 장치
JP2012104782A (ja) * 2010-11-15 2012-05-31 Elpida Memory Inc 半導体装置の製造方法および装置
CN104124196A (zh) * 2013-04-23 2014-10-29 中芯国际集成电路制造(上海)有限公司 一种制作半导体器件的方法
TW201606969A (zh) * 2014-08-14 2016-02-16 艾馬克科技公司 用於半導體晶粒互連的雷射輔助接合
CN105637649A (zh) * 2013-10-15 2016-06-01 原子能和代替能源委员会 制造光伏电池的方法
TW201737444A (zh) * 2016-04-15 2017-10-16 艾馬克科技公司 用於半導體晶粒的雷射輔助接合之系統及方法
CN107683522A (zh) * 2015-04-28 2018-02-09 荷兰应用自然科学研究组织Tno 使用闪光灯进行芯片的非接触转移和焊接的设备和方法

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN105374774A (zh) * 2014-08-29 2016-03-02 中芯国际集成电路制造(上海)有限公司 一种半导体器件及其制作方法和电子装置
SG10201903641TA (en) * 2014-10-23 2019-05-30 Agency Science Tech & Res Method of bonding a first substrate and a second substrate
US9508667B2 (en) * 2014-12-23 2016-11-29 Intel Corporation Formation of solder and copper interconnect structures and associated techniques and configurations
US10251272B2 (en) * 2017-06-30 2019-04-02 Intel Corporation Microelectronic devices designed with ultra-high-k dielectric capacitors integrated with package substrates
CN107195607B (zh) * 2017-07-03 2020-01-24 京东方科技集团股份有限公司 一种芯片封装方法及芯片封装结构

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1513206A (zh) * 2001-03-28 2004-07-14 ض� 无焊剂倒装芯片互连
JP2007005707A (ja) * 2005-06-27 2007-01-11 Sony Corp 部品接合方法および部品接合用治具
CN101295658A (zh) * 2007-04-24 2008-10-29 三星Techwin株式会社 加热芯片的设备、倒装芯片接合器及接合倒装芯片的方法
JP2012104782A (ja) * 2010-11-15 2012-05-31 Elpida Memory Inc 半導体装置の製造方法および装置
KR20120052486A (ko) * 2010-11-16 2012-05-24 주식회사 에이에스티젯텍 레이저를 이용한 전자부품의 본딩 방법 및 장치
CN104124196A (zh) * 2013-04-23 2014-10-29 中芯国际集成电路制造(上海)有限公司 一种制作半导体器件的方法
CN105637649A (zh) * 2013-10-15 2016-06-01 原子能和代替能源委员会 制造光伏电池的方法
TW201606969A (zh) * 2014-08-14 2016-02-16 艾馬克科技公司 用於半導體晶粒互連的雷射輔助接合
CN107683522A (zh) * 2015-04-28 2018-02-09 荷兰应用自然科学研究组织Tno 使用闪光灯进行芯片的非接触转移和焊接的设备和方法
TW201737444A (zh) * 2016-04-15 2017-10-16 艾馬克科技公司 用於半導體晶粒的雷射輔助接合之系統及方法

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